[all-commits] [llvm/llvm-project] 7dcca6: [mlir][ArmSVE] Add `arm_sve.zip.x2` and `arm_sve.z...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7dcca6213258bf2df2dd8a7d555c9a12c1484759
      https://github.com/llvm/llvm-project/commit/7dcca6213258bf2df2dd8a7d555c9a12c1484759
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-02-16 (Fri, 16 Feb 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/ArmSVE/IR/ArmSVE.td
    M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
    M mlir/test/Dialect/ArmSVE/invalid.mlir
    M mlir/test/Dialect/ArmSVE/legalize-for-llvm.mlir
    M mlir/test/Dialect/ArmSVE/roundtrip.mlir

  Log Message:
  -----------
  [mlir][ArmSVE] Add `arm_sve.zip.x2` and `arm_sve.zip.x4` ops (#81278)

This adds ops for the two and four-way SME 2 multi-vector zips.

See:

-
https://developer.arm.com/documentation/ddi0602/2023-12/SME-Instructions/ZIP--two-registers---Interleave-elements-from-two-vectors-?lang=en
-
https://developer.arm.com/documentation/ddi0602/2023-12/SME-Instructions/ZIP--four-registers---Interleave-elements-from-four-vectors-?lang=en