[all-commits] [llvm/llvm-project] feee62: [RISCV] Make sure ADDI replacement in optimizeCond...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: feee627974df81e4cbf15537e4c4688aed66b12f
      https://github.com/llvm/llvm-project/commit/feee627974df81e4cbf15537e4c4688aed66b12f
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-15 (Thu, 15 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
    A llvm/test/CodeGen/RISCV/branch-opt.mir

  Log Message:
  -----------
  [RISCV] Make sure ADDI replacement in optimizeCondBranch has a virtual reg destination. (#81938)

If it isn't virtual, we may extend the live range of the physical
register past were it is valid. For example, across a call.

Found while trying to enable -riscv-enable-sink-fold which enables some
copy propagation in machine sink that led to ADDIs with physical
register destinations.