[all-commits] [llvm/llvm-project] f6f8e2: [AArch64][GlobalISel] Refactor Combine G_CONCAT_VE...

[chuongg3 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: f6f8e202f59f54429878f41bcc9aea614613a4af
      https://github.com/llvm/llvm-project/commit/f6f8e202f59f54429878f41bcc9aea614613a4af
  Author: chuongg3 <chuong.goh at arm.com>
  Date:   2024-02-15 (Thu, 15 Feb 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
    M llvm/include/llvm/Target/GlobalISel/Combine.td
    M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
    M llvm/lib/Target/AArch64/AArch64Combine.td
    M llvm/lib/Target/AArch64/GISel/AArch64O0PreLegalizerCombiner.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUPreLegalizerCombiner.cpp
    M llvm/test/CodeGen/AArch64/itofp.ll
    M llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
    M llvm/test/CodeGen/AArch64/vecreduce-add.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Refactor Combine G_CONCAT_VECTOR (#80866)

The combine now works using tablegen and checks if new instruction is
legal before creating it.