[all-commits] [llvm/llvm-project] 02b11c: [𝘀𝗽𝗿] initial version

[Dhruv Chawla (work) via All-commits]

  Branch: refs/heads/users/dc03-work/spr/aarch64globalisel-improve-codegen-for-g_vecreduce_sminsmaxuminumax-for-odd-sized-vectors
  Home:   https://github.com/llvm/llvm-project
  Commit: 02b11c8ae4dd5d00ff6cabf178101a139cfb47e0
      https://github.com/llvm/llvm-project/commit/02b11c8ae4dd5d00ff6cabf178101a139cfb47e0
  Author: Dhruv Chawla <dhruvc at nvidia.com>
  Date:   2024-02-15 (Thu, 15 Feb 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/GlobalISel/LegalizerHelper.h
    M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/aarch64-minmaxv.ll
    M llvm/test/CodeGen/AArch64/vecreduce-umax-legalization.ll

  Log Message:
  -----------
  [𝘀𝗽𝗿] initial version

Created using spr 1.3.5