[all-commits] [llvm/llvm-project] bb7704: [RISCV] Handle fixed length vectors with exact VLE...

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: bb77047a3b93e332be9cb3d85ad658e0ffa25525
      https://github.com/llvm/llvm-project/commit/bb77047a3b93e332be9cb3d85ad658e0ffa25525
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-02-13 (Tue, 13 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll

  Log Message:
  -----------
  [RISCV] Handle fixed length vectors with exact VLEN in loweringEXTRACT_SUBVECTOR (#79949)

This is a revival of #65392. When we lower an extract_subvector, we
extract the
subregister that the subvector is contained in first and then do a
vslidedown
with LMUL=1. We can currently only do this for scalable vectors though
because
the index is scaled by vscale and thus we will know what subregister the
subvector lies in.

For fixed length vectors, the index isn't scaled by vscale and so the
subvector
could lie in any arbitrary subregister, so we have to do a vslidedown
with the
full LMUL.

The exception to this is when we know the exact VLEN: in which case, we
can
still work out the exact subregister and do the LMUL=1 vslidedown on it.

This patch handles this case by scaling the index by 1/vscale before
computing
the subregister, and extending the LMUL=1 path to handle fixed length
vectors.