[all-commits] [llvm/llvm-project] 0b6e04: [RISCV] Exclude X1 and X5 from register scavenging...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0b6e04005ca0eab7c5566950d8595379a9f72d41
      https://github.com/llvm/llvm-project/commit/0b6e04005ca0eab7c5566950d8595379a9f72d41
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-12 (Mon, 12 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  [RISCV] Exclude X1 and X5 from register scavenging for long branch. (#80215)

When a branch target is too far away we need to emit an indirect branch.
We scavenge a register for this since we don't know we need this until
after register allocation.

Jumps using X1 and X5 as the source are hints to the hardware to pop the
return-address stack. We should avoiding using them for jumps that
aren't a return or tail call.