[all-commits] [llvm/llvm-project] ab7025: [mlir][VectorOps] Add vector.interleave operation ...

[Benjamin Maxwell via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ab702513f1ee2268ce216d11c310a08cae24a0e7
      https://github.com/llvm/llvm-project/commit/ab702513f1ee2268ce216d11c310a08cae24a0e7
  Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
  Date:   2024-02-12 (Mon, 12 Feb 2024)

  Changed paths:
    M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
    M mlir/test/Dialect/Vector/ops.mlir

  Log Message:
  -----------
  [mlir][VectorOps] Add vector.interleave operation (#80965)

The interleave operation constructs a new vector by interleaving the
elements from the trailing (or final) dimension of two input vectors,
returning a new vector where the trailing dimension is twice the size.

Note that for the n-D case this differs from the interleaving possible
with `vector.shuffle`, which would only operate on the leading
dimension.

Another key difference is this operation supports scalable vectors,
though currently a general LLVM lowering is limited to the case where
only the trailing dimension is scalable.

Example:
```mlir
%0 = vector.interleave %a, %b
            : vector<[4]xi32>     ; yields vector<[8]xi32>
%1 = vector.interleave %c, %d
            : vector<8xi8>        ; yields vector<16xi8>
%2 = vector.interleave %e, %f
            : vector<f16>         ; yields vector<2xf16>
%3 = vector.interleave %g, %h
            : vector<2x4x[2]xf64> ; yields vector<2x4x[4]xf64>
%4 = vector.interleave %i, %j
            : vector<6x3xf32>     ; yields vector<6x6xf32>
```

Note: This change alone does not add any lowerings.