[all-commits] [llvm/llvm-project] 373d9d: [RISCV] Add sched model for XiangShan-NanHu (#70232)

[Yingwei Zheng via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 373d9d72145cd40c9dc00abefd14632763a2987b
      https://github.com/llvm/llvm-project/commit/373d9d72145cd40c9dc00abefd14632763a2987b
  Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
  Date:   2024-02-12 (Mon, 12 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCV.td
    M llvm/lib/Target/RISCV/RISCVProcessors.td
    A llvm/lib/Target/RISCV/RISCVSchedXiangShanNanHu.td
    A llvm/test/tools/llvm-mca/RISCV/XiangShan/cascade-fma.s
    A llvm/test/tools/llvm-mca/RISCV/XiangShan/gpr-bypass.s
    A llvm/test/tools/llvm-mca/RISCV/XiangShan/load-to-alu.s

  Log Message:
  -----------
  [RISCV] Add sched model for XiangShan-NanHu (#70232)

[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an
open-source high-performance RISC-V processor.

This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of
the XiangShan processor series.
Overview:
https://xiangshan-doc.readthedocs.io/zh-cn/latest/integration/overview/

It is based on the patch [D122556](https://reviews.llvm.org/D122556) by
@SForeKeeper. The original patch hasn't been updated for a long time and
it is out of sync with the current RTL design.

---------

Co-authored-by: SForeKeeper <zkliu6 at gmail.com>