[all-commits] [llvm/llvm-project] d0dbd5: [bazel] Add missing header for 7ec996d4c5c30083b07...
Wang Pengcheng via All-commits
all-commits at lists.llvm.org
Fri Feb 9 04:30:18 PST 2024
Branch: refs/heads/users/wangpc-pp/spr/clangriscv-refactor-builtins-to-tablegen
Home: https://github.com/llvm/llvm-project
Commit: d0dbd50cf0dc85834842380235f445e80516cb59
https://github.com/llvm/llvm-project/commit/d0dbd50cf0dc85834842380235f445e80516cb59
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Add missing header for 7ec996d4c5c30083b070be4898140440094e6b97
Commit: 468b23935a56d2be75c1f86fea97e5620b230a93
https://github.com/llvm/llvm-project/commit/468b23935a56d2be75c1f86fea97e5620b230a93
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Merge TableGenGlobalISel into the tablegen target
These two are intertwined enough so it doesn't really make sense to have
it standalone and hack around it by putting headers into both.
Commit: 395c8175e37248c11ddbffe47294033834b0ec51
https://github.com/llvm/llvm-project/commit/395c8175e37248c11ddbffe47294033834b0ec51
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Put back the pieces of TableGenGlobalISel that unittests depend on
This is a mess and needs to be cleaned up some day.
Commit: 415bf200a725055a3a38e96269f4b752ea6fc330
https://github.com/llvm/llvm-project/commit/415bf200a725055a3a38e96269f4b752ea6fc330
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/lib/ResultAggregator.cpp
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
M llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
M llvm/unittests/tools/llvm-exegesis/ResultAggregatorTest.cpp
M llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp
Log Message:
-----------
[llvm-exegesis] Replace --num-repetitions with --min-instructions (#77153)
This patch replaces --num-repetitions with --min-instructions to make it
more clear that the value refers to the minimum number of instructions
in the final assembled snippet rather than the number of repetitions of
the snippet. This patch also refactors some llvm-exegesis internal
variable names to reflect the name change.
Fixes #76890.
Commit: ca7fd25492388003fab4e19d7e95517bdee2d210
https://github.com/llvm/llvm-project/commit/ca7fd25492388003fab4e19d7e95517bdee2d210
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix a typo from e7d40a87ff230528131541f6ac17a2e1a7dc78e1
Commit: e9e01675a31969d5ae7c250caa6efcc8dcdb80bc
https://github.com/llvm/llvm-project/commit/e9e01675a31969d5ae7c250caa6efcc8dcdb80bc
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/HLFIR/invalid.fir
M flang/test/Lower/HLFIR/minval.f90
Log Message:
-----------
[flang][HLFIR] Relax verifiers of intrinsic operations (#80132)
The verifiers are currently very strict: requiring intrinsic operations
to be used only in cases where the Fortran standard permits the
intrinsic to be used.
There have now been a lot of cases where these verifiers have caused
bugs in corner cases. In a recent ticket, @jeanPerier pointed out that
it could be useful for future optimizations if somewhat invalid uses of
these operations could be allowed in dead code. See this comment:
https://github.com/llvm/llvm-project/issues/79995#issuecomment-1918118234
In response to all of this, I have decided to relax the intrinsic
operation verifiers. The intention is now to only disallow operation
uses that are likely to crash the compiler. Other checks are still
available under `-strict-intrinsic-verifier`.
The disadvantage of this approach is that IR can now represent intrinsic
invocations which are incorrect. The lowering and implementation of
these intrinsic functions is unlikely to do the right thing in all of
these cases, and as they should mostly be impossible to generate using
normal Fortran code, these edge cases will see very little testing,
before some new optimization causes them to become more common.
Fixes #79995
Commit: 1bbb797e9c7f37aa814b9bbaba2961f730a26891
https://github.com/llvm/llvm-project/commit/1bbb797e9c7f37aa814b9bbaba2961f730a26891
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/aarch64-target-features.c
Log Message:
-----------
[Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR (#80163)
This updates clang's target defines to include the ACLE changes covering
the FEAT_PAuth_LR architecture extension.
The changes include:
* The new `__ARM_FEATURE_PAUTH_LR` feature macro, which is set to 1 when
FEAT_PAuth_LR is available in the target.
* A new bit field for the existing `__ARM_FEATURE_PAC_DEFAULT` macro,
indicating the use of PC as a diversifier for Pointer Authentication
(from -mbranch-protection=pac-ret+pc).
The approved changes to the ACLE spec can be found here:
https://github.com/ARM-software/acle/pull/292
Commit: f34418c73b718abb24cd5b921b5a2846011e7d0c
https://github.com/llvm/llvm-project/commit/f34418c73b718abb24cd5b921b5a2846011e7d0c
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/IR/DebugInfoMetadata.cpp
Log Message:
-----------
[HWASAN] Remove DW_OP_LLVM_tag_offset from DIExpression::isImplicit (#79816)
According to its doc-comment `isImplicit` is meant to return true if the
expression is an implicit location description (describes an object or part of
an object which has no location by computing the value from available program
state).
There's a brief entry for `DW_OP_LLVM_tag_offset` in the LangRef and there's
some info in the original commit fb9ce100d19be130d004d03088ccd4af295f3435.
>From what I can tell it doesn't look like `DW_OP_LLVM_tag_offset` affects
whether or not the location is implicit; the opcode doesn't get included in the
final location description but instead is added as an attribute to the variable.
This was tripping an assertion in the latest application of the fix to #76545,
#78606, where an expression containing a `DW_OP_LLVM_tag_offset` is split into
a fragment (i.e., describe a part of the whole variable).
Commit: 96a3d05ed923d2abd51acb52984b83b9e8044924
https://github.com/llvm/llvm-project/commit/96a3d05ed923d2abd51acb52984b83b9e8044924
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub][workflows] Reflow some text in buildbot info PR comment
When the markdown link renders the line gets a lot shorter.
Commit: b5c0b67bc270936c8fa254dc42d920e867adef54
https://github.com/llvm/llvm-project/commit/b5c0b67bc270936c8fa254dc42d920e867adef54
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64.cl
Log Message:
-----------
[AMDGPU] Check wavefrontsize for GFX11 WMMA builtins (#79980)
Commit: da437330beca0411912ca46f2d5ef1e46403acbd
https://github.com/llvm/llvm-project/commit/da437330beca0411912ca46f2d5ef1e46403acbd
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/IndVarSimplify/iv-poison.ll
Log Message:
-----------
[SCEVExp] Keep NUW/NSW if both original inc and isomporphic inc agree. (#79512)
We are replacing with a wider increment. If both OrigInc and
IsomorphicInc are NUW/NSW, then we can preserve them on the wider
increment; the narrower IsomorphicInc would wrap before the wider
OrigInc, so the replacement won't make IsomorphicInc's uses more
poisonous.
PR: https://github.com/llvm/llvm-project/pull/79512
Commit: 7d78ccf7d5a9861839126d5899b443f55236cab9
https://github.com/llvm/llvm-project/commit/7d78ccf7d5a9861839126d5899b443f55236cab9
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__memory/allocate_at_least.h
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/memory
M libcxx/include/version
M libcxx/modules/std/memory.inc
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
R libcxx/test/std/utilities/memory/allocator.traits/allocate_at_least.pass.cpp
A libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_at_least.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++][memory] P2652R2: Disallow Specialization of `allocator_traits` (#79978)
Implements P2652R2 <https://wg21.link/P2652R2>:
- https://eel.is/c++draft/allocator.requirements.general
- https://eel.is/c++draft/memory.syn
- https://eel.is/c++draft/allocator.traits.general
- https://eel.is/c++draft/allocator.traits.members
- https://eel.is/c++draft/diff.cpp20.concepts
- https://eel.is/c++draft/diff.cpp20.utilities
---------
Co-authored-by: Zingam <zingam at outlook.com>
Commit: ea2984287d91b96f5e2cc0aa66d146d6dbd1d1bb
https://github.com/llvm/llvm-project/commit/ea2984287d91b96f5e2cc0aa66d146d6dbd1d1bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/CodeGen/ARM/popcnt.ll
Log Message:
-----------
[ARM] Add ctpop codegen tests
Commit: c105848fd29d3b46eeb794bb6b10dad04f903b09
https://github.com/llvm/llvm-project/commit/c105848fd29d3b46eeb794bb6b10dad04f903b09
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[IndVars] Add tests for #79861 (NFC)
Commit: 178719e86043c1e830a7e24de027a84f6f8ea28f
https://github.com/llvm/llvm-project/commit/178719e86043c1e830a7e24de027a84f6f8ea28f
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
Log Message:
-----------
[RISCV][NFC] Simplify calls.ll and autogenerate checks for tail-calls.ll
Split out from #78417.
Reviewers: topperc, asb, kito-cheng
Reviewed By: asb
Pull Request: https://github.com/llvm/llvm-project/pull/79248
Commit: d2565bb11308f6cf98d838e828d9bcbe2d51e0e4
https://github.com/llvm/llvm-project/commit/d2565bb11308f6cf98d838e828d9bcbe2d51e0e4
Author: Alexandre Ganea <37383324+aganea at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/cmake/HandleOpenMPOptions.cmake
Log Message:
-----------
[openmp] On Windows, fix standalone cmake build (#80174)
This fixes: https://github.com/llvm/llvm-project/issues/80117
Commit: f956e7fbf161447b9236f7c4448a9d02d3564261
https://github.com/llvm/llvm-project/commit/f956e7fbf161447b9236f7c4448a9d02d3564261
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
Log Message:
-----------
[AMDGPU] Prefer `s_memtime` for `readcyclecounter` on GFX10 (#80211)
Summary:
The old `s_memtime` instruction was supported until the GFX10
architecture. Although this instruction has a higher latency than the
new shader counter, it's much more usable as a processor clock as it is
a full 64-bit counter. The new shader counter is only a 20-bit counter,
which makes it difficult to use as a standard cycle counter as it will
overflow in a few milliseconds. This patch suggests preferring
`s_memtime` for this instrinsic if it is still available.
Commit: d313614b60ff1194f48e5f0b1bb8d63d2b7eb52d
https://github.com/llvm/llvm-project/commit/d313614b60ff1194f48e5f0b1bb8d63d2b7eb52d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
M clang/test/Modules/aarch64-sme-keywords.cppm
M llvm/docs/AArch64SME.rst
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
M llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call-remarks.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
M llvm/test/CodeGen/AArch64/sme-new-za-function.ll
M llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
M llvm/test/Transforms/Inline/AArch64/sme-pstateza-attrs.ll
M llvm/test/Verifier/sme-attributes.ll
M llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
M mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/ArmSME/enable-arm-za.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[AArch64] Replace LLVM IR function attributes for PSTATE.ZA. (#79166)
Since https://github.com/ARM-software/acle/pull/276 the ACLE
defines attributes to better describe the use of a given SME state.
Previously the attributes merely described the possibility of it being
'shared' or 'preserved', whereas the new attributes have more semantics
and also describe how the data flows through the program.
For ZT0 we already had to add new LLVM IR attributes:
* aarch64_new_zt0
* aarch64_in_zt0
* aarch64_out_zt0
* aarch64_inout_zt0
* aarch64_preserves_zt0
We have now done the same for ZA, such that we add:
* aarch64_new_za (previously `aarch64_pstate_za_new`)
* aarch64_in_za (more specific variation of `aarch64_pstate_za_shared`)
* aarch64_out_za (more specific variation of `aarch64_pstate_za_shared`)
* aarch64_inout_za (more specific variation of
`aarch64_pstate_za_shared`)
* aarch64_preserves_za (previously `aarch64_pstate_za_shared,
aarch64_pstate_za_preserved`)
This explicitly removes 'pstate' from the name, because with SME2 and
the new ACLE attributes there is a difference between "sharing ZA"
(sharing
the ZA matrix register with the caller) and "sharing PSTATE.ZA" (sharing
either the ZA or ZT0 register, both part of PSTATE.ZA with the caller).
Commit: 5d41788f3798da5ea91dc6cac86e3d9eebdee3ce
https://github.com/llvm/llvm-project/commit/5d41788f3798da5ea91dc6cac86e3d9eebdee3ce
Author: David Green <david.green at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/test/CodeGen/AArch64/select_fmf.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
Log Message:
-----------
[AArch64] Alter latency of FCSEL under Cortex-A510 (#80178)
As per the Cortex-A510 software optimization guide, the latency of a
fcsel should be 3 not 4. It would previously get the latency from
WriteF.
Commit: c3eb2978a60b4e2e0cf9c8a8f9c51b48bd49477a
https://github.com/llvm/llvm-project/commit/c3eb2978a60b4e2e0cf9c8a8f9c51b48bd49477a
Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
Log Message:
-----------
[mlir][scf] Considering defining operators of indices when fusing scf::ParallelOp (#80145)
When checking the load indices of the second loop coincide with the
store indices of the first loop, it only considers the index values are
the same or not. However, there are some cases the index values defined
by other operators. In these cases, it will treat them as different even
the results of defining operators are the same.
We already check if the iteration space is the same in isFusionLegal().
When checking operands of defining operators, we only need to consider
the operands come from the same induction variables. If so, we know the
results of defining operators are the same.
Commit: 112fba974ce42a6e552f7391d20a858a128283a1
https://github.com/llvm/llvm-project/commit/112fba974ce42a6e552f7391d20a858a128283a1
Author: Quentin Dian <dianqk at dianqk.net>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/ARM/cmpxchg.mir
M llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
M llvm/test/CodeGen/MIR/X86/unreachable-block-print.mir
M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
M llvm/test/CodeGen/PowerPC/branch_coalescing.mir
M llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
M llvm/test/CodeGen/PowerPC/nofpexcept.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/Thumb2/cmpxchg.mir
M llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
M llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir
M llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
M llvm/test/CodeGen/X86/cse-two-preds.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
Log Message:
-----------
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
Per #80143, we can remove the extra line break when there is no
instruction.
Commit: 15295d01352c922f1dfe564d801d556cf5fe01b3
https://github.com/llvm/llvm-project/commit/15295d01352c922f1dfe564d801d556cf5fe01b3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Introduce and use computeCommonAlignment function, NFC.
Commit: 2a50921553798d2db52ca6330c89f0f8a5bc2215
https://github.com/llvm/llvm-project/commit/2a50921553798d2db52ca6330c89f0f8a5bc2215
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-char.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-double.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-float.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-int.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll
A llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-short.ll
Log Message:
-----------
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
This patch utilizes the -maix-small-local-exec-tls option to produce a
faster,
non-TOC-based access sequence for the local-exec TLS model.
Specifically, for
when the offsets from the TLS variable are non-zero.
In particular, this patch produces either a single:
- addi/la with a displacement off of R13 plus a non-zero offset for when
an address is calculated, or
- load or store off of R13 plus a non-zero offset for when an address is
calculated and used for further
access where R13 is the thread pointer, respectively.
In order to produce a single addi or load/store off of the thread
pointer with a non-zero offset,
this patch also adds the necessary support in the assembly printer when
printing these instructions.
Specifically:
- The non-zero offset is added to the TLS variable address when the
address of the
TLS variable + it's offset is less than 32KB.
- Otherwise, when the address of the TLS variable + its offset is
greater than 32KB, the
non-zero offset (and a multiple of 64KB) is subtracted from the TLS
address.
This handling in the assembly printer is necessary to ensure that the
TLS address + the non-zero offset
is between [-32768, 32768), so that the total displacement can fit
within the addi/load/store instructions.
This patch is meant to be a follow-up to
3f46e5453d9310b15d974e876f6132e3cf50c4b1 (where the
optimization occurs for when the offset is zero).
Commit: 40f6b7d4761657cebd383b102ff3e6e612337f01
https://github.com/llvm/llvm-project/commit/40f6b7d4761657cebd383b102ff3e6e612337f01
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Log Message:
-----------
[PowerPC] Fix -Wunused-variable in PPCAsmPrinter.cpp and PPCISelDAGToDAG.cpp (NFC)
llvm-project/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1648:15:
error: unused variable 'InstDisp' [-Werror,-Wunused-variable]
ptrdiff_t InstDisp = TLSVarAddress + Offset - Delta;
^
llvm-project/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:7624:19:
error: unused variable 'TPReg' [-Werror,-Wunused-variable]
RegisterSDNode *TPReg = dyn_cast<RegisterSDNode>(TPRegNode.getNode());
^
llvm-project/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:7625:23:
error: unused variable 'Subtarget' [-Werror,-Wunused-variable]
const PPCSubtarget &Subtarget =
^
Commit: f7b05e055fa63e1c4b5ae5e391b654b57161a0e4
https://github.com/llvm/llvm-project/commit/f7b05e055fa63e1c4b5ae5e391b654b57161a0e4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/Transforms/LoopUnroll/runtime-i128.ll
Log Message:
-----------
[LoopUnroll] Add test for #80289 (NFC)
Commit: 62ae7d976f494f3dbd297331b19cd1204750de6f
https://github.com/llvm/llvm-project/commit/62ae7d976f494f3dbd297331b19cd1204750de6f
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/test/Transforms/LoopUnroll/runtime-i128.ll
Log Message:
-----------
[LoopUnroll] Fix missing sign extension
For integers larger than 64-bit, this would zero-extend a -1
value, instead of sign-extending it.
Fixes https://github.com/llvm/llvm-project/issues/80289.
Commit: 3c64b24ed35fe6bb4a7a1fe304089e6069fcd14d
https://github.com/llvm/llvm-project/commit/3c64b24ed35fe6bb4a7a1fe304089e6069fcd14d
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Profile/StaleProfileMatching.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
Log Message:
-----------
[BOLT] Add extra staleness logging (#80225)
Report two extra metrics:
- # of stale functions with matching block count,
- # of stale blocks with matching instruction count.
Commit: fcd3752342ebd193d4eef39b9c0730599eca4486
https://github.com/llvm/llvm-project/commit/fcd3752342ebd193d4eef39b9c0730599eca4486
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/test/Driver/rocm-detect.hip
Log Message:
-----------
[HIP] fix HIP detection for /usr (#80190)
Skip checking HIP version file under parent directory for /usr/local
since /usr will be checked after /usr/local.
Fixes: https://github.com/llvm/llvm-project/issues/78344
Commit: 6050cf28846e5be2c162108f1a024d5ff25d5637
https://github.com/llvm/llvm-project/commit/6050cf28846e5be2c162108f1a024d5ff25d5637
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
Log Message:
-----------
[mlir][scf] Add reductions support to `scf.parallel` fusion (#75955)
Properly handle fusion of loops with reductions:
* Check there are no first loop results users between loops
* Create new loop op with merged reduction init values
* Update `scf.reduce` op to contain reductions from both loops
* Update loops users with new loop results
Commit: 390d66b03b5a5e352b7d696aaed679a2deb25c6c
https://github.com/llvm/llvm-project/commit/390d66b03b5a5e352b7d696aaed679a2deb25c6c
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Log Message:
-----------
[LSR] Add tests for restricting term-fold budget based on exact trip count
Commit: 6ac4fe8de014336ce66d02ddd07e85db3b8e77a2
https://github.com/llvm/llvm-project/commit/6ac4fe8de014336ce66d02ddd07e85db3b8e77a2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants.cpp - refactor constant search loop to take array of sorted candidates
Pulled out of #79815 - refactors the internal FixupConstant logic to just accept an array of vzload/broadcast candidates that are pre-sorted in ascending constant pool size
Commit: 9acd61ec1999ac3a54371d0a8b9d922ef5ca2b50
https://github.com/llvm/llvm-project/commit/9acd61ec1999ac3a54371d0a8b9d922ef5ca2b50
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/test/SemaCXX/datasizeof.cpp
Log Message:
-----------
[Sema] Fix crash in __datasizeof with unknown types (#80300)
Fixes #80284.
Calling `getASTRecordLayout` on invalid types may crash and results of
`__datasizeof` on invalid types can be arbitrary, so just use whatever
`sizeof` returns.
Commit: c5f461918cece4362fb70c7b16de4e95c1af8e5f
https://github.com/llvm/llvm-project/commit/c5f461918cece4362fb70c7b16de4e95c1af8e5f
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Parse/Parser.cpp
M clang/test/CXX/temp/p3.cpp
M clang/test/OpenMP/declare_simd_messages.cpp
Log Message:
-----------
[Clang][Parse] Diagnose member template declarations with multiple declarators (#78243)
According to [temp.pre] p5:
> In a template-declaration, explicit specialization, or explicit instantiation the init-declarator-list in the declaration shall contain at most one declarator.
A member-declaration that is a template-declaration or explicit-specialization contains a declaration, even though it declares a member. This means it _will_ contain an init-declarator-list (not a member-declarator-list), so [temp.pre] p5 applies.
This diagnoses declarations such as:
```
struct A
{
template<typename T>
static const int x = 0, f(); // error: a template declaration can only declare a single entity
template<typename T>
static const int g(), y = 0; // error: a template declaration can only declare a single entity
};
```
The diagnostic messages are the same as those of the equivalent namespace scope declarations.
Note: since we currently do not diagnose declarations with multiple abbreviated function template declarators at namespace scope e.g., `void f(auto), g(auto);`, so this patch does not add diagnostics for the equivalent member declarations.
This patch also refactors `ParseSingleDeclarationAfterTemplate` (now named `ParseDeclarationAfterTemplate`) to call `ParseDeclGroup` and return the resultant `DeclGroup`.
Commit: a52eea66795018550e95c4b060165a7250899298
https://github.com/llvm/llvm-project/commit/a52eea66795018550e95c4b060165a7250899298
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aarch64-targetattr.c
M clang/test/Preprocessor/aarch64-target-features.c
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)
Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.
After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.
The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.
Commit: bed3608c22fbd3afbdbc782f04e8c9c6e6e8fa18
https://github.com/llvm/llvm-project/commit/bed3608c22fbd3afbdbc782f04e8c9c6e6e8fa18
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT][NFC] Factor out RI::disassemblePLTInstruction (#80302)
Commit: 4eb0810922a8d6ad9a32fbf09326166317dc5c08
https://github.com/llvm/llvm-project/commit/4eb0810922a8d6ad9a32fbf09326166317dc5c08
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm-objdump][AMDGPU] Pass ELF ABIVersion through disassembler (#78907)
Admittedly, its a bit ugly to pass the ABIVersion through onSymbolStart
but I'm not sure what a better place for it would be.
Commit: 09b4649ea5cefc4f93d9c936d38863df5c6568ed
https://github.com/llvm/llvm-project/commit/09b4649ea5cefc4f93d9c936d38863df5c6568ed
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertCall.cpp
M flang/test/Lower/HLFIR/procedure-pointer.f90
Log Message:
-----------
[flang] Fix passing NULL to OPTIONAL procedure pointers (#80267)
Procedure pointer lowering used `prepareUserCallActualArgument` because
it was convenient, but this helper was not meant for POINTERs when
originally written and it did not handled passing NULL to an OPTIONAL
procedure pointer correctly.
The resulting argument should be a disassociated pointer, not an absent
pointer (Fortran 15.5.2.12 point 1.).
Move the logic for procedure pointer argument "cooking" in its own
helper to avoid triggering the logic that created an absent argument in
this case.
Commit: bfdd78233fba4623366bbef5631ff0ebab29c42e
https://github.com/llvm/llvm-project/commit/bfdd78233fba4623366bbef5631ff0ebab29c42e
Author: Kevin Frei <kevinfrei at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DIContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/test/DebugInfo/X86/skeleton-unit-verify.s
M llvm/test/DebugInfo/dwarfdump-accel.test
M llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes_no_files.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_file_encoding.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_overlapping_cu_ranges.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_parent_zero_length.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_split_cu.s
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
Log Message:
-----------
Aggregate errors from llvm-dwarfdump --verify (#79648)
The amount and format of output from `llvm-dwarfdump --verify` makes it
quite difficult to know if a change to a tool that produces or modifies
DWARF is causing new problems, or is fixing existing problems. This diff
adds a categorized summary of issues found by the DWARF verifier, on by
default, at the bottom of the error output.
The change includes a new `--error-display` option with 4 settings:
* `--error-display=quiet`: Only display if errors occurred, but no
details or summary are printed.
* `--error-display=summary`: Only display the aggregated summary of
errors with no error detail.
* `--error-display=details`: Only display the detailed error messages
with no summary (previous behavior)
* `--error-display=full`: Display both the detailed error messages and
the aggregated summary of errors (the default)
I changed a handful of tests that were failing due to new output, adding
the flag to use the old behavior for all but a couple. For those two I
added the new aggregated output to the expected output of the test.
The `OutputCategoryAggregator` is a pretty simple little class that
@clayborg suggested to allow code to only be run to dump detail if it's
enabled, while still collating counts of the category. Knowing that the
lambda passed in is only conditionally executed is pretty important
(handling errors has to be done *outside* the lambda). I'm happy to move
this somewhere else (and change/improve it) to be more broadly useful if
folks would like.
---------
Co-authored-by: Kevin Frei <freik at meta.com>
Commit: 4739a97faedf766541245e6a5b48595d4a3deaae
https://github.com/llvm/llvm-project/commit/4739a97faedf766541245e6a5b48595d4a3deaae
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Log Message:
-----------
[Clang][NFC] Remove TemplateArgumentList::OnStack (#79760)
This patch removes on-stack `TemplateArgumentList`'s. They were primary used
to pass an `ArrayRef<TemplateArgument>` to
`Sema::getTemplateInstantiationArgs`, which had a `const
TemplateArgumentList*` parameter for the innermost template argument
list. Changing this parameter to an
`std::optional<ArrayRef<TemplateArgument>>` eliminates the need for
on-stack `TemplateArgumentList`'s, which in turn eliminates the need for
`TemplateArgumentList` to store a pointer to its template argument
storage (which is redundant in almost all cases, as it is an AST
allocated type).
Commit: 548d132b9457aa5223ee87d2306a7bec30da93d2
https://github.com/llvm/llvm-project/commit/548d132b9457aa5223ee87d2306a7bec30da93d2
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/cmake/modules/LLVMLibCLibraryRules.cmake
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
Log Message:
-----------
[libc][NFC] Refactor FLAGS expansion using cmake_language(CALL ...). (#80156)
Commit: 46068f5e8d318c67d0b9088ed751e09473776a0d
https://github.com/llvm/llvm-project/commit/46068f5e8d318c67d0b9088ed751e09473776a0d
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
Log Message:
-----------
[NFC] Reorder test lines in arith-fp-frem.ll (#79991)
Run lines appear in a more natural order:
- no veclib (neon, sve)
- neon + veclib
- sve + veclib
- sve + tailfold + veclib
Commit: 7b9bf80ab51b9b09d9f07fb636f4b64581a3c3e0
https://github.com/llvm/llvm-project/commit/7b9bf80ab51b9b09d9f07fb636f4b64581a3c3e0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
Log Message:
-----------
[SLP][NFC]Add tests with strided loads, NFC.
Commit: 7e7f118404cdfbee9eaf7c05ab8ea54a25b52aa4
https://github.com/llvm/llvm-project/commit/7e7f118404cdfbee9eaf7c05ab8ea54a25b52aa4
Author: XDeme <tagawafernando at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Handles Elaborated type specifier for enum in trailing return (#80085)
Fixes llvm/llvm-project#80062
Commit: e0e6236fd61f906f8529dcaa8ecd0beec1f5a18a
https://github.com/llvm/llvm-project/commit/e0e6236fd61f906f8529dcaa8ecd0beec1f5a18a
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
A lldb/test/API/commands/target/debuginfo/TestDebugInfoSize.py
A lldb/test/API/commands/target/debuginfo/a.out-foo.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out-main.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out.yaml
Log Message:
-----------
Fix debug info size statistics for split dwarf (#80218)
`statistics dump` command relies on `SymbolFile::GetDebugInfoSize()` to
get total debug info size.
The current implementation is missing debug info for split dwarf
scenarios which requires getting debug info from separate dwo/dwp files.
This patch fixes this issue for split dwarf by parsing debug info from
dwp/dwo.
New yaml tests are added.
---------
Co-authored-by: jeffreytan81 <jeffreytan at fb.com>
Commit: 28699e385681e7f0aeefc208b7b59d6f1d484800
https://github.com/llvm/llvm-project/commit/28699e385681e7f0aeefc208b7b59d6f1d484800
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/include/errno.h.def
M libc/src/errno/CMakeLists.txt
M libc/src/errno/libc_errno.cpp
M libc/src/errno/libc_errno.h
M libc/test/integration/startup/linux/tls_test.cpp
M libc/test/src/errno/errno_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/sys/mman/linux/madvise_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mmap_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
Log Message:
-----------
[libc] Update libc_errno to work correctly in both overlay and full build modes. (#80177)
Commit: 1f3c30911cc5eee4b42bdc9c6358c689b2f2f223
https://github.com/llvm/llvm-project/commit/1f3c30911cc5eee4b42bdc9c6358c689b2f2f223
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
Log Message:
-----------
[AMDGPU] Mark PC_ADD_REL_OFFSET rematerializable (#79674)
Currently machine LICM hoist PC_ADD_REL_OFFSET out of loops, causes
register pressure when function calls are deep in loops. This is a main
cause of sgpr spill for programs containing large number of function
calls in loops.
This patch marks PC_ADD_REL_OFFSET as rematerializable, which eliminates
sgpr spills due to function calls in loops.
Commit: 94166c6ea1574372521f54d72522b81cc85cdbb6
https://github.com/llvm/llvm-project/commit/94166c6ea1574372521f54d72522b81cc85cdbb6
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/integration/startup/linux/tls_test.cpp
Log Message:
-----------
[libc] Fix wrong errno number in tls_test. (#80312)
Commit: 87e04b471e8c52991c4100a270d4b59a84b7c48d
https://github.com/llvm/llvm-project/commit/87e04b471e8c52991c4100a270d4b59a84b7c48d
Author: Matin Raayai <30674652+matinraayai at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
Log Message:
-----------
Fix Passing TargetOptions by Value in TargetMachines for AMDGPU (#79866)
`TargetOptions` is currently passed by value in AMDGPU targets, which
makes unnecessary copies. This PR fixes this issue.
Commit: de1ea787ed70ff376a1ff3b4262d0e25e4d135f2
https://github.com/llvm/llvm-project/commit/de1ea787ed70ff376a1ff3b4262d0e25e4d135f2
Author: Mike Rice <michael.p.rice at intel.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/decomposition-openmp.cpp
Log Message:
-----------
[OpenMP] Move unsupported structured bindings diagnostic (#80216)
Move the diagnostic so it fires only when doing an OpenMP capture, not
for non-OpenMP captures. This allows non-OpenMP code to work when using
OpenMP elsewhere, such as the code reported in
https://github.com/llvm/llvm-project/issues/66999.
Commit: ecb5a1b0e236a98f59863793b4cfef1f13ea225c
https://github.com/llvm/llvm-project/commit/ecb5a1b0e236a98f59863793b4cfef1f13ea225c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/experimental/__memory
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++][NFC] Remove <experimental/__memory> (#80194)
The header is unused now, so we can remove it.
Commit: 6a3fde6d600cccd2ffbede6dd54519036cc4089c
https://github.com/llvm/llvm-project/commit/6a3fde6d600cccd2ffbede6dd54519036cc4089c
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/stdbit.rst
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/CMakeLists.txt
A libc/src/stdbit/stdc_leading_ones_uc.cpp
A libc/src/stdbit/stdc_leading_ones_uc.h
A libc/src/stdbit/stdc_leading_ones_ui.cpp
A libc/src/stdbit/stdc_leading_ones_ui.h
A libc/src/stdbit/stdc_leading_ones_ul.cpp
A libc/src/stdbit/stdc_leading_ones_ul.h
A libc/src/stdbit/stdc_leading_ones_ull.cpp
A libc/src/stdbit/stdc_leading_ones_ull.h
A libc/src/stdbit/stdc_leading_ones_us.cpp
A libc/src/stdbit/stdc_leading_ones_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/CMakeLists.txt
A libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
Log Message:
-----------
[libc] implement stdc_leading_ones (C23) (#80082)
Commit: 10a55caccf4e2d397f94c1455b93d774591be45f
https://github.com/llvm/llvm-project/commit/10a55caccf4e2d397f94c1455b93d774591be45f
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv-inline-asm.c
M clang/test/Sema/inline-asm-validate-riscv.c
M llvm/docs/LangRef.rst
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
R llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
A llvm/test/CodeGen/RISCV/inline-asm-s-constraint-error.ll
A llvm/test/CodeGen/RISCV/inline-asm-s-constraint.ll
Log Message:
-----------
[RISCV] Support constraint "s" (#80201)
GCC has supported a generic constraint "s" for a long time (since at
least 1992), which references a symbol or label with an optional
constant offset. "i" is a superset that also supports a constant
integer.
GCC's RISC-V port also supports a machine-specific constraint "S",
which cannot be used with a preemptible symbol. (We don't bother to
check preemptibility.) In PIC code, an external symbol is preemptible by
default, making "S" less useful if you want to create an artificial
reference for linker garbage collection, or define sections to hold
symbol addresses:
```
void fun();
// error: impossible constraint in ‘asm’ for riscv64-linux-gnu-gcc -fpie/-fpic
void foo() { asm(".reloc ., BFD_RELOC_NONE, %0" :: "S"(fun)); }
// good even if -fpie/-fpic
void foo() { asm(".reloc ., BFD_RELOC_NONE, %0" :: "s"(fun)); }
```
This patch adds support for "s". Modify https://reviews.llvm.org/D105254
("S") to handle multi-depth GEPs (https://reviews.llvm.org/D61560).
Commit: f0c8d88e25dbed02605994da227dfa75c1304d4a
https://github.com/llvm/llvm-project/commit/f0c8d88e25dbed02605994da227dfa75c1304d4a
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/MachO/ObjC.cpp
M lld/test/MachO/objc-category-conflicts.s
Log Message:
-----------
[lld-macho] Make ObjC category checker print the source file name of category (#80221)
When printing category conflicts in the ObjC category checker, also
print the source file name of the problematic categories. Currently we
only print the object file name. This change is mostly useful only for
thinLTO builds, where the object file name will be of form
999.arm64.lto.o and thus does not reveal any information about the
original source file.
---------
Co-authored-by: Alex Borcan <alexborcan at meta.com>
Commit: cc0c8e592f8ff58ab821a04b7dcfb71403b4bea6
https://github.com/llvm/llvm-project/commit/cc0c8e592f8ff58ab821a04b7dcfb71403b4bea6
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp
Log Message:
-----------
[OpenMP] Fix build breakage (NFC) (#80313)
Assign `nullptr` to the pointer instead.
Commit: 58b87300ecaac71e237cefec80d3934610f55fbd
https://github.com/llvm/llvm-project/commit/58b87300ecaac71e237cefec80d3934610f55fbd
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Conversion/SCFToEmitC/SCFToEmitC.h
Log Message:
-----------
[mlir][EmitC] Harmonize include guard (NFC)
Harmonizes the include guard as it is rather uncommon within the MLIR
subproject to append an underscore to include guards.
Commit: ef7f6aca149c88089ec4964e87889f3709321f03
https://github.com/llvm/llvm-project/commit/ef7f6aca149c88089ec4964e87889f3709321f03
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Add some extra checks/reorganize the code to improve compile time, NFC.
Commit: e296cedcd686e24fee75756185669f1bb3b47fdd
https://github.com/llvm/llvm-project/commit/e296cedcd686e24fee75756185669f1bb3b47fdd
Author: Brendan Sweeney <brs at eecs.berkeley.edu>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/RISCV/rv32zalasr-invalid.s
A llvm/test/MC/RISCV/rv32zalasr-valid.s
A llvm/test/MC/RISCV/rv64zalasr-invalid.s
A llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
This PR implements experimental support for the RISC-V Atomic
Load-Acquire and Store-Release Extension (Zalasr). It has been approved
to be pursued as a fast track extension
(https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698),
but has not yet been approved by ARC or ratified. See
https://github.com/mehnadnerd/riscv-zalasr for draft spec.
---------
Co-authored-by: brs <turtwig at utexas.edu>
Co-authored-by: Philip Reames <preames at rivosinc.com>
Commit: 20a9fa3e145999d7cb0d311c832ee6c72fc276fb
https://github.com/llvm/llvm-project/commit/20a9fa3e145999d7cb0d311c832ee6c72fc276fb
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
Log Message:
-----------
[mlir][sparse] add sparsification options to pretty print and debug s… (#80205)
…parse loops.
Commit: 41be5412e2da0235811af24b10eb2dacab03f8b5
https://github.com/llvm/llvm-project/commit/41be5412e2da0235811af24b10eb2dacab03f8b5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/MC/RISCV/supervisor-csr-names.s
Log Message:
-----------
[RISCV] Add srmcfg CSR from Ssqosid extension. (#79914)
Based on the spec here
https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1
Ssqosid extension name will be added in a separate patch.
Commit: 10c2d5ff7c6de8096c8f4c4621612970940f6dd3
https://github.com/llvm/llvm-project/commit/10c2d5ff7c6de8096c8f4c4621612970940f6dd3
Author: Jiahan Xie <88367305+jiahanxie353 at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
Log Message:
-----------
[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)
RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.
Commit: f883365cc7600cf1c29b36343f2f8cdbe3394881
https://github.com/llvm/llvm-project/commit/f883365cc7600cf1c29b36343f2f8cdbe3394881
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/include/stdbit_test.cpp
Log Message:
-----------
[libc] fix stdbit include test when not all entrypoints are available (#80323)
The intent of the test is to check that: 1. The type generic macros are
defined. 2. Those macros dispatch to the correct underlying function.
The issue is that when new functionality is added to our stdbit.h without
rolling out the new entrypoint to all targets, this test breaks because our
generated stdbit.h will not contain declarations for the underlying function.
In that case, we should just declare the underlying functions first before
including our generated stdbit.h which just contains declarations. A definition
is a declaration, but redeclarations must match, hence the additions of
noexcept and extern "C".
Commit: 116e801a15569386c452085de783ecb9223050ff
https://github.com/llvm/llvm-project/commit/116e801a15569386c452085de783ecb9223050ff
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/phdr-out-of-order.test
Log Message:
-----------
[BOLT] Adjust section sizes based on file offsets (#80226)
When we adjust section sizes while rewriting a binary, we should be
using section offsets and not addresses to determine if section overlap.
NFC for existing binaries.
Commit: a693ae5306d224228acbbc1366dc90432afce434
https://github.com/llvm/llvm-project/commit/a693ae5306d224228acbbc1366dc90432afce434
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/linux-orc.s
Log Message:
-----------
[BOLT] Enable re-writing of Linux kernel binary (#80228)
Write modified Linux kernel binary to disk. The output is not supposed
to be functional at the moment, but it will allow for future patches to
test the output binary.
Commit: a063df20abeee3513d3577dc41bff7e54159efa5
https://github.com/llvm/llvm-project/commit/a063df20abeee3513d3577dc41bff7e54159efa5
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/CMakeLists.txt
Log Message:
-----------
[OpenMP] Fix typo (NFC) (#80332)
Commit: 6f32d6a4f362ad1c7f6328232a68f44a44fc2d2e
https://github.com/llvm/llvm-project/commit/6f32d6a4f362ad1c7f6328232a68f44a44fc2d2e
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/prefer-member-initializer.rst
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init.cpp
Log Message:
-----------
[clang-tidy] Remove enforcement of rule C.48 from cppcoreguidelines-prefer-member-init (#80330)
This functionality already exists in
cppcoreguidelines-use-default-member-init. It was deprecated from this
check in clang-tidy 17.
This allows us to fully decouple this check from the corresponding
modernize check, which has an unhealthy dependency.
Fixes https://github.com/llvm/llvm-project/issues/62169
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: 7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
https://github.com/llvm/llvm-project/commit/7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc] add bazel support for most of unistd (#80078)
Much of unistd involves modifying files. The tests for these functions
need to use libc_make_test_file_path which didn't exist when they were
first implemented. This patch adds most of unistd to the bazel along
with the corresponding tests. Tests that modify directories had to be
disabled since bazel doesn't seem to handle them properly.
Commit: aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
https://github.com/llvm/llvm-project/commit/aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
Author: Micah Weston <micahsweston at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP][llvm-readobj] Implements llvm-readobj handling for PGOAnalysisMap. (#79520)
Adds raw printing of PGOAnalysisMap in llvm-readobj.
I'm leaving the fixme's for a later patch that will provide a 'pretty'
printing for BBFreq and BrProb (i.e. relative frequencies and
probabilities) that will apply to both llvm-readobj and llvm-objdump.
Commit: 08fccf80949c649e2c4c81bf9149fd77206002c4
https://github.com/llvm/llvm-project/commit/08fccf80949c649e2c4c81bf9149fd77206002c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
Log Message:
-----------
[AArch64][PAC] Expand blend(reg, imm) operation in aarch64-pauth pass (#74729)
In preparation for implementing code generation for more @llvm.ptrauth.* intrinsics, move the expansion of blend(register, small integer) variant of @llvm.ptrauth.blend to the AArch64PointerAuth pass, where most other PAuth-related code generation takes place.
Commit: fe408eb5845737f8d6bf5eeed0aca8651991e687
https://github.com/llvm/llvm-project/commit/fe408eb5845737f8d6bf5eeed0aca8651991e687
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
Log Message:
-----------
[flang][openacc][openmp] Use #0 from hlfir.declare value when generating bound ops (#80317)
`getDataOperandBaseAddr` retrieve the address of a value when we need to
generate bound operations. When switching to HLFIR, we did not really
handle the fact that this value was then pointing to the result of a
hlfir.declare. Because of that the `#1` value was being used. `#0` value
is carrying the correct information about lowerbounds and should be
used. This patch updates the `getDataOperandBaseAddr` function to use
the correct result value from hlfir.declare.
Commit: 243bfed68367263cfc3fb3f396660acf60051fbf
https://github.com/llvm/llvm-project/commit/243bfed68367263cfc3fb3f396660acf60051fbf
Author: Artem Dergachev <adergachev at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
A clang/test/Analysis/html_diagnostics/counter.c
Log Message:
-----------
[analyzer][HTMLRewriter] Cache partial rewrite results. (#80220)
This is a follow-up for 721dd3bc2 [analyzer] NFC: Don't regenerate
duplicate HTML reports.
Because HTMLRewriter re-runs the Lexer for syntax highlighting and macro
expansion purposes, it may get fairly expensive when the rewriter is
invoked multiple times on the same file. In the static analyzer (which
uses HTMLRewriter for HTML output mode) we only get away with this
because there are usually very few reports emitted per file. But if loud
checkers are enabled, such as `webkit.*`, this may explode in complexity
and even cause the compiler to run over the 32-bit SourceLocation
addressing limit.
This patch caches intermediate results so that re-lexing only needed to
happen once.
As the clever __COUNTER__ test demonstrates, "once" is still too many.
Ideally we shouldn't re-lex anything at all, which remains a TODO.
Commit: 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
https://github.com/llvm/llvm-project/commit/8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
Author: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI]Add support for strided loads/stores.
Added basic legality check and cost estimation functions for strided loads and stores.
These interfaces will be built upon in https://github.com/llvm/llvm-project/pull/80310.
Reviewers: preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/80329
Commit: 59e559067b1e47b72f3c631483c1f71919d5358e
https://github.com/llvm/llvm-project/commit/59e559067b1e47b72f3c631483c1f71919d5358e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
Log Message:
-----------
Revert "[RISCV] Refine cost on Min/Max reduction" (#80340)
Reverts llvm/llvm-project#79402. Crash reported. On closer inspection,
this patch does not handle Intrinsic::maximum and Intrinsic::minimum.
Commit: edbd93d3706b806e7c91dfd2c359476488dfcc96
https://github.com/llvm/llvm-project/commit/edbd93d3706b806e7c91dfd2c359476488dfcc96
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/stdc_leading_ones_uc.cpp
M libc/src/stdbit/stdc_leading_ones_uc.h
M libc/src/stdbit/stdc_leading_ones_ul.cpp
M libc/src/stdbit/stdc_leading_ones_ul.h
M libc/src/stdbit/stdc_leading_ones_ull.cpp
M libc/src/stdbit/stdc_leading_ones_ull.h
M libc/src/stdbit/stdc_leading_ones_us.cpp
M libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
Log Message:
-----------
[libc][stdbit] fix return types (#80337)
All of the functions I've previously implemented return an unsigned int; not
the parameter type.
Commit: 5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
https://github.com/llvm/llvm-project/commit/5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/StackSlotColoring.cpp
A llvm/test/CodeGen/RISCV/pr80052.mir
M llvm/test/CodeGen/X86/pr30821.mir
Log Message:
-----------
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
The stack slot coloring pass is concerned with optimizing spill
slots. If any change is a pass is made over the function to remove
stack stores that use the same register and stack slot as an
immediately preceding load.
The register check is too simple for constant registers like AArch64
and RISC-V's zero register. This register can be used as the result
of a load if we want to discard the result, but still have the memory
access performed. Like for a volatile or atomic load.
If the code sees a load from the zero register followed by a store
of the zero register at the same stack slot, the pass mistakenly
believes the store isn't needed.
Since the main stack coloring optimization is only concerned with
spill slots, it seems reasonable that RemoveDeadStores should
only be concerned with spills. Since we never generate a reload of
x0, this avoids the issue seen by RISC-V.
Test case concept is adapted from pr30821.mir from X86. That test
had to be updated to mark the stack slot as a spill slot.
Fixes #80052.
Commit: 33b463ad9976fa7a27c1a22419297fcccd79f99f
https://github.com/llvm/llvm-project/commit/33b463ad9976fa7a27c1a22419297fcccd79f99f
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
A mlir/test/Dialect/SparseTensor/external.mlir
Log Message:
-----------
[mlir][sparse] external entry method wrapper for sparse tensors (#80326)
Similar to the emit_c_interface, this pull request adds a pass that
converts public entry methods that use sparse tensors as input
parameters and/or output return values into wrapper functions that
[dis]assemble the individual tensors that constitute the actual storage
used externally into MLIR sparse tensors. This pass can be used to
prepare the public entry methods of a program that is compiled by the
MLIR sparsifier to interface with an external runtime, e.g., when
passing sparse tensors as numpy arrays from and to Python. Note that
eventual bufferization decisions (e.g. who [de]allocates the underlying
memory) should be resolved in agreement with the external runtime
(Python, PyTorch, JAX, etc.)
Commit: 5d228eaf0f5d9c873ba12fc439609148f3f88733
https://github.com/llvm/llvm-project/commit/5d228eaf0f5d9c873ba12fc439609148f3f88733
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add beginner-focused office hours (#80308)
These are initially being hosted by a rotating cast of: @danakj
@gburgessiv @nickdesaulniers @sudonatalie
Commit: 9258f3e692493a69e0f4755bb129a5391ef10b50
https://github.com/llvm/llvm-project/commit/9258f3e692493a69e0f4755bb129a5391ef10b50
Author: Greg Clayton <gclayton at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
Log Message:
-----------
[lldb] Fix a crash when using .dwp files and make type lookup reliable with the index cache (#79544)
When using split DWARF with .dwp files we had an issue where sometimes
the DWO file within the .dwp file would be parsed _before_ the skeleton
compile unit. The DWO file expects to be able to always be able to get a
link back to the skeleton compile unit. Prior to this fix, the only time
the skeleton compile unit backlink would get set, was if the unit
headers for the main executable have been parsed _and_ if the unit DIE
was parsed in that DWARFUnit. This patch ensures that we can always get
the skeleton compile unit for a DWO file by adding a function:
```
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
```
Prior to this fix DWARFUnit had some unsafe accessors that were used to
store two different things:
```
void *DWARFUnit::GetUserData() const;
void DWARFUnit::SetUserData(void *d);
```
This was used by SymbolFileDWARF to cache the `lldb_private::CompileUnit
*` for a SymbolFileDWARF and was also used to store the `DWARFUnit *`
for SymbolFileDWARFDwo. This patch clears up this unsafe usage by adding
two separate accessors and ivars for this:
```
lldb_private::CompileUnit *DWARFUnit::GetLLDBCompUnit() const { return m_lldb_cu; }
void DWARFUnit::SetLLDBCompUnit(lldb_private::CompileUnit *cu) { m_lldb_cu = cu; }
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
void DWARFUnit::SetSkeletonUnit(DWARFUnit *skeleton_unit);
```
This will stop anyone from calling `void *DWARFUnit::GetUserData()
const;` and casting the value to an incorrect value.
A crash could occur in `SymbolFileDWARF::GetCompUnitForDWARFCompUnit()`
when the `non_dwo_cu`, which is a backlink to the skeleton compile unit,
was not set and was NULL. There is an assert() in the code, and then the
code just will kill the program if the assert isn't enabled because the
code looked like:
```
if (dwarf_cu.IsDWOUnit()) {
DWARFCompileUnit *non_dwo_cu =
static_cast<DWARFCompileUnit *>(dwarf_cu.GetUserData());
assert(non_dwo_cu);
return non_dwo_cu->GetSymbolFileDWARF().GetCompUnitForDWARFCompUnit(
*non_dwo_cu);
}
```
This is now fixed by calling the `DWARFUnit::GetSkeletonUnit()` which
will correctly always get the skeleton compile uint for a DWO file
regardless of if the skeleton unit headers have been parse or if the
skeleton unit DIE wasn't parsed yet.
To implement the ability to get the skeleton compile units, I added code
the DWARFDebugInfo.cpp/.h that make a map of DWO ID -> skeleton
DWARFUnit * that gets filled in for DWARF5 when the unit headers are
parsed. The `DWARFUnit::GetSkeletonUnit()` will end up parsing the unit
headers of the main executable to fill in this map if it already hasn't
been done. For DWARF4 and earlier we maintain a separate map that gets
filled in only for any DWARF4 compile units that have a DW_AT_dwo_id or
DW_AT_gnu_dwo_id attributes. This is more expensive, so this is done
lazily and in a thread safe manor. This allows us to be as efficient as
possible when using DWARF5 and also be backward compatible with DWARF4 +
split DWARF.
There was also an issue that stopped type lookups from succeeding in
`DWARFDIE SymbolFileDWARF::GetDIE(const DIERef &die_ref)` where it
directly was accessing the `m_dwp_symfile` ivar without calling the
accessor function that could end up needing to locate and load the .dwp
file. This was fixed by calling the
`SymbolFileDWARF::GetDwpSymbolFile()` accessor to ensure we always get a
valid value back if we can find the .dwp file. Prior to this fix it was
down which APIs were called and if any APIs were called that loaded the
.dwp file, it worked fine, but it might not if no APIs were called that
did cause it to get loaded.
When we have valid debug info indexes and when the lldb index cache was
enabled, this would cause this issue to show up more often.
I modified an existing test case to test that all of this works
correctly and doesn't crash.
Commit: 1bc7be6bce861acfe477f0c9abd349c1dc6ea160
https://github.com/llvm/llvm-project/commit/1bc7be6bce861acfe477f0c9abd349c1dc6ea160
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost model coverage for vp.strided.load and vp.strided.store
Commit: 391393179a6e316909add3b8455eb6d7c7c38ddb
https://github.com/llvm/llvm-project/commit/391393179a6e316909add3b8455eb6d7c7c38ddb
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
Log Message:
-----------
[lld-macho] icf objc stubs (#79730)
This supports icf for objc stubs.
Commit: ecdbffe59e80666c9cadf3f80bd20bb34828fb47
https://github.com/llvm/llvm-project/commit/ecdbffe59e80666c9cadf3f80bd20bb34828fb47
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/src/sys/epoll/linux/epoll_wait.cpp
Log Message:
-----------
[libc] Support epoll_wait using epoll_pwait (#80224)
The epoll_wait syscall is equivalent to calling epoll_pwait with a null
sigset. This is useful to support systems that have epoll_pwait but not
epoll_wait.
Commit: bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
https://github.com/llvm/llvm-project/commit/bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
Author: Hana Dusíková <hanicka at hanicka.net>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/test/CoverageMapping/if.cpp
Log Message:
-----------
[coverage] fix crash in code coverage and `if constexpr` with `ExprWithCleanups` (#80292)
Fixes https://github.com/llvm/llvm-project/issues/80285
Commit: 375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
https://github.com/llvm/llvm-project/commit/375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add aligned/unaligned tests for vp.strided.load and vp.strided.store
Commit: 07bf1ddb4eb0abfff20542fd4459bace1f72107f
https://github.com/llvm/llvm-project/commit/07bf1ddb4eb0abfff20542fd4459bace1f72107f
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
Log Message:
-----------
[mlir][sparse] support non-id map for [Dis]assembleOp (#80355)
Commit: 4eac14683855e040adaf507ed6b14e28a09f983e
https://github.com/llvm/llvm-project/commit/4eac14683855e040adaf507ed6b14e28a09f983e
Author: Greg Clayton <clayborg at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
Log Message:
-----------
Fix buildbots after #79544
https://github.com/llvm/llvm-project/pull/79544
Commit: 4a653b4df5d84c4d2df8f6d4040ef46413ac3816
https://github.com/llvm/llvm-project/commit/4a653b4df5d84c4d2df8f6d4040ef46413ac3816
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
Log Message:
-----------
[mlir][sparse] Support pretty print to debug sparse iteration. (#80207)
Commit: 8fd0bce43c4c8334bcb31d214a32260914f59515
https://github.com/llvm/llvm-project/commit/8fd0bce43c4c8334bcb31d214a32260914f59515
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
Log Message:
-----------
[mlir][spirv][memref] Calculate alignment for `PhysicalStorageBuffer`s (#80243)
The SPIR-V spec requires that memory accesses to
`PhysicalStorageBuffer`s are annotated with appropriate alignment
attributes [1]. Calculate these based on memref alignment attributes or
scalar type sizes.
[1] Otherwise spirv-val complains:
```
[VULKAN] ! Validation Error: [ VUID-VkShaderModuleCreateInfo-pCode-01379 ] | MessageID = 0x2a1bf17f | SPIR-V module not valid: [VUID-StandaloneSpirv-PhysicalStorageBuffer64-04708] Memory accesses with PhysicalStorageBuffer must use Aligned.
%48 = OpLoad %float %47
```
Commit: 4d89356fef1a568de790ad8b3f53dc494b461e5b
https://github.com/llvm/llvm-project/commit/4d89356fef1a568de790ad8b3f53dc494b461e5b
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
Log Message:
-----------
[libc][bazel] disable epoll_pwait2 (#80362)
Similar to #80051. The epoll_pwait2 syscall isn't available on all
target platforms, and this is causing downstream test failures. This
patch disables it until it can be detected whether or not it is
available.
Commit: ff3194037071e7f5fe859ad2173a5b67eed08b3b
https://github.com/llvm/llvm-project/commit/ff3194037071e7f5fe859ad2173a5b67eed08b3b
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port ecb5a1b0e236
Commit: 59eadcd28f787a98a2fd5f057beb3df7950654ee
https://github.com/llvm/llvm-project/commit/59eadcd28f787a98a2fd5f057beb3df7950654ee
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/test/python/dialects/memref.py
Log Message:
-----------
[mlir][py] Reduce size of allocation memrefs in test.
Commit: cc0d752f345f0e8995bec8807e3f365f38864fb6
https://github.com/llvm/llvm-project/commit/cc0d752f345f0e8995bec8807e3f365f38864fb6
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add git to actions container image (#80341)
Commit: 70eab122bceb94b15218c86db7045ff2448ea979
https://github.com/llvm/llvm-project/commit/70eab122bceb94b15218c86db7045ff2448ea979
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[AArch64][MachinePipeliner] Add pipeliner support for AArch64 (#79589)
Add AArch64 implementations for the interfaces of MachinePipeliner pass.
The pass is disabled by default for AArch64. It is enabled by specifying
--aarch64-enable-pipeliner.
5 tests in llvm-test-suites show performance improvement by more than 5%
on a Neoverse V1 processor.
| test | improvement |
| ---------------------------------------------------------------- |
-----------:|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl.test | 16%
|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-flt.test | 16%
|
| SingleSource/Benchmarks/Adobe-C++/loop_unroll.test | 14% |
| SingleSource/Benchmarks/Misc/flops-5.test | 13% |
| SingleSource/Benchmarks/BenchmarkGame/spectral-norm.test | 6% |
(base flags: -mcpu=neoverse-v1 -O3 -mrecip, flags for pipelining: -mllvm
-aarch64-enable-pipeliner -mllvm
-pipeliner-max-stages=100 -mllvm -pipeliner-max-mii=100 -mllvm
-pipeliner-enable-copytophi=0)
On the other hand, there are cases of significant performance
degradation. Algorithm improvements and adding the option/pragma will be
needed in the future.
Commit: acec6419e811a46050b0603dfa72fc6a169aa0f7
https://github.com/llvm/llvm-project/commit/acec6419e811a46050b0603dfa72fc6a169aa0f7
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/basic-block-address-map.c
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
A lld/test/ELF/lto/basic-block-address-map.ll
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
A llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
A llvm/test/CodeGen/X86/basic-block-address-map.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels.ll
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP] Allow basic-block-sections and labels be used together by decoupling the handling of the two features. (#74128)
Today `-split-machine-functions` and `-fbasic-block-sections={all,list}`
cannot be combined with `-basic-block-sections=labels` (the labels
option will be ignored).
The inconsistency comes from the way basic block address map -- the
underlying mechanism for basic block labels -- encodes basic block
addresses
(https://lists.llvm.org/pipermail/llvm-dev/2020-July/143512.html).
Specifically, basic block offsets are computed relative to the function
begin symbol. This relies on functions being contiguous which is not the
case for MFS and basic block section binaries. This means Propeller
cannot use binary profiles collected from these binaries, which limits
the applicability of Propeller for iterative optimization.
To make the `SHT_LLVM_BB_ADDR_MAP` feature work with basic block section
binaries, we propose modifying the encoding of this section as follows.
First let us review the current encoding which emits the address of each
function and its number of basic blocks, followed by basic block entries
for each basic block.
| | |
|--|--|
| Address of the function | Function Address |
| Number of basic blocks in this function | NumBlocks |
| BB entry 1
| BB entry 2
| ...
| BB entry #NumBlocks
To make this work for basic block sections, we treat each basic block
section similar to a function, except that basic block sections of the
same function must be encapsulated in the same structure so we can map
all of them to their single function.
We modify the encoding to first emit the number of basic block sections
(BB ranges) in the function. Then we emit the address map of each basic
block section section as before: the base address of the section, its
number of blocks, and BB entries for its basic block. The first section
in the BB address map is always the function entry section.
| | |
|--|--|
| Number of sections for this function | NumBBRanges |
| Section 1 begin address | BaseAddress[1] |
| Number of basic blocks in section 1 | NumBlocks[1] |
| BB entries for Section 1
|..................|
| Section #NumBBRanges begin address | BaseAddress[NumBBRanges] |
| Number of basic blocks in section #NumBBRanges |
NumBlocks[NumBBRanges] |
| BB entries for Section #NumBBRanges
The encoding of basic block entries remains as before with the minor
change that each basic block offset is now computed relative to the
begin symbol of its containing BB section.
This patch adds a new boolean codegen option `-basic-block-address-map`.
Correspondingly, the front-end flag `-fbasic-block-address-map` and LLD
flag `--lto-basic-block-address-map` are introduced.
Analogously, we add a new TargetOption field `BBAddrMap`. This means BB
address maps are either generated for all functions in the compiling
unit, or for none (depending on `TargetOptions::BBAddrMap`).
This patch keeps the functionality of the old
`-fbasic-block-sections=labels` option but does not remove it. A
subsequent patch will remove the obsolete option.
We refactor the `BasicBlockSections` pass by separating the BB address
map and BB sections handing to their own functions (named
`handleBBAddrMap` and `handleBBSections`). `handleBBSections` renumbers
basic blocks and places them in their assigned sections.
`handleBBAddrMap` is invoked after `handleBBSections` (if requested) and
only renumbers the blocks.
- New tests added:
- Two tests basic-block-address-map-with-basic-block-sections.ll and
basic-block-address-map-with-mfs.ll to exercise the combination of
`-basic-block-address-map` with `-basic-block-sections=list` and
'-split-machine-functions`.
- A driver sanity test for the `-fbasic-block-address-map` option
(basic-block-address-map.c).
- An LLD test for testing the `--lto-basic-block-address-map` option.
This reuses the LLVM IR from `lld/test/ELF/lto/basic-block-sections.ll`.
- Renamed and modified the two existing codegen tests for basic block
address map (`basic-block-sections-labels-functions-sections.ll` and
`basic-block-sections-labels.ll`)
- Removed `SHT_LLVM_BB_ADDR_MAP_V0` tests. Full deprecation of
`SHT_LLVM_BB_ADDR_MAP_V0` and `SHT_LLVM_BB_ADDR_MAP` version less than 2
will happen in a separate PR in a few months.
Commit: 3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
https://github.com/llvm/llvm-project/commit/3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
Log Message:
-----------
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)
Commit: 58c494f47cf56a30bf50024d22661c75003db809
https://github.com/llvm/llvm-project/commit/58c494f47cf56a30bf50024d22661c75003db809
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (#79399)
This is a good portion of the extensions mentioned in the RVA23 profile
here
https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc
I don't believe these add any new CSRs. Sstc does add new CSRs, but we
already added them without the extension name a while back.
I tried to keep the descriptions in RISCVFeatures.td fairly short since
the strings show up in `-print-supported-extensions`.
Commit: 082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
https://github.com/llvm/llvm-project/commit/082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Remove duplicate expression (#80380)
Reported by cpp check static analyzer in #80111.
Fixes #80111.
Commit: e270ec47cda26a8f0a3cdd195aa60992f109df8a
https://github.com/llvm/llvm-project/commit/e270ec47cda26a8f0a3cdd195aa60992f109df8a
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
Log Message:
-----------
[X86] X86InstrInfo.cpp - Remove dead code for memory folding, NFCI
`commuteInstruction(MI, false, OpNum, CommuteOpIdx2)` should never create
any new instruction, so we don't need to check and erase it.
Commit: 7dd790db8b77c4a833c06632e903dc4f13877a64
https://github.com/llvm/llvm-project/commit/7dd790db8b77c4a833c06632e903dc4f13877a64
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
[lldb] NFC fixes addressing David's feedback
David Spickett had several suggestions for
https://github.com/llvm/llvm-project/pull/79962 after I'd
already merged it. Address those.
Commit: dee8786f70a3d62b639113343fa36ef55bdbad63
https://github.com/llvm/llvm-project/commit/dee8786f70a3d62b639113343fa36ef55bdbad63
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/insert-before.test
Log Message:
-----------
[ELF] Fix compareSections assertion failure when OutputDescs in sectionCommands are non-contiguous
In a `--defsym y0=0 -T a.lds` link where a.lds contains only INSERT
commands, the `script->sectionCommands` layout may be:
```
orphan sections
SymbolAssignment due to --defsym
sections created by INSERT commands
```
The `OutputDesc` objects are not contiguous in sortInputSections, and
`compareSections` will be called with a SymbolAssignment argument,
leading to an assertion failure.
Commit: 374a600df7207fbe2002e754a799c7595a0e4833
https://github.com/llvm/llvm-project/commit/374a600df7207fbe2002e754a799c7595a0e4833
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[MachinePipeliner] Fix missing requirements for tests (#80386)
Add asserts requirements for tests that verify debug output.
Commit: 2147a2a4f3ef344a561677b55444ce4d028ec59f
https://github.com/llvm/llvm-project/commit/2147a2a4f3ef344a561677b55444ce4d028ec59f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/auto-type.c
Log Message:
-----------
[clang][Interp] Not all TypeTraitExprs are of bool type
In C, they return an integer, so emit their value as such.
Commit: 58ceefe09cd992c3692bb3af7c2807ac8949ba67
https://github.com/llvm/llvm-project/commit/58ceefe09cd992c3692bb3af7c2807ac8949ba67
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Support ChooseExprs
Commit: a2da7d06c7e1ec75812ff8ced29541d4af3668c9
https://github.com/llvm/llvm-project/commit/a2da7d06c7e1ec75812ff8ced29541d4af3668c9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Ignore LValueToRValue casts before doing the load
If the SubExpr results in an invalid pointer, we will otherwise
reject the constant expression.
Commit: 65ac8c16e028b23b49fd6b03817faa1ab6c0229d
https://github.com/llvm/llvm-project/commit/65ac8c16e028b23b49fd6b03817faa1ab6c0229d
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir] Skip invalid test on big endian platform (s390x) (#80246)
The buildbot test running on s390x platform keeps failing since [this
time](https://lab.llvm.org/buildbot/#/builders/199/builds/31136). This
is because of the dependency on the endianness of the platform. It
expects the format invalid in the big endian platform (s390x). We can
simply skip it.
See: https://discourse.llvm.org/t/mlir-s390x-linux-failure/76695
Commit: a8b5994b337cf1d461202a65204a4ee6c5eae341
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp][NFC] Add a broken test case
The LHS of the subtraction returns 16 right now, but should
return 0.
Commit: d9c20e437fe110fb79b5ca73a52762e5b930b361
https://github.com/llvm/llvm-project/commit/d9c20e437fe110fb79b5ca73a52762e5b930b361
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aarch64-inline-asm.c
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
Log Message:
-----------
[AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276)
This enables specifing "za" or "zt0" to the clobber list for inline asm.
This complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276
Commit: 0be39155bd22258b3e90468b6184bfd87a948bec
https://github.com/llvm/llvm-project/commit/0be39155bd22258b3e90468b6184bfd87a948bec
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/Sema/warn-cast-qual.c
Log Message:
-----------
[clang][Interp] Protect stores against dummy pointers
Commit: 3be79790ede30762f73b95218be8877c3b2c3774
https://github.com/llvm/llvm-project/commit/3be79790ede30762f73b95218be8877c3b2c3774
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang] Update documentation for `#pragma diagnostic` (#78095)
GCC has changed over the past decade, and we're not implementing
everything they do.
Fixes #51472
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 75c4339ef31922bf8c883a7a5dfe638ec6818ab2
https://github.com/llvm/llvm-project/commit/75c4339ef31922bf8c883a7a5dfe638ec6818ab2
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/EvaluationResult.cpp
Log Message:
-----------
[clang][Interp][NFC] Implement dumping Invalid/Valid results
This was just an omission from an earlier commit, clearly
we can print them.
Commit: 0f26441cb83c1dea9aef12c748a79e3f38e3230a
https://github.com/llvm/llvm-project/commit/0f26441cb83c1dea9aef12c748a79e3f38e3230a
Author: Maciej Gabka <maciej.gabka at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[TLI][AArch64] Adjust TLI mappings to vector functions taking linear pointers (#80296)
The masked symbols in SLEEF are incorrectly implemented as calls to non
masked variants, what only works fine for functions which do not modify
memory.
For vector variants which modify memory we can only use a non masked
symbols for now.
The SVE ArmPL mappings need to be removed for now as well.
Commit: 237a799e938aca86dc7e62def792b26974bbae5d
https://github.com/llvm/llvm-project/commit/237a799e938aca86dc7e62def792b26974bbae5d
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/IR/Builders.cpp
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Notify about block insertion when cloning an op (#80262)
`OpBuilder::clone(Operation &)` should trigger not only
`notifyOperationInserted` but also `notifyBlockInserted` (for all block
contained in `op`).
Commit: a792cb6e3e03aff22dabb6cc94db68d15d953a55
https://github.com/llvm/llvm-project/commit/a792cb6e3e03aff22dabb6cc94db68d15d953a55
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/IR/Builders.cpp
Log Message:
-----------
[mlir][IR] Do not trigger `notifyOperationInserted` for unlinked ops (#80278)
This commit changes `OpBuilder::create` and `OpBuilder::createOrFold`
such that `notifyOperationInserted` is no longer triggered if no
insertion point is set. In such a case, an unlinked operation is created
but not inserted, so `notifyOperationInserted` should not be triggered.
Note: Inserting another op into a block that belongs to an unlinked op
(e.g., by the builder of the unlinked op) will trigger a notification.
Commit: c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
https://github.com/llvm/llvm-project/commit/c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
Author: ManuelvOK <info at manuel-thieme.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
Log Message:
-----------
[Coverage] Map regions from system headers (#76950)
In 2155195131a57f2f01e7cfabb85bb027518c2dc6, the
"system-headers-coverage" option has been added but not used in all
necessary places.
This is the recommit since it has been reverted in
faef68bca852d08511ea0311d8a0d221cb202e73
Potential reviewers: @gulfemsavrun @petrhosek
Co-authored-by: Manuel Kalettka <manuel.kalettka at kernkonzept.com>
Commit: b840d2968391dd610b792a65133a1edc1bcc397c
https://github.com/llvm/llvm-project/commit/b840d2968391dd610b792a65133a1edc1bcc397c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Send notifications for `cloneRegionBefore` (#66871)
Similar to `OpBuilder::clone`, operation/block insertion notifications
should be sent when cloning the contents of a region. E.g., this is to
ensure that the newly created operations are put on the worklist of the
greedy pattern rewriter driver.
Also move `cloneRegionBefore` from `RewriterBase` to `OpBuilder`. It
only creates new IR, so it should be part of the builder API (like
`clone(Operation &)`). The function does not have to be virtual. Now
that notifications are properly sent, the override in the dialect
conversion is no longer needed.
Commit: 73e546625d6567e5a33454741d257b6929c89635
https://github.com/llvm/llvm-project/commit/73e546625d6567e5a33454741d257b6929c89635
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix up broken test case
This was not working right on armv8:
https://lab.llvm.org/buildbot/#/builders/245/builds/20020
Commit: 9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
https://github.com/llvm/llvm-project/commit/9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[mlir][memref] `memref.subview`: Verify result strides with rank reductions (#80158)
This is a follow-up on #79865. Result strides are now also verified if
the `memref.subview` op has rank reductions.
Commit: 9e649518e6038a5b9ea38cfa424468657d3be59e
https://github.com/llvm/llvm-project/commit/9e649518e6038a5b9ea38cfa424468657d3be59e
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/init-aarch64.c
Log Message:
-----------
[Clang][AArch64] Add missing SME macros (#80293)
__ARM_STATE_ZA and __ARM_STATE_ZT0 are set when the compiler can parse
the "za" and "zt0" strings in the SME attributes.
__ARM_FEATURE_SME and __ARM_FEATURE_SME2 are set when the compiler can
generate code for attributes with "za" and "zt0" state, respectively.
__ARM_FEATURE_LOCALLY_STREAMING is set when the compiler supports the
__arm_locally_streaming attribute.
Commit: 438fe1db09b0c20708ea1020519d8073c37feae8
https://github.com/llvm/llvm-project/commit/438fe1db09b0c20708ea1020519d8073c37feae8
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
Log Message:
-----------
CoverageMappingWriter: Emit `Decision` before `Expansion` (#78966)
To relax scanning record, tweak order by `Decision < Expansion`, or
`Expansion` could not be distinguished whether it belonged to `Decision`
or not.
Relevant to #77871
Commit: acf6811d0f2b6b453be46ddf7e046e1346991c98
https://github.com/llvm/llvm-project/commit/acf6811d0f2b6b453be46ddf7e046e1346991c98
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
A llvm/test/TableGen/deftype.td
Log Message:
-----------
[TableGen] Support type aliases via new keyword deftype
We can use `deftype` (not using `typedef` here to be consistent
with `def`, `defm`, `defset`, `defvar`, etc) to define type aliases.
Currently, only primitive types and type aliases are supported to be
the source type and `deftype` statements can only appear at the top
level.
Reviewers: fpetrogalli, Artem-B, nhaehnle, jroelofs
Reviewed By: jroelofs, nhaehnle, Artem-B
Pull Request: https://github.com/llvm/llvm-project/pull/79570
Commit: a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
https://github.com/llvm/llvm-project/commit/a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Lex/PPMacroExpansion.cpp
A clang/test/Preprocessor/has_builtin_cpuid.c
Log Message:
-----------
[Preprocessor] Fix __has_builtin for CPU ID functions (#80058)
My recent commit (67c1c1d) made the CPU ID builtins target-independent
so they can be used on PPC as well. However, that had the unintended
consequence of changing the behaviour of __has_builtin in that it
reports these as supported at the pre-processor level. This makes it
impossible to guard the use of these with this feature test macro which
is clearly not ideal.
This patch restores the behaviour of __has_builtin for __builtin_cpu_is,
__builtin_cpu_init,
__builtin_cpu_supports. Now the preprocessor queries the target to
determine whether the target supports the builtin.
Commit: 42ec9934e1079742e0b5d839e420bc3f746fc73b
https://github.com/llvm/llvm-project/commit/42ec9934e1079742e0b5d839e420bc3f746fc73b
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Fix gcc -Wparentheses warning [NFC]
Without this gcc warns like
../lib/Target/PowerPC/PPCAsmPrinter.cpp:1650:33: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
1650 | (InstDisp >= -32768) &&
| ~~~~~~~~~~~~~~~~~~~~~^~
1651 | "Expecting the instruction displacement for local-exec TLS "
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1652 | "variables to be between [-32768, 32768)!");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
https://github.com/llvm/llvm-project/commit/5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[SCEVExpander] Do not reuse disjoint or (#80281)
SCEV treats "or disjoint" the same as "add nsw nuw". However, when
expanding, we cannot generally replace an add SCEV node with an "or
disjoint" instruction. Just dropping the poison flag is insufficient in
this case, we would have to actually convert the or into an add.
This is a partial fix for #79861.
Commit: 84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
https://github.com/llvm/llvm-project/commit/84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
Log Message:
-----------
[MLIR][Vector] Implement memory effect for print (#80400)
Add write memory effect for the print operation. The exact memory
behavior is implemented in other print-like operations such as
`transform::PrintOp` or `gpu::printf`.
Providing memory behavior allows using the operation in passes like
buffer deallocation instead of emitting an error.
Commit: c2dea7122cd9f559f64cd0b34431d21e61f5bf15
https://github.com/llvm/llvm-project/commit/c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
Log Message:
-----------
[mlir][ArmSME] Fold extracts from 3D create_masks of SME-like masks (#80148)
When unrolling the reduction dimension of something like a matmul for
SME, it is possible to get 3D masks, which are vectors of SME-like
masks. The 2D masks for individual operations are then extracted from
the 3D masks.
i.e.:
```mlir
%mask = vector.create_mask %nonConstantDim, %a, %b : vector<4x[4]x[4]xi1>
%subMask = vector.extract %mask[2]
: vector<[4]x[4]xi1> from vector<4x[4]x[4]xi1>
```
ArmSME only supports lowering 2D create_masks, so we must fold the
extract into the create_mask. This can be done by checking if the
extraction index is within the true region, then using that select the
first dimension of the 2D mask. This is shown below.
```mlir
%extractionInTrueRegion = arith.cmpi slt, %c2, %nonConstantDim : index
%newMaskFrontDim = arith.select %extractionInTrueRegion, %a, %c0 : index
%subMask = vector.create_mask %newMaskFrontDim, %b : vector<[4]x[4]xi1>
```
Commit: 6d1d2c67e7597dc417c097d5027558b0159ed2e2
https://github.com/llvm/llvm-project/commit/6d1d2c67e7597dc417c097d5027558b0159ed2e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
[clang] Fix a possible out-of-bounds read (#80023)
Fixes #79964
Commit: 4b8e514334786e1aa6f86d7d777385aa9702d835
https://github.com/llvm/llvm-project/commit/4b8e514334786e1aa6f86d7d777385aa9702d835
Author: Tuan Chuong Goh <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Pre-Commit tests for Legalize BSWAP Vectors
Commit: 2cf415f2a03433fd3661938fb2f4af0754ad2274
https://github.com/llvm/llvm-project/commit/2cf415f2a03433fd3661938fb2f4af0754ad2274
Author: Peter Smith <peter.smith at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/SecurityTransparencyReports.rst
Log Message:
-----------
Add security group 2023 transparency report. (#80320)
Commit: ffb3589b8cb3468713d25ff2a4378918eafa7044
https://github.com/llvm/llvm-project/commit/ffb3589b8cb3468713d25ff2a4378918eafa7044
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Remove transitive <locale> include from <vector> (#80282)
This reduces the time to include `<vector>` from 468ms to 367ms.
Commit: 9410019ac977141bc73aee19690b5896ded59219
https://github.com/llvm/llvm-project/commit/9410019ac977141bc73aee19690b5896ded59219
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-combine.ll
M llvm/test/CodeGen/X86/popcnt.ll
Log Message:
-----------
[X86] Add i8 CTPOP lowering using i32 MUL (#79989)
This is the first basic proposal in #79823 - we can investigate improving support for other widths if we can find further use cases.
Commit: 10943695f76f513503162026669e84cb72275e84
https://github.com/llvm/llvm-project/commit/10943695f76f513503162026669e84cb72275e84
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)
Add support of i16 vector operation for BSWAP and change to TableGen to
select instructions
Handle vector types that are smaller/larger than legal for BSWAP
Commit: cca9f9b78fc657c280f7e4024a552af43a315bdb
https://github.com/llvm/llvm-project/commit/cca9f9b78fc657c280f7e4024a552af43a315bdb
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Commit: 2d1f5af8b0b07a4ac19eae699aa660debb1a5613
https://github.com/llvm/llvm-project/commit/2d1f5af8b0b07a4ac19eae699aa660debb1a5613
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
Use !tolower instead of repeating the name when defining a renamed Real
instruction.
Commit: 589b21f38932ed1150906fc30307f030c62f6e8f
https://github.com/llvm/llvm-project/commit/589b21f38932ed1150906fc30307f030c62f6e8f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__memory/temporary_buffer.h
Log Message:
-----------
[libc++][NFC] Remove <__type_traits/alignment_of.h> include
Commit: 2e669ff59ebb096d67d02ec51dbb7050dc5e2235
https://github.com/llvm/llvm-project/commit/2e669ff59ebb096d67d02ec51dbb7050dc5e2235
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerBuildVector* - share the same SDLoc argument instead of recreating it over and over again.
Commit: b5d35feacb7246573c6a4ab2bddc4919a4228ed5
https://github.com/llvm/llvm-project/commit/b5d35feacb7246573c6a4ab2bddc4919a4228ed5
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/avx512-arith.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/combine-addo.ll
M llvm/test/CodeGen/X86/combine-and.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-pavg.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/combine-sub.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/combine-urem.ll
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/extract-concat.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-shuffle.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/packus.ll
M llvm/test/CodeGen/X86/paddus.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/pr48215.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr61964.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/pr63507.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-512.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-512.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - load+sign-extend vector constants that can be stored in a truncated form (#79815)
Reduce the size of the vector constant by storing it in the constant pool in a truncated form, and sign-extend it as part of the load.
I've extended the existing FixupConstant functionality to support these sext constant rebuilds - we still select the smallest stored constant entry and prefer vzload/broadcast/vextload for same bitwidth to avoid domain flips.
I intend to add the matching load+zero-extend handling in a future PR, but that requires some alterations to the existing MC shuffle comments handling first.
Commit: ffd84a6a9afc43968fe24c9057bd4f86e148e283
https://github.com/llvm/llvm-project/commit/ffd84a6a9afc43968fe24c9057bd4f86e148e283
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in MemRefOps.cpp (NFC)
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2763:23:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() == droppedDims.size() && "incorrect number of bits");
~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2764:38:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() - t2.getRank() == droppedDims.count() &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~
Commit: d912f1f0cb49465b08f82fae89ece222404e5640
https://github.com/llvm/llvm-project/commit/d912f1f0cb49465b08f82fae89ece222404e5640
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
A llvm/test/tools/llvm-cov/mcdc-macro.test
Log Message:
-----------
[Coverage] Let `Decision` take account of expansions (#78969)
The current implementation (D138849) assumes `Branch`(es) would follow
after the corresponding `Decision`. It is not true if `Branch`(es) are
forwarded to expanded file ID. As a result, consecutive `Decision`(s)
would be confused with insufficient number of `Branch`(es).
`Expansion` will point `Branch`(es) in other file IDs if `Expansion` is
included in the range of `Decision`.
Fixes #77871
---------
Co-authored-by: Alan Phipps <a-phipps at ti.com>
Commit: 4cf2ed4396ddeda1487d6c5151a7dfdf14573920
https://github.com/llvm/llvm-project/commit/4cf2ed4396ddeda1487d6c5151a7dfdf14573920
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Fix -Wsign-compare in X86MCInstLower.cpp (NFC)
llvm-project/llvm/lib/Target/X86/X86MCInstLower.cpp:1588:48:
error: comparison of integers of different signs: 'unsigned int' and 'int' [-Werror,-Wsign-compare]
if (C && C->getType()->getScalarSizeInBits() == SrcEltBits) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~
1 error generated.
Commit: 319f4c03ba2909c7240ac157cc46216bf1518c10
https://github.com/llvm/llvm-project/commit/319f4c03ba2909c7240ac157cc46216bf1518c10
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/aarch64-sme-func-attrs.c
Log Message:
-----------
[Clang][AArch64] Emit 'unimplemented' diagnostic for SME (#80295)
When a function F has ZA and ZT0 state, calls another function G that
only shares ZT0 state with its caller, F will have to save ZA before
the call to G, and restore it afterwards (rather than setting up a
lazy-sve).
This is not yet implemented in LLVM and does not result in a
compile-time error either. So instead of silently generating incorrect
code, it's better to emit an error saying this is not yet implemented.
Commit: b8025d1482a9664463cfc727a0e51cad86fdf2fe
https://github.com/llvm/llvm-project/commit/b8025d1482a9664463cfc727a0e51cad86fdf2fe
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
Reapply "[AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode." (#80303)
Reapply #71556 with added lit test constraint: `REQUIRES: amdgpu-registered-target`.
This reverts commit 9791e5414960f92396582b9e9ee503ac15799312.
Commit: c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
https://github.com/llvm/llvm-project/commit/c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
Log Message:
-----------
[SCEV] Add SCEV analysis tests with congruent IVs.
This patch adds a set of tests taken
from/llvm/test/Transforms/IndVarSimplify/iv-poison.ll with multiple
congruent IVs but different set of flags on the increments.
Extra tests for https://github.com/llvm/llvm-project/pull/80430.
Commit: 7a4570acdb1a32935d96831142748ba3298a2b7f
https://github.com/llvm/llvm-project/commit/7a4570acdb1a32935d96831142748ba3298a2b7f
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/HLFIR/array-ctor-character.f90
Log Message:
-----------
[flang] sanitize set_length in lowering (#80412)
In fortran, it is possible to give a negative "i" in "character(i)" in
which case the standard says the length is zero. So the length must be
sanitized as max(0, user_input) in lowering.
This is already done when lowering specification parts, but was not done
when "character(i)" appears in array constructors. Sanitize the length
when lowering SetLength in lowering.
Fixes https://github.com/llvm/llvm-project/issues/80270
Commit: 92bbf615f50c67030ed536f08cc5bb266e0718db
https://github.com/llvm/llvm-project/commit/92bbf615f50c67030ed536f08cc5bb266e0718db
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Use function-attached target attributes for OpenMP lowering (#78291)
This patch removes the omp.target module attribute, since the
information it held on the target CPU and features is available through
the fir.target_cpu and fir.target_features module attributes. Target
outlining during the MLIR to LLVM IR translation stage is updated, so
that these attributes, at that point available as llvm.func attributes,
are passed along to the newly created function.
Commit: 3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
https://github.com/llvm/llvm-project/commit/3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] FP<->INT helpers - share the same SDLoc argument instead of recreating it over and over again.
Commit: a1df10da59e8eb0c1d90df81bf9000d2f7869328
https://github.com/llvm/llvm-project/commit/a1df10da59e8eb0c1d90df81bf9000d2f7869328
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
AMDGPU/NFC: Add predicate for supporting ds_add_f64 (#80379)
Commit: 1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
https://github.com/llvm/llvm-project/commit/1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix broken test case again
Instead of asserting that it's wrong, assert the correct
value.
See the discussion in
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Commit: 274d1b000cae57acf2dc988fcb65cfe7383ed2b0
https://github.com/llvm/llvm-project/commit/274d1b000cae57acf2dc988fcb65cfe7383ed2b0
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[NFC] Add useFPRegsForHalfType(). (#74147)
Currently, half operations can be promoted in one of two ways.
* If softPromoteHalfType() returns false, fp16 values are passed around
in fp32 registers, and whole chains of fp16 operations are promoted to
fp32 in one go.
* If softPromoteHalfType() returns true, fp16 values are passed around
in i16 registers, and individual fp16 operations are promoted to fp32
and the result truncated to fp16 right away.
The softPromoteHalfType behavior is necessary for correctness, but
changing this for an existing target breaks the ABI. Therefore, this
commit adds a third option:
* If softPromoteHalfType() returns true and useFPRegsForHalfType()
returns true as well, fp16 values are passed around in fp32 registers,
but individual fp16 operations are promoted to fp32 and the result
truncated to fp16 right away.
This change does not yet update any target to make use of it.
Commit: 1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
https://github.com/llvm/llvm-project/commit/1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
Author: lifengxiang1025 <lifengxiang.1025 at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
Log Message:
-----------
[MemProf] Fix when CallStackTrie has a single chain to leaf with multi alloc type (#79433)
Fix one corner case when `CallStackTrie` has a single chain to leaf with
multi alloc type. This will cause stackIds in function summary is empty.
Commit: 275729ae06d568e9589392c142a416fb8c2bb1a8
https://github.com/llvm/llvm-project/commit/275729ae06d568e9589392c142a416fb8c2bb1a8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
Log Message:
-----------
[X86] Generalize i8 CTPOP expansion to work with any input with 8 or less active bits
Extend #79989 slightly to use KnownBits on the CTPOP input - this should make it easier to add additional cases identified in #79823
Commit: 66b339aa6ba3ee63806c87630aec1dc6a45e63c5
https://github.com/llvm/llvm-project/commit/66b339aa6ba3ee63806c87630aec1dc6a45e63c5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
Log Message:
-----------
[IndVars] Regenerate test checks (NFC)
Commit: a986f5e218ab8a68097fcc1fd3234b8743839ef8
https://github.com/llvm/llvm-project/commit/a986f5e218ab8a68097fcc1fd3234b8743839ef8
Author: alexfh <alexfh at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
Fix clang crash when printing highlighted code in diagnostic (after #66514) (#80442)
Implements the fix proposed by Evgeny Eltsin on
https://github.com/llvm/llvm-project/pull/66514#issuecomment-1924039038.
No test case provided, since the bug is extremely sensitive to the
preprocessor
state (headers, macros, including the ones defined on command line), and
it
turned out to be non-trivial to create an isolated test.
Commit: fbf9356be07408efc05621a7a8d0472a61c66228
https://github.com/llvm/llvm-project/commit/fbf9356be07408efc05621a7a8d0472a61c66228
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Add ctpop-mask.ll - test coverage based off #79823
Commit: 46b6756255029f442165148115bad99d04057622
https://github.com/llvm/llvm-project/commit/46b6756255029f442165148115bad99d04057622
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
M clang/test/Driver/hip-options.hip
Log Message:
-----------
[AMDGPU] Diagnose unaligned atomic (#80322)
AMDGPU does not support unaligned atomics, therefore make the warning an
error.
This patch is transferred from
https://reviews.llvm.org/D99201
Commit: 43dd1e84df1ecdad872e1004af47b489e08fc228
https://github.com/llvm/llvm-project/commit/43dd1e84df1ecdad872e1004af47b489e08fc228
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[SCEV] Move canReuseInstruction() helper into SCEV (NFC)
To allow reusing it in IndVars.
Commit: 7524b037257cdeb67e3ed80364da94eab8e98122
https://github.com/llvm/llvm-project/commit/7524b037257cdeb67e3ed80364da94eab8e98122
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add note about calendar timezones (#80346)
Commit: 67eee4a029797c09129889c3655416d1be487cfe
https://github.com/llvm/llvm-project/commit/67eee4a029797c09129889c3655416d1be487cfe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
[libc++] Optimize vector growing of trivially relocatable types (#76657)
This patch introduces a new trait to represent whether a type is
trivially
relocatable, and uses that trait to optimize the growth of a std::vector
of trivially relocatable objects.
```
--------------------------------------------------
Benchmark old new
--------------------------------------------------
bm_grow<int> 1354 ns 1301 ns
bm_grow<std::string> 5584 ns 3370 ns
bm_grow<std::unique_ptr<int>> 3506 ns 1994 ns
bm_grow<std::deque<int>> 27114 ns 27209 ns
```
This also changes to order of moving and destroying the objects when
growing the vector. This should not affect our conformance.
Commit: 30503116550c2bffe706366e93dbaee15850014c
https://github.com/llvm/llvm-project/commit/30503116550c2bffe706366e93dbaee15850014c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 67eee4a02979
Commit: b629414ae13d6dcd641e92d0389c5d4b7638a644
https://github.com/llvm/llvm-project/commit/b629414ae13d6dcd641e92d0389c5d4b7638a644
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
Log Message:
-----------
[libc][NFC] Simplify logic in `sqrt` (#80426)
Commit: 28865da37451904c4654f20cdaddee815fdeff1d
https://github.com/llvm/llvm-project/commit/28865da37451904c4654f20cdaddee815fdeff1d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Log Message:
-----------
[LSR][term-fold] Adjust expansion budget based on trip count (#80304)
Follow up to https://github.com/llvm/llvm-project/pull/74747
This change extends the previously added fixed expansion threshold by
scaling down the cost allowed for an expansion for a loop with either a
small known trip count or a profile which indicates the trip count is
likely small. The goal here is to improve code generation for a loop
nest where the outer loop has a high trip count, and the inner loop runs
only a handful of iterations.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 1437a83491cbe4af1b452a3f862a6b609057c26d
https://github.com/llvm/llvm-project/commit/1437a83491cbe4af1b452a3f862a6b609057c26d
Author: Rushi Bhamani <99245918+rushiraj7677 at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
Log Message:
-----------
Add --abort-on-invalid-reduction to more lit tests (#80263)
Commit: b78b264518e0f341d99a4291cbf24134c7536f6d
https://github.com/llvm/llvm-project/commit/b78b264518e0f341d99a4291cbf24134c7536f6d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/RISCV/gep.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[TTI] Add costing for vp.strided.load and vp.strided.store (#80360)
The primary motivation of this patch is to add testing infrastructure
atop the recently landed 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7, so
that we can separate the costing aspects of strided memory operations
from the SLP implementation details.
I want to be clear that I am *not* proposing that we use the
vp.strided.* forms as our canonical IR representation. I'm merely using
them as a testing vehicle to exercise the costing machinery. The
canonical IR form remains a masked.gather or masked.scatter. I do want
to explore adding a non-vp strided load/store intrinsic, but that's a
separate line of work.
There is one costing change included in this. As I wrote my test, I
discovered that the default implementation was scalarized (if invoked
via generic routines such as getInstructionCost), and when adding the
call into the strided specific costing discovered that we hadn't modeled
the fallback to scalarization properly in the initial patch. After
fixing that, there is a minor difference in scalarization cost reported
for the unaligned case but I believe that to be uninteresting.
For the record, I did confirm that vp.strided.store is lowered to a
strided store on RISCV. :)
Commit: a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
https://github.com/llvm/llvm-project/commit/a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
Author: Manish Kausik H <46352931+Nirhar at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
A llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
Log Message:
-----------
[SelectionDAG] Use unaligned store to move AVX registers onto stack for `extractelement` (#78422)
Prior to this patch, SelectionDAG generated aligned move onto stacks for
AVX registers when the function was marked as a no-realign-stack
function. This lead to misalignment between the stack and the
instruction generated. This patch fixes the issue.
Fixes #77730
Commit: 7b08b4360b488b35428c97132b3f9d2a777bd770
https://github.com/llvm/llvm-project/commit/7b08b4360b488b35428c97132b3f9d2a777bd770
Author: Nathan Gauër <brioche at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
Log Message:
-----------
[SPIR-V] add convergence region analysis (#78456)
This new analysis returns a hierarchical view of the convergence regions
in the given function.
This will allow our passes to query which basic block belongs to which
convergence region, and structurize the code in consequence.
Definition
----------
A convergence region is a CFG with:
- a single entry node.
- one or multiple exit nodes (different from LLVM's regions).
- one back-edge
- zero or more subregions.
Excluding sub-regions nodes, the nodes of a region can only reference a
single convergence token. A subregion uses a different convergence
token.
Algorithm
---------
This algorithm assumes all loops are in the Simplify form.
Create an initial convergence region for the whole function.
- the convergence token is the function entry token.
- the entry is the function entrypoint.
- Exits are all the basic blocks terminating with a return instruction.
Take the function CFG, and process it in DAG order (ignoring
back-edges). If a basic block is a loop header:
- Create a new region.
- The parent region is the parent's loop region if any, otherwise, the
top level region.
- The region blocks are all the blocks belonging to this loop.
- For each loop exit: - visit the rest of the CFG in DAG order (ignore
back-edges). - if the region's convergence token is found, add all the
blocks dominated by the exit from which the token is reachable to the
region.
- continue the algorithm with the loop headers successors.
Commit: 7ecfb66c77ad77dabbb705cbb1f3b17a3d1391a4
https://github.com/llvm/llvm-project/commit/7ecfb66c77ad77dabbb705cbb1f3b17a3d1391a4
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.meaning.general/p3.cpp
Log Message:
-----------
[Clang][Sema] Correctly look up primary template for variable template specializations (#80359)
Consider the following:
```
namespace N0 {
namespace N1 {
template<typename T>
int x1 = 0;
}
using namespace N1;
}
template<>
int N0::x1<int>;
```
According to [dcl.meaning.general] p3.3:
> - If the _declarator_ declares an explicit instantiation or a partial
or explicit specialization, the _declarator_ does not bind a name. If it
declares a class member, the terminal name of the _declarator-id_ is not
looked up; otherwise, **only those lookup results that are nominable in
`S` are considered when identifying any function template specialization
being declared**.
In particular, the requirement for lookup results to be nominal in the
lookup context of the terminal name of the _declarator-id_ only applies
to function template specializations -- not variable template
specializations. We currently reject the above declaration, but we do
(correctly) accept it if the using-directive is replaced with a `using`
declaration naming `N0::N1::x1`. This patch makes it so the above
specialization is (correctly) accepted.
Commit: 3a758076f54d521d20e32856a62c7d24803ee9e8
https://github.com/llvm/llvm-project/commit/3a758076f54d521d20e32856a62c7d24803ee9e8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Allow i8 CTPOP expansion to work with a 'shifted' active bits value of 8 bits or less
Shift down the value so the active bits are at the lsb
Commit: faeb3d1f106d607f51babe3770e899bc9bda7f3a
https://github.com/llvm/llvm-project/commit/faeb3d1f106d607f51babe3770e899bc9bda7f3a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
Log Message:
-----------
[AMDGPU] Regenerate ctpop64.ll test checks
Commit: 1156bbc5b1837e688b0e5d6952f1a900aca29062
https://github.com/llvm/llvm-project/commit/1156bbc5b1837e688b0e5d6952f1a900aca29062
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/TypeLoc.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/drs/dr7xx.cpp
M clang/test/CXX/temp/temp.decls/temp.class/temp.mem.func/p1.cpp
A clang/test/CXX/temp/temp.names/p5.cpp
M clang/test/CXX/temp/temp.spec/part.spec.cpp
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaTemplate/class-template-spec.cpp
Log Message:
-----------
[Clang][Sema] Diagnose use of template keyword after declarative nested-name-specifiers (#78595)
According to [temp.names] p5:
> The keyword template shall not appear immediately after a declarative nested-name-specifier.
[expr.prim.id.qual] p2 defines a declarative nested-name-specifier as follows:
> A nested-name-specifier is declarative if it is part of
> - a class-head-name,
> - an enum-head-name,
> - a qualified-id that is the id-expression of a declarator-id, or
> - a declarative nested-name-specifier.
Note: I believe this definition is defective as it doesn't include _nested-name-specifiers_ appearing in _elaborated-type-specifiers_ that declare partial/explicit specializations and explicit instantiations. See my post to the core reflector. Minus a few bugs that are addressed by this PR, this is how we implement it.
This means that declarations like:
```
template<typename>
struct A
{
template<typename>
struct B
{
void f();
};
};
template<typename T>
template<typename U>
void A<T>::template B<U>::f() { } // error: 'template' cannot be used after a declarative nested name specifier
```
are ill-formed. This PR add diagnostics for such declarations. The name of the diagnostic group is `template-in-declaration-name`.
Regarding the aforementioned "few bugs that are addressed by this PR" in order to correctly implement this:
- `CheckClassTemplate` did not call `diagnoseQualifiedDeclaration` when the semantic context was dependent. This allowed for constructs like:
```
struct A
{
template<typename T>
struct B
{
template<typename U>
struct C;
};
};
template<typename T>
template<typename U>
struct decltype(A())::B<T>::C { };
```
- `ActOnClassTemplateSpecialization` did not call `diagnoseQualifiedDeclaration` at all, allowing for qualified partial/explicit specializations at class scope and other related nonsense
- `TreeTransform::TransformNestedNameSpecifierLoc` would rebuild a `NestedNameSpecifier::TypeSpecWithTemplate` as a `NestedNameSpecifier::TypeSpec`
- `TemplateSpecializationTypeLoc::initializeLocal` would set the `template` keyword `SourceLocation` to the provided `Loc` parameter, which would result in a `TemplateSpecializationTypeLoc` obtained via `ASTContext::getTrivialTypeSourceInfo` being displayed as always having a `template` prefix (since the presence of the keyword is not stored anywhere else).
Commit: 9cc2122bf5a81f7063c2a32b2cb78c8d615578a1
https://github.com/llvm/llvm-project/commit/9cc2122bf5a81f7063c2a32b2cb78c8d615578a1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/type-traits.cpp
M libcxx/include/__type_traits/is_nothrow_convertible.h
Log Message:
-----------
[Clang][libc++] Implement __is_nothrow_convertible and use it in libc++ (#80436)
GCC 13 has implemented this builtin.
Commit: d4de4c3eafa9b70c255a4d6d5a14dccff79d10e9
https://github.com/llvm/llvm-project/commit/d4de4c3eafa9b70c255a4d6d5a14dccff79d10e9
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/Sema/inline-asm-validate-aarch64.c
M llvm/docs/LangRef.rst
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
Log Message:
-----------
[AArch64] Support optional constant offset for constraint "S" (#80255)
Modify the initial implementation (https://reviews.llvm.org/D46745) to
support a constant offset so that the following code will compile:
```
int a[2][2];
void foo() { asm("// %0" :: "S"(&a[1][1])); }
```
We use the generic code path for "s". In GCC's aarch64 port, "S" is
supported for PIC while "s" isn't, making "s" less useful. We implement
"S" but not "s".
Similar to #80201 for RISC-V.
Commit: ef1f999e13bd58394bc1099c87a470d91682153d
https://github.com/llvm/llvm-project/commit/ef1f999e13bd58394bc1099c87a470d91682153d
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M lld/wasm/InputFiles.cpp
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/Object/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
Log Message:
-----------
[Object][Wasm] Move WasmSymbolInfo directly into WasmSymbol (NFC) (#80219)
Move the WasmSymbolInfos from their own vector on the WasmLinkingData
directly into the WasmSymbol object. Removing the const-ref to an
external object allows the vector of WasmSymbols to be safely
expanded/reallocated; generating symbol info from the name section will
require this, as the numbers of function and data segment names are
stored separately.
This is a step toward generating symbol information from name sections
for #76107
Commit: 74fb205876be681d2ca9d8bdd23e171e671df5e1
https://github.com/llvm/llvm-project/commit/74fb205876be681d2ca9d8bdd23e171e671df5e1
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.signed_integral.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.unsigned_integral.pass.cpp
Log Message:
-----------
[libc++][format] Improves tests. (#76291)
Tests the returned type. This was first done for the vector<bool>
formatters. This adds it to the other formatters where it wasn't done
yet.
Commit: 7ca4012e115a39c09647bbd28105ea7e5edcd441
https://github.com/llvm/llvm-project/commit/7ca4012e115a39c09647bbd28105ea7e5edcd441
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/docs/AliasingAnalysisFIR.md
M flang/docs/FIRArrayOperations.md
M flang/docs/FlangDriver.md
M flang/docs/HighLevelFIR.md
M flang/docs/OpenACC-descriptor-management.md
M flang/docs/Overview.md
M flang/docs/ParameterizedDerivedTypes.md
M flang/docs/PolymorphicEntities.md
M flang/docs/ProcedurePointer.md
M flang/docs/conf.py
M flang/docs/index.md
Log Message:
-----------
[flang][docs] Fix broken flang website (#80363)
These are several fixes for the flang site. The look has been changed to
match clang since flang, like clang, is a frontend. Some broken links
were removed. Most fixes are to secton titles so the table of contents
is generated correctly. A minor typo has been fixed.
Commit: ad0acf9ef6ff219795159663dbf59116fef416db
https://github.com/llvm/llvm-project/commit/ad0acf9ef6ff219795159663dbf59116fef416db
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[GISEL] More accounting for scalable vectors when operating on LLTs (#80372)
This is stacked on by #80377 and #80378
Commit: bc06cd5cbcfc22dd976f6742d10bc934e1353b8a
https://github.com/llvm/llvm-project/commit/bc06cd5cbcfc22dd976f6742d10bc934e1353b8a
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A .github/workflows/issue-write.yml
M .github/workflows/pr-code-format.yml
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
[workflows] Split pr-code-format into two parts to make it more secure (#78216)
Actions triggered by pull_request_target events have access to all
repository secrets, so it is unsafe to use them when executing untrusted
code. The pr-code-format workflow does not execute any untrusted code,
but it passes untrused input into clang-format. An attacker could use
this to exploit a flaw in clang-format and potentially gain access to
the repository secrets.
By splitting the workflow, we can use the pull_request target which is
more secure and isolate the issue write permissions in a separate job.
The pull_request target also makes it easier to test changes to the
code-format-helepr.py script, because the version of the script from the
pull request will be used rather than the version of the script from
main.
Fixes #77142
Commit: dd0356d741aefa25ece973d6cc4b55dcb73b84b4
https://github.com/llvm/llvm-project/commit/dd0356d741aefa25ece973d6cc4b55dcb73b84b4
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/utils/perf-training/CMakeLists.txt
M clang/utils/perf-training/perf-helper.py
M llvm/docs/AdvancedBuilds.rst
Log Message:
-----------
[CMake][PGO] Add option for using an external project to generate profile data (#78879)
The new CLANG_PGO_TRAINING_DATA_SOURCE_DIR allows users to specify a
CMake project to use for generating the profile data. For example, to
use the llvm-test-suite to generate profile data you would do:
$ cmake -G Ninja -B build -S llvm -C <path to
source>/clang/cmake/caches/PGO.cmake \
-DBOOTSTRAP_CLANG_PGO_TRAINING_DATA_SOURCE_DIR=<path to llvm-test-suite>
\
-DBOOTSTRAP_CLANG_PGO_TRAINING_DEPS=runtimes
Note that the CLANG_PERF_TRAINING_DEPS has been renamed to
CLANG_PGO_TRAINING_DEPS.
---------
Co-authored-by: Petr Hosek <phosek at google.com>
Commit: e12be9cde44f92bc5a788930508a7fd13db78f11
https://github.com/llvm/llvm-project/commit/e12be9cde44f92bc5a788930508a7fd13db78f11
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/test/CodeGen/RISCV/rv64-legal-i32/condops.ll
Log Message:
-----------
[RISCV] Don't promote ISD::SELECT with rv64-legal-i32 when XTHeadCondMov is enabled.
Fixes an infinite loop.
Test copied from the non-rv64-legal-i32 test.
Commit: 1ac68462637749d44695361cfce3225cc107fd4e
https://github.com/llvm/llvm-project/commit/1ac68462637749d44695361cfce3225cc107fd4e
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
A mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dilated_conv_2d_nhwc_hwcf.mlir
Log Message:
-----------
[mlir][sparse] support sparse dilated convolution. (#80470)
Commit: 9a4a4c3f740226ecfe78db407b5b4333bfe2f8bc
https://github.com/llvm/llvm-project/commit/9a4a4c3f740226ecfe78db407b5b4333bfe2f8bc
Author: David Blaikie <dblaikie at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/ADT/StringMap.h
M llvm/lib/Support/StringMap.cpp
M llvm/unittests/ADT/StringMapTest.cpp
Log Message:
-----------
Reapply "[ADT][StringMap] Add ability to precompute and reuse the string hash"
Reverted due to an internally discovered lld crash, which turned out to
be an existing lld bug that got tickled by this changes. That's
addressed in dee8786f70a3d62b639113343fa36ef55bdbad63 so let's have
another go with this change.
Original commit message:
Useful for lldb's const string pool, using the hash to determine which
string map to lock and query/insert.
Derived from https://reviews.llvm.org/D122974 by Luboš Luňák
This reverts commit f976719fb2cb23364957e5993f7fc3684ee15391.
Effectively reapplying 67c631d283fc96d652304199cd625be426b98f8e.
Commit: f6b387589d648945372528a4ac77c58f310e5165
https://github.com/llvm/llvm-project/commit/f6b387589d648945372528a4ac77c58f310e5165
Author: David Blaikie <dblaikie at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M lldb/source/Utility/ConstString.cpp
M llvm/lib/Support/StringMap.cpp
Log Message:
-----------
Reapply "lldb: Cache string hash during ConstString pool queries/insertions"
Reverted due to an internally discovered lld crash due to the underlying
StringMap changes, which turned out to be an existing lld bug that got
tickled by the StringMap changes. That's addressed in
dee8786f70a3d62b639113343fa36ef55bdbad63 so let's have another go with
this change.
Original commit message:
lldb was rehashing the string 3 times (once to determine which StringMap
to use, once to query the StringMap, once to insert) on insertion (twice
on successful lookup).
This patch allows the lldb to benefit from hash improvements in LLVM
(from djbHash to xxh3).
Though further changes would be needed to cache this value to disk - we
shouldn't rely on the StringMap::hash remaining the same in the
future/this value should not be serialized to disk. If we want cache
this value StringMap should take a hashing template parameter to allow
for a fixed hash to be requested.
This reverts commit 5bc1adff69315dcef670e9fcbe04067b5d5963fb.
Effectively reapplying the original 2e197602305be18b963928e6ae024a004a95af6d.
Commit: 06c14c03dae6dcd0b24b5b0e427bbecd97cf0eff
https://github.com/llvm/llvm-project/commit/06c14c03dae6dcd0b24b5b0e427bbecd97cf0eff
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
R .github/workflows/issue-write.yml
M .github/workflows/pr-code-format.yml
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
Revert "[workflows] Split pr-code-format into two parts to make it more secure (#78216)"
This reverts commit bc06cd5cbcfc22dd976f6742d10bc934e1353b8a.
This caused the job to fail for PRs which still had an older version
of code-format-helper.py in their tree.
Commit: 095367a521fc9ff714e1779e507bdd91d4fe9c7d
https://github.com/llvm/llvm-project/commit/095367a521fc9ff714e1779e507bdd91d4fe9c7d
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
Log Message:
-----------
[LLVM][DWARF] Chnage order for .debug_names abbrev print out (#80229)
This stemps from conversatin in:
https://github.com/llvm/llvm-project/pull/77457#discussion_r1457889792.
Right now Abbrev code for abbrev is combination of DIE TAG and other
attributes.
In the future it will be changed to be an index. Since DenseSet does not
preserve an order, added a sort based on abbrev code. Once change to
index is
made, it will print out abbrevs in the order they are stored.
Commit: 2352fdd2026e36c4206053331deba1a70b70d925
https://github.com/llvm/llvm-project/commit/2352fdd2026e36c4206053331deba1a70b70d925
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
R libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
R libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
Revert "[libc++] Optimize vector growing of trivially relocatable types (#76657)"
Broke sanitizer bots: https://lab.llvm.org/buildbot/#/builders/5/builds/40641
This reverts commit 67eee4a029797c09129889c3655416d1be487cfe.
Commit: cc38cd856d9a9df77d5d727377e38a891807774b
https://github.com/llvm/llvm-project/commit/cc38cd856d9a9df77d5d727377e38a891807774b
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.h
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.h
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.h
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.cpp
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.h
M clang-tools-extra/clang-tidy/llvm/HeaderGuardCheck.h
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.h
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.h
M clang-tools-extra/clang-tidy/utils/HeaderGuard.cpp
M clang-tools-extra/clang-tidy/utils/HeaderGuard.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/suspicious-include.rst
M clang-tools-extra/docs/clang-tidy/checks/google/build-namespaces.rst
M clang-tools-extra/docs/clang-tidy/checks/google/global-names-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/header-guard.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/definitions-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unused-using-decls.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-anonymous-namespace.rst
Log Message:
-----------
[clang-tidy] Remove check-specific HeaderFileExtensions and Implement… (#80333)
…ationFileExtensions
Deprecated since clang-tidy 17. Use the corresponding global options
instead.
Fixes #61947
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: 7f828c4a2b7d9508ba369efff4dc259974eba048
https://github.com/llvm/llvm-project/commit/7f828c4a2b7d9508ba369efff4dc259974eba048
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn] Add dummy build file for SPIRVTests
sync_source_lists_from_cmake.py checks that every unittest in CMake
also exists in the GN build. 7b08b4360b48 added SPRIVTests, but the GN
build doesn't include the SPIRV target. So add a dummy target for this
to placate the check.
See also VETests in the gn build, which has the same setup.
Commit: 4ca0e00af569d74c479c66d19a5ffaf41fcb08d9
https://github.com/llvm/llvm-project/commit/4ca0e00af569d74c479c66d19a5ffaf41fcb08d9
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn] Fix typo in SPIRVTests dummy target comment
Commit: 9c2446ea7c7149af6057c10a22e55b833bf4cc7a
https://github.com/llvm/llvm-project/commit/9c2446ea7c7149af6057c10a22e55b833bf4cc7a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2352fdd2026e
Commit: 05a6cb208635a54fb63622f13420e4d8549e5ba1
https://github.com/llvm/llvm-project/commit/05a6cb208635a54fb63622f13420e4d8549e5ba1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
A clang/test/SemaCXX/libstdcxx_is_nothrow_convertible_hack.cpp
Log Message:
-----------
[Clang] Allow __is_nothrow_convertible to be used as an identifier (#80476)
`__is_nothrow_convertible` has been used by libstdc++ previously as an
identifier.
Commit: a4cd9812bacf959ba7a1e7dbb022b7546f5952e3
https://github.com/llvm/llvm-project/commit/a4cd9812bacf959ba7a1e7dbb022b7546f5952e3
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
A llvm/include/llvm/IR/Analysis.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
Log Message:
-----------
[NFC][PassManager] Remove PreservedAnalysesT template parameter (#80324)
This is always PreservedAnalyses. Perhaps in the past there was the idea
to make some types of passes return more invalidation information, but
that hasn't happened.
Requires splitting out some analysis classes into a header so
PassManagerInternal.h can see the definition of PreservedAnalyses.
Commit: 52864d9c7bd49ca41191bd34fcee47f61cfea743
https://github.com/llvm/llvm-project/commit/52864d9c7bd49ca41191bd34fcee47f61cfea743
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-half-promote.ll
M llvm/test/CodeGen/ARM/fp16-args.ll
M llvm/test/CodeGen/ARM/fp16-instructions.ll
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/ARM/llvm.exp10.ll
M llvm/test/CodeGen/ARM/llvm.frexp.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/Thumb2/mve-vabd.ll
Log Message:
-----------
[ARM] Switch to soft promoting half types. (#80440)
The traditional promotion is known to generate wrong code.
Fixes #73805.
Commit: 659419ac2f05035cd8ff19806a9e48ccc725d3ba
https://github.com/llvm/llvm-project/commit/659419ac2f05035cd8ff19806a9e48ccc725d3ba
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc
Log Message:
-----------
[builtins][FMV] Remove dead include from fmv/apple.inc. NFC
Commit: ec73441f2b5bea696e6cb5af07e740fa34fb4d47
https://github.com/llvm/llvm-project/commit/ec73441f2b5bea696e6cb5af07e740fa34fb4d47
Author: Usama Hameed <u_hameed at apple.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/Instrumentation/AddressSanitizer/global_with_comdat.ll
Log Message:
-----------
[Clang][Test] Delete hardcoded version string from test (#80384)
Remove hardcoded string from test
rdar://120498671
Commit: 0d6ed8399f35cc8b23a8e6d094379e3d0dd71c45
https://github.com/llvm/llvm-project/commit/0d6ed8399f35cc8b23a8e6d094379e3d0dd71c45
Author: Florian Mayer <fmayer at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC] reorder AND to check cheaper condition first
Commit: 5294ad1d5c995850ecc903ff2c3464d37cfb49c2
https://github.com/llvm/llvm-project/commit/5294ad1d5c995850ecc903ff2c3464d37cfb49c2
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Improve `extf` folder (#80232)
* Use APFloat conversion function to avoid losing information by
converting to `double`. This would be the case with large types like
`f80` or `f128`.
* Check for potential information loss. This is intended for small
floating point types that may have values not present in larger ones
(e.g., f8m2e5fnuz and f16).
* Support folding vector constants.
Commit: 7a94acb2da5b20d12f13f3c5f4eb0f3f46e78e73
https://github.com/llvm/llvm-project/commit/7a94acb2da5b20d12f13f3c5f4eb0f3f46e78e73
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/AST/TypePrinter.cpp
A clang/test/AST/ast-dump-pack-indexing-crash.cpp
Log Message:
-----------
[Clang] Fix a crash when dumping a pack indexing type. (#80439)
Fix a crash caused by incorrect assumptions
Reported here
https://github.com/llvm/llvm-project/pull/72644#discussion_r1469525524
Commit: 5eae09519c8ca208e0d971acce35870955612615
https://github.com/llvm/llvm-project/commit/5eae09519c8ca208e0d971acce35870955612615
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Rename some SubtargetFeature names to remove an extra 's'. NFC
I wrote FeaturesStdExt instead of FeatureStdExt in a previous patch.
Commit: 0ce61e48ce0a2ca401599318401079e42ed5b0f9
https://github.com/llvm/llvm-project/commit/0ce61e48ce0a2ca401599318401079e42ed5b0f9
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libc/docs/index.rst
A libc/docs/search.rst
Log Message:
-----------
[libc] add doc for search.h (#80492)
Commit: 2d2f962c9b646e809c58eccf6a46ed6b619ac252
https://github.com/llvm/llvm-project/commit/2d2f962c9b646e809c58eccf6a46ed6b619ac252
Author: Martin Storsjö <martin at martin.st>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
[openmp] Add a dependency on the separate import library (#80449)
Currently, when doing e.g. "ninja check-openmp", the check-openmp target
only depends on the target "omp", which builds the library. Thus by
doing that, the separate import library "libomp.lib", which is generated
directly from a def file, never gets created, unless one does a separate
invocation first, that builds all targets.
To fix this, make the "omp" target depend on the target for the separate
import library, whenever that is created/used.
Commit: 820f244aa92f11292e59440c9bc5afbdec395b20
https://github.com/llvm/llvm-project/commit/820f244aa92f11292e59440c9bc5afbdec395b20
Author: Yijia Gu <yijiagu at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Add missing dependency in ArithDialect
Commit: 31350c2681b4893a5018ea19ca8f0ed322b8b0b2
https://github.com/llvm/llvm-project/commit/31350c2681b4893a5018ea19ca8f0ed322b8b0b2
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][openacc][NFC] Add information about getters for operands with device_type (#80389)
Add information in the operation's description about which operands must
be accessed with special getters for device_type support.
Commit: 0da21043630c3f5af3806945eb64e1c5ef261798
https://github.com/llvm/llvm-project/commit/0da21043630c3f5af3806945eb64e1c5ef261798
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
A flang/test/Fir/OpenACC/propagate-attr-folding.fir
Log Message:
-----------
[flang][openacc] Do not loose attributes on folding (#80516)
hlfir.declare introduce some boxes that can be later optimized away. The
OpenACC lowering is currently setting some attributes on FIR operations
to track declare variables. When the boxes are optimized away these
attributes are lost. This patch propagate OpenACC attributes from
box_addr op to the defining op of the folding result.
Commit: 42d6eb54752c37c2583301158e30648cf09195a4
https://github.com/llvm/llvm-project/commit/42d6eb54752c37c2583301158e30648cf09195a4
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
Log Message:
-----------
[MemCpyOpt] Handle scalable aggregate types in memmove/memset formation (#80487)
Without this change, the included test cases crash the compiler. I
believe this is fallout from the homogenous scalable struct work from a
while back; I think we just forgot to update this case.
Likely to fix https://github.com/llvm/llvm-project/issues/80463.
Commit: b49fa212891983517f2988c60529c6994e2fed7c
https://github.com/llvm/llvm-project/commit/b49fa212891983517f2988c60529c6994e2fed7c
Author: yubingex007-a11y <bing1.yu at intel.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
Log Message:
-----------
[X86] Stop custom-widening v2f32 = fpext v2bf16 (#80106)
Commit: 82a32140acb52472241f04644cdcf88a4cf4bee8
https://github.com/llvm/llvm-project/commit/82a32140acb52472241f04644cdcf88a4cf4bee8
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/function-type-qual.cpp
Log Message:
-----------
[Clang][Sema] Fix crash with const qualified member operator new (#80327)
We should diagnose a const qualified member operator new but we fail to
do so and this leads to crash during debug info generation.
The fix is to diagnose this as ill-formed in the front-end.
Fixes: https://github.com/llvm/llvm-project/issues/79748
Commit: b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c
https://github.com/llvm/llvm-project/commit/b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix crash in lowerVPSpliceExperimental with RV64LegalI32.
EVL1 will be i32 and not get type legalized to i64 so we need to
manually promote it to XLenVT.
Commit: 78b4e7c5e349d8c101b50affbd260eb109748f8f
https://github.com/llvm/llvm-project/commit/78b4e7c5e349d8c101b50affbd260eb109748f8f
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/test/MC/WebAssembly/tables.s
M llvm/test/MC/WebAssembly/type-checker-errors.s
Log Message:
-----------
[WebAssembly] validate `table.grow` correctly (#80437)
This PR add support in wasm asm type checker to implement checker of
`table.grow`
Fixes: #79966.
Commit: 141de749597c7b59ebe2c4aa7ee573d124dc903c
https://github.com/llvm/llvm-project/commit/141de749597c7b59ebe2c4aa7ee573d124dc903c
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaTemplate/concepts-recovery-expr.cpp
Log Message:
-----------
[clang][Sema] Populate function template depth at AddTemplateOverloadCandidate (#80395)
This is yet another one-line patch to fix crashes on constraint
substitution.
```cpp
template <class, class> struct formatter;
template <class, class> struct basic_format_context {};
template <typename CharType>
concept has_format_function = format(basic_format_context<CharType, CharType>());
template <typename ValueType, typename CharType>
requires has_format_function<CharType>
struct formatter<ValueType, CharType> {
template <typename OutputIt>
CharType format(basic_format_context<OutputIt, CharType>);
};
```
In this case, we would build up a `RecoveryExpr` for a call within a
constraint expression due to the absence of viable functions. The
heuristic algorithm attempted to find such a function inside of a
ClassTemplatePartialSpecialization, from which we started to substitute
its requires-expression, and it succeeded with a FunctionTemplate such
that
1) It has only one parameter, which is dependent.
2) The only one parameter depends on two template parameters. They are,
in canonical form, `<template-parameter-1-0>` and
`<template-parameter-0-1>` respectively.
Before we emit an error, we still want to recover the most viable
functions. This goes downhill to deducing template parameters against
its arguments, where we would collect the argument type with the same
depth as the parameter type into a Deduced set. The size of the set is
presumed to be that of function template parameters, which is 1 in this
case. However, since we haven't yet properly set the template depth
before the dance, we'll end up putting the type for
`<template-parameter-0-1>` to the second position of Deduced set, which
is unfortunately an access violation!
The bug seems to appear since clang 12.0.
This fixes [the
case](https://github.com/llvm/llvm-project/issues/58548#issuecomment-1287935336).
Commit: 7278cb5a388e0f2f4000dc8d6b3b421de66a945b
https://github.com/llvm/llvm-project/commit/7278cb5a388e0f2f4000dc8d6b3b421de66a945b
Author: joyhou-hw <houzhenyu at huawei.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.h
M clang/test/Sema/attr-aligned.c
Log Message:
-----------
[X86] [iamcu] Fix wrong alignment value for attr (aligned) with -miamcu (#80401)
attribute ((aligned)) should be 4 for -miamcu.
relate: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66818
Commit: e7ec0c972e6f5ddd01099fd05ca24352cb992b44
https://github.com/llvm/llvm-project/commit/e7ec0c972e6f5ddd01099fd05ca24352cb992b44
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[CodeGen] Port PrintMIR to new pass manager (#79440)
The legacy version print machine functions to a string stream, then
output the module and string in `doFinalization`. This patch break
`MIRPrintingPass` into two parts `PrintMIRPreparePass` and
`PrintMIRPass`. `PrintMIRPreparePass` output the original IR in yaml
string, `PrintMIRPass` just print the machine function, so we can avoid
the `doFinalization`.
Commit: f5154b9c9888f3b1b243d9a142585fabf643f422
https://github.com/llvm/llvm-project/commit/f5154b9c9888f3b1b243d9a142585fabf643f422
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
Log Message:
-----------
[clang][RISCV] Enable struct of homogeneous scalable vector as function argument (#78550)
llvm IR supports struct as function input, so RISCV tuple
type can just use struct of homogeneous scalable vector instead
of flatten them.
Commit: d9850fe23cc69b784cf655405cdfae7defa44573
https://github.com/llvm/llvm-project/commit/d9850fe23cc69b784cf655405cdfae7defa44573
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvtbf16.c
Log Message:
-----------
[RISCV][clang] Add Zvfbfmin C intrinsics support (#79618)
Commit: cca3db93e0d441f943387d519702db2d3095f4ca
https://github.com/llvm/llvm-project/commit/cca3db93e0d441f943387d519702db2d3095f4ca
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M libc/src/__support/CPP/expected.h
Log Message:
-----------
[libc][NFC] Fix accessor qualifiers for `cpp::expected` (#80424)
Commit: cba1b64099a0558499c7a355db4c59bb5851b6aa
https://github.com/llvm/llvm-project/commit/cba1b64099a0558499c7a355db4c59bb5851b6aa
Author: Michael Klemm <michael.klemm at amd.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/acosd.f90
A flang/test/Lower/Intrinsics/asind.f90
Log Message:
-----------
[flang] Implement ACOSD and ASIND (#80448)
This PR implements two missing intrinsics from F2023: ACOSD and ASIND.
The implementation breaks them down to the existing ACOS and ASIN
implementation.
Commit: 260fe032c2506cd53c6a813a71c2f096ba161e7f
https://github.com/llvm/llvm-project/commit/260fe032c2506cd53c6a813a71c2f096ba161e7f
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[llvm][AArch64][TargetParser][NFC] Use parseArchExtension in parseModifier. (#80427)
This allows making changes in parseArchExtension to make their way in
the command line as well, not only in target attributes.
Commit: 514d0691f4da40d5bb6d618a673e975b8eacfb77
https://github.com/llvm/llvm-project/commit/514d0691f4da40d5bb6d618a673e975b8eacfb77
Author: Danny Mösch <danny.moesch at icloud.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/add_new_check.py
Log Message:
-----------
[clang-tidy] Fix warnings caused by "new check" template (#80537)
Commit: 752c172bc7d628fe5ce4a78f3620893b8d7bcfba
https://github.com/llvm/llvm-project/commit/752c172bc7d628fe5ce4a78f3620893b8d7bcfba
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiate.cpp
A clang/test/SemaTemplate/default-parm-init.cpp
Log Message:
-----------
[Clang][Sema] fix outline member function template with default align crash (#80288)
Try to fix [issue](https://github.com/llvm/llvm-project/issues/68490 )
and some extented problem. Root cause of current issue is that error
handling in instantiation of function parameter with default
initialization on sizeof or align expression. When instance an
out-of-line template member function, depth of `TemplateTypeParmDecl` in
default initialization doesn't change while depth of other template
parameter does and this will lead to some template parameter
uninstanced. Also, sometime it will leader to wrong instantiation when
it uses the template parameter of the template class.
Fix it by add template args of context. This will make
MultiLevelTemplateArgumentList::getNumLevels matching the depth of
template parameter. Testcase with some static_assert demonstrates the
template parameter has been instanced correctly.
But, the default initialization of lambda expression compiles failed
when only checking if the member function is out-of-line. We should
check the `PrimaryFunctionTemplateDecl` of the funtion if it's
out-of-line.
Co-authored-by: huqizhi <836744285 at qq.com>
Commit: 248aeac1ad2cf4f583490dd1312a5b448d2bb8cc
https://github.com/llvm/llvm-project/commit/248aeac1ad2cf4f583490dd1312a5b448d2bb8cc
Author: Martin Storsjö <martin at martin.st>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M compiler-rt/lib/builtins/i386/chkstk.S
M compiler-rt/lib/builtins/x86_64/chkstk.S
Log Message:
-----------
[compiler-rt] Remove duplicate MS names for chkstk symbols (#80450)
Prior to 885d7b759b5c166c07c07f4c58c6e0ba110fb0c2, the builtins library
contained two chkstk implementations for each of i386 and x86_64, one
that was used in mingw environments, and one unused (with a symbol name
not matching anything that is used anywhere). Some of the functions
additionally had other, also unused, aliases.
After cleaning this up in 885d7b759b5c166c07c07f4c58c6e0ba110fb0c2, the
unused symbol names were removed.
At the same time, symbol aliases were added for the names as they are
used by MSVC; the functions are functionally equivalent, but have
different names between mingw and MSVC style environments.
By adding a symbol alias (so that one object file contains two different
symbols for the same function), users can run into problems with
duplicate definitions, if they themselves define one of the symbols (for
various reasons), but need to link in the other one.
This happens for Wine, which provides their own definition of
"__chkstk", but when built in mingw mode does need compiler-rt to
provide the mingw specific symbol names; see
https://github.com/mstorsjo/llvm-mingw/issues/397.
To avoid the issue, remove the extra MS style names. They weren't
entirely usable as such for MSVC style environments anyway, as
compiler-rt builtins don't build these object files at all, when built
in MSVC mode; thus, the effort to provide them for MSVC style
environments in 885d7b759b5c166c07c07f4c58c6e0ba110fb0c2 was a
half-hearted step towards that.
If we really do want to provide those functions (as an alternative to
the ones provided by MSVC itself), we should do it in a separate object
file (even if the function implementation is the same), so that users
who have a definition of one of them but need a definition of the other,
won't have conflicts.
Additionally, if we do want to provide them for MSVC, those files
actually should be built when building the builtins in MSVC mode as well
(see compiler-rt/lib/builtins/CMakeLists.txt).
If we do that, there's a risk that an MSVC style build ends up linking
in and preferring our implementation over the one provided by MSVC,
which would be suboptimal. Our implementation always probes the
requested amount of stack, while the MSVC one checks the amount of
allocated stack and only probes as much as really is needed.
In short - this reverts the situation to what it was in the 17.x release
series (except for unused functions that have been removed).
Commit: 2906f3626b54136b885d82d2b28b7991f3d728ae
https://github.com/llvm/llvm-project/commit/2906f3626b54136b885d82d2b28b7991f3d728ae
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Update ::onlyScalarsGenerated to take IsScalable bool (NFCI).
Instead of passing in a full VF, just pass IsScalable as bool.
Commit: 693647902076034e7c81f380d1b937a65aef8ae6
https://github.com/llvm/llvm-project/commit/693647902076034e7c81f380d1b937a65aef8ae6
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Mark vputils::onlyFirstLaneUsed arg as const (NFC)
Split off https://github.com/llvm/llvm-project/pull/80269 as suggested.
Commit: 3444240540b0b36902dc8b9b11339b8969f7bca9
https://github.com/llvm/llvm-project/commit/3444240540b0b36902dc8b9b11339b8969f7bca9
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Mark vputils::onlyFirstPartUsed arg as const (NFC)
Split off https://github.com/llvm/llvm-project/pull/80269 as
suggested.
Commit: 47abbf4fe956ad1c12832de03c8ae3294eb5cb78
https://github.com/llvm/llvm-project/commit/47abbf4fe956ad1c12832de03c8ae3294eb5cb78
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
Log Message:
-----------
[VPlan] Update VPInst::onlyFirstLaneUsed to check users. (#80269)
A VPInstruction only has its first lane used if all users use its first
lane only. Use vputils::onlyFirstLaneUsed to continue checking the
recipe's users to handle more cases.
Besides allowing additional introduction of scalar steps when
interleaving in some cases, this also enables using an Add VPInstruction
to model the increment - as a follow up.
Commit: 5ca2777c69f8708d583e230c56ac7f5f6376fb40
https://github.com/llvm/llvm-project/commit/5ca2777c69f8708d583e230c56ac7f5f6376fb40
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M libcxx/include/valarray
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/get.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/and_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/divide_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/minus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/modulo_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/or_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/plus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_left_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_right_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/times_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/xor_valarray.pass.cpp
Log Message:
-----------
[libc++] Fixes valarray proxy type compound assignment operations. (#76528)
The valarray<>::operator[](...) const functions return proxy objects.
The valarray<>::operator[](...) functions return valarray objects.
However the standard allows functions returning valarray objects to
return custom proxy objects instead. Libc++ returns __val_expr proxies.
Functions taking a valarray object must work with the custom proxies
too. Therefore several operations have a custom proxy overload instead
of valarray overloads.
Libc++ doesn't specify a valarray overload. This is an issue with the
standard proxy types; these can implicitly be converted to a valarray.
The solution is to allow the standard proxies to behave as-if they are
custom proxies.
This patch fixes the valarray compound assignments. Other operations,
like the binary non-member functions are not fixed. These will be done
in a followup patch.
Fixes: https://github.com/llvm/llvm-project/issues/21320
Commit: 7189219ec9fc768f159917052b4b5998d077c39f
https://github.com/llvm/llvm-project/commit/7189219ec9fc768f159917052b4b5998d077c39f
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/include/llvm/TextAPI/Utils.h
M llvm/lib/TextAPI/Utils.cpp
A llvm/test/tools/llvm-readtapi/Inputs/libSystem.1.yaml
A llvm/test/tools/llvm-readtapi/stubify-delete.test
A llvm/test/tools/llvm-readtapi/stubify-simple.test
A llvm/test/tools/llvm-readtapi/stubify-symlink.test
R llvm/test/tools/llvm-readtapi/stubify.test
M llvm/tools/llvm-readtapi/TapiOpts.td
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[readtapi] Add support for stubify-ing directories (#76885)
When given a directory input `llvm-readtapi` traverses through the
directory to find dylibs or tbd files to operate on. TBD files will be
created with the same base file name as the dylib. Symlinks should be
created if the input is one.
This also introduces options to delete input files which are defined as
library files that existed before `readtapi -stubify` was invoked. Also
the ability to delete private libraries where private libraries are in a
predefined file system locations on darwin based platforms.
Commit: ab9a69878c7a14b85389c16e130ea117ee4f4358
https://github.com/llvm/llvm-project/commit/ab9a69878c7a14b85389c16e130ea117ee4f4358
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M flang/lib/Parser/preprocessor.cpp
Log Message:
-----------
[flang] Simplify a string comparison (NFC)
Commit: 8926af426f202c158dd17b2034c044e85eceb108
https://github.com/llvm/llvm-project/commit/8926af426f202c158dd17b2034c044e85eceb108
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Support/VirtualFileSystem.cpp
Log Message:
-----------
[Support] Use StringRef::starts_with (NFC)
Commit: 9ad78b0994a2a1d7c28f463a89585a0ffd5310e4
https://github.com/llvm/llvm-project/commit/9ad78b0994a2a1d7c28f463a89585a0ffd5310e4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
Log Message:
-----------
[Lanai] Use StringRef::consume_back (NFC)
Commit: 06da452ba7d8d4959cb5070727b842eea4c8af71
https://github.com/llvm/llvm-project/commit/06da452ba7d8d4959cb5070727b842eea4c8af71
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Analysis/LoopInfo.cpp
Log Message:
-----------
[Analysis] Use range-based for loops (NFC)
Commit: 0ed02621b9d87342daff0dcd9014319d4eeb2735
https://github.com/llvm/llvm-project/commit/0ed02621b9d87342daff0dcd9014319d4eeb2735
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
A llvm/test/tools/llvm-readtapi/stubify-symlink-darwin.test
R llvm/test/tools/llvm-readtapi/stubify-symlink.test
Log Message:
-----------
[readtapi] make symlink test darwin only
Appeases bots for now.
Commit: 5bcd91058ee4855804780c4ae35ac87ed45a4b58
https://github.com/llvm/llvm-project/commit/5bcd91058ee4855804780c4ae35ac87ed45a4b58
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[readtapi] Use ExitOnError instead of errorcodes for `readlink` wrapper
Silences: ` error C4716: 'read_link': must return a value` windows error
Commit: f87e3b61c8b6af896aebf551a03b2387e71dfe73
https://github.com/llvm/llvm-project/commit/f87e3b61c8b6af896aebf551a03b2387e71dfe73
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__locale
A libcxx/include/__locale_dir/locale_base_api.h
A libcxx/include/__locale_dir/locale_base_api/android.h
A libcxx/include/__locale_dir/locale_base_api/fuchsia.h
A libcxx/include/__locale_dir/locale_base_api/ibm.h
A libcxx/include/__locale_dir/locale_base_api/musl.h
A libcxx/include/__locale_dir/locale_base_api/newlib.h
A libcxx/include/__locale_dir/locale_base_api/openbsd.h
A libcxx/include/__locale_dir/locale_base_api/win32.h
R libcxx/include/__support/android/locale_bionic.h
R libcxx/include/__support/fuchsia/xlocale.h
R libcxx/include/__support/ibm/xlocale.h
R libcxx/include/__support/musl/xlocale.h
R libcxx/include/__support/newlib/xlocale.h
R libcxx/include/__support/openbsd/xlocale.h
R libcxx/include/__support/win32/locale_win32.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/src/locale.cpp
Log Message:
-----------
[libc++] Move the locale support headers to __locale_dir/locale_base_api/ (#74522)
Differential Revision: https://reviews.llvm.org/D147869
Commit: b205ea15c1573fd3c55d2356a22a9068c55c8065
https://github.com/llvm/llvm-project/commit/b205ea15c1573fd3c55d2356a22a9068c55c8065
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port f87e3b61c8b6
Commit: de4360d7d535ffff9e655fdb40657cf95871ec6c
https://github.com/llvm/llvm-project/commit/de4360d7d535ffff9e655fdb40657cf95871ec6c
Author: David Green <david.green at arm.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] Add extra scalable typesize and offset tests. NFC
A collection of tests from #69152 and for constant offsets with scalable typesizes.
Commit: d62c5706a8fabca8b14484ce5078b03756f8a37b
https://github.com/llvm/llvm-project/commit/d62c5706a8fabca8b14484ce5078b03756f8a37b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Custom legalize i32 SMULO with RV64LegalI32.
The default lowering will use shifts to make use of an i32 setcc.
We don't support i32 setcc, so its better to sig extend the low
32 bits and compare the full 64 bit result. This gives produces
mul+mulw+xor+snez like we do without RV64LegalI32.
Commit: f09092434423be14f32781d8ae263dc041d24551
https://github.com/llvm/llvm-project/commit/f09092434423be14f32781d8ae263dc041d24551
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Custom legalize i32 SADDO/SSUBO with RV64LegaI32.
The default legalization uses 2 compares and an xor. We can instead
use add+addw+xor+snez like we do without RV64LegaI32.
Commit: ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44
https://github.com/llvm/llvm-project/commit/ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Add more RUN lines to rv64-legal-i32/xaluo.ll. NFC
This matches the non-rv64-legal-i32 version.
Commit: 9d00c3413299f537748e448e7197d6942c4651ea
https://github.com/llvm/llvm-project/commit/9d00c3413299f537748e448e7197d6942c4651ea
Author: David Green <david.green at arm.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-mov.ll
Log Message:
-----------
[AArch64] Extend and cleanup movi tests. NFC
Commit: 2333865546cb6d4cda7b511ed07b8cb66a0d4eab
https://github.com/llvm/llvm-project/commit/2333865546cb6d4cda7b511ed07b8cb66a0d4eab
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M openmp/libomptarget/include/device.h
M openmp/libomptarget/src/omptarget.cpp
M openmp/libomptarget/test/offloading/dynamic_module_load.c
Log Message:
-----------
[Libomptarget] Fix data mapping on dynamic loads (#80559)
Summary:
The current logic tries to map target mapping tables to the current
device. Right now it assumes that data is only mapped a single time per
device. This is only true if we have a single instance of the runtime
running on a single program. However, in the case of dynamic library
loads or shared libraries, this may happen multiple times.
Given a case of a simple dynamic library load which has its own target
kernel instruction, the current logic had only the first call to
`__tgt_target_kernel` to the data mapping for that device. Then, when
the next dynamic library load got called, it would see that the global
were already mapped for that device and skip registering its own
entires, even though they were distinct. This resulted in none of the
mappings being done and hitting an assertion.
This patch simply gets rid of this per-device check. The check should
instead be on the host offloading entries. We already have logic that
calls `continue` if we already have entries for that pointer, so we can
simply rely on that instead.
Commit: 08e942aca64d4d16e55a25d7e7eda8ef192727fd
https://github.com/llvm/llvm-project/commit/08e942aca64d4d16e55a25d7e7eda8ef192727fd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)) for RV64LegalI32.
This is needed with RV64LegalI32 when the setcc is created after type
legalization. An i1 xor would have been promoted to i32, but the setcc
would have i64 result.
Commit: 390b99743bdd60649414fe470d7a9bacc9992231
https://github.com/llvm/llvm-project/commit/390b99743bdd60649414fe470d7a9bacc9992231
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
A llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
Log Message:
-----------
[InstCombine] Handle isNanOrInf idioms (#80414)
This patch folds:
```
(icmp eq (and (bitcast X to int), ExponentMask), ExponentMask) --> llvm.is.fpclass(X, fcInf|fcNan)
(icmp ne (and (bitcast X to int), ExponentMask), ExponentMask) --> llvm.is.fpclass(X, ~(fcInf|fcNan))
```
Alive2: https://alive2.llvm.org/ce/z/_hXAAF
Commit: 4e112e5c1c8511056030294af3264da35f95d93c
https://github.com/llvm/llvm-project/commit/4e112e5c1c8511056030294af3264da35f95d93c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
A libcxx/test/std/containers/sequences/vector/vector.modifiers/destory_elements.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
Reapply "[libc++] Optimize vector growing of trivially relocatable types" (#80558)
This reapplies #76657. Non-trivial elements didn't get destroyed
previously. This fixes the bug and adds tests for all the vector
insertion functions.
Commit: 6ad692b7b3416f632e1d38cef3cc83f618f428b0
https://github.com/llvm/llvm-project/commit/6ad692b7b3416f632e1d38cef3cc83f618f428b0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 4e112e5c1c85
Commit: 61ff9f8db8d18002767ea27f83a4bfb8ed47f255
https://github.com/llvm/llvm-project/commit/61ff9f8db8d18002767ea27f83a4bfb8ed47f255
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
Log Message:
-----------
[X86] Add strictfp version of PR43024 test. (#80573)
For the current version of the PR43024 test, we should be able to
optimize away the operations but fail to do so. This commit adds a
strictfp version of the test where we should not be able to optimize
away the operations, as a verification that changes to improve the other
effect have no adverse effect.
Commit: 1da2921bbdff847eb57184f3d5e7ae5c363b9e88
https://github.com/llvm/llvm-project/commit/1da2921bbdff847eb57184f3d5e7ae5c363b9e88
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Add missing extload test cases to xtheadmemidx.ll. NFC
We had the isel patterns, but no tests that used them. We only had
sextload and zextload tests.
Also reduce the alignment on some of the test cases that were
unnecessarily over aligned.
Commit: f2cf8da636ee2b27b54f14fea540d7ef75cebc05
https://github.com/llvm/llvm-project/commit/f2cf8da636ee2b27b54f14fea540d7ef75cebc05
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Add more XTheadMemIdx patterns for -riscv-experimental-rv64-legal-i32.
Commit: a3d8b78333b80b47209ad0dc8f8159d70c7fcb39
https://github.com/llvm/llvm-project/commit/a3d8b78333b80b47209ad0dc8f8159d70c7fcb39
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenCXX/dynamic-cast-dead.cpp
M clang/test/CodeGenCXX/dynamic-cast.cpp
Log Message:
-----------
[Clang][CodeGen] Mark `__dynamic_cast` as `willreturn` (#80409)
According to the C++ standard, `dynamic_cast` of pointers either returns
a pointer (7.6.1.7) or results in undefined behavior (11.9.5). This
patch marks `__dynamic_cast` as `willreturn` to remove unused calls.
Fixes #77606.
Commit: 9dfdea6fbddfa871dab32c3322259babcc13dcdc
https://github.com/llvm/llvm-project/commit/9dfdea6fbddfa871dab32c3322259babcc13dcdc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll
Log Message:
-----------
[RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.
Commit: b0f0babff22e9c0af74535b05e2c6424392bb24a
https://github.com/llvm/llvm-project/commit/b0f0babff22e9c0af74535b05e2c6424392bb24a
Author: Koakuma <koachan at protonmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/sparc64-codemodel.c
Log Message:
-----------
[clang] Add GCC-compatible code model names for sparc64
This adds GCC-compatible names for code model selection on 64-bit SPARC
with absolute code.
Testing with a 2-stage build then running codegen tests works okay under
all of the supported code models.
(32-bit target does not have selectable code models)
Reviewed By: @brad0, @MaskRay
Commit: b4eb7a10c01162b17cb5dc94a97d9d137bb6fe57
https://github.com/llvm/llvm-project/commit/b4eb7a10c01162b17cb5dc94a97d9d137bb6fe57
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
A llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
Log Message:
-----------
[GlobalISel][ARM] Legalze set_fpenv and get_fpenv (#79852)
Implement handling of get/set floating point environment for ARM in
Global Instruction Selector. Lowering of these intrinsics to operations
on FPSCR was previously inplemented in DAG selector, in GlobalISel it is
reused.
Commit: d25022bb689b9bf48a24c0ae6c29c1d3c2f32823
https://github.com/llvm/llvm-project/commit/d25022bb689b9bf48a24c0ae6c29c1d3c2f32823
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[workflows] Stop using the build-test-llvm-project action (#80580)
This action is really just a wrapper around cmake and ninja. It doesn't
add any value to the builds, and I don't think we need it now that there
are reusable workflows.
Commit: 2193c95e2459887e7e6e4f9f4aacf9252e99858f
https://github.com/llvm/llvm-project/commit/2193c95e2459887e7e6e4f9f4aacf9252e99858f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[workflows] Only run code formatter on the main branch (#80348)
Modifying a cherry-picked patch to fix code formatting issues can be
risky, so we don't typically do this. Therefore, it's not necessary to
run this job on the release branches.
Commit: 7d269a484142459a1154ba81c68bf0c31f291fc8
https://github.com/llvm/llvm-project/commit/7d269a484142459a1154ba81c68bf0c31f291fc8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
Log Message:
-----------
[CodeGen] Use range-based for loops (NFC)
Commit: 3be989e8c30f3cad61e5e1fa54199fc45edf7ff7
https://github.com/llvm/llvm-project/commit/3be989e8c30f3cad61e5e1fa54199fc45edf7ff7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
Log Message:
-----------
[FileCheck] Use StringRef::rtrim (NFC)
Commit: 3c93c037c9ede2eaa0bdea6924c92d646ca0cfe5
https://github.com/llvm/llvm-project/commit/3c93c037c9ede2eaa0bdea6924c92d646ca0cfe5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
Log Message:
-----------
[Basic] Use StringRef::ends_with (NFC)
Commit: 34fba4fb1e32f06237e5024373cc0163cecc3fd5
https://github.com/llvm/llvm-project/commit/34fba4fb1e32f06237e5024373cc0163cecc3fd5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/Basic/Sarif.cpp
Log Message:
-----------
[Basic] Use StringRef::contains (NFC)
Commit: a37e8b85ee5187bc7a1fed7adce8ed5693215795
https://github.com/llvm/llvm-project/commit/a37e8b85ee5187bc7a1fed7adce8ed5693215795
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
Log Message:
-----------
[ExecutionEngine] Simplify a string comparison (NFC)
Commit: 1b33b3f27f8bf3902d754ed83da29f9a6f15e4e1
https://github.com/llvm/llvm-project/commit/1b33b3f27f8bf3902d754ed83da29f9a6f15e4e1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
Log Message:
-----------
[MIRParser] Simplify a string comparison (NFC)
Commit: 9d2e8dca12c8bbb70223eeb74330fe603e215ce3
https://github.com/llvm/llvm-project/commit/9d2e8dca12c8bbb70223eeb74330fe603e215ce3
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/test/MC/WebAssembly/tables.s
M llvm/test/MC/WebAssembly/type-checker-errors.s
Log Message:
-----------
[WebAssembly] fix `table.grow` type checker (#80572)
table.grow is valid with type `[t i32] -> [i32]`.
Fixes: #79966.
Commit: 3bcb1f2bdd5c70b2ac4aff3290996486d9ae0236
https://github.com/llvm/llvm-project/commit/3bcb1f2bdd5c70b2ac4aff3290996486d9ae0236
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV] Rework isSignExtendingOpW to store Register in the worklist.
Previously we stored MachineInstr which restricted the implementation
to only handle operand 0.
The TH_LWD instruction has two sign extended destinations.
Commit: bc9c2be3577c58d3daabff995360bd9bea44b0b9
https://github.com/llvm/llvm-project/commit/bc9c2be3577c58d3daabff995360bd9bea44b0b9
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/minmax.ll
Log Message:
-----------
[ConstraintElim] Simplify `MinMaxIntrinsic` (#75306)
This patch replaces min/max intrinsic with one of its operands if
possible.
Alive2: https://alive2.llvm.org/ce/z/LoHfYf
Fixes #75155.
Commit: 72105605d1fbc816c1219bb1d719693291322011
https://github.com/llvm/llvm-project/commit/72105605d1fbc816c1219bb1d719693291322011
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/test/CodeGen/target-builtin-noerror.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Support more ISAs to enable __builtin_cpu_supports (#79086)
This patch will also expand supports for attribute/target, while
the priority of newly supported ISAs will be set to zero.
Commit: d71ef3e75c6325f0c10c19ee34e2c0337a0fd452
https://github.com/llvm/llvm-project/commit/d71ef3e75c6325f0c10c19ee34e2c0337a0fd452
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Merge identical setOperationAction calls. NFC.
Commit: 114a33be4751328c549c6b8b05e9ece19e452189
https://github.com/llvm/llvm-project/commit/114a33be4751328c549c6b8b05e9ece19e452189
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Log Message:
-----------
[DAG] getStackAlignedMMO - return the getMachineMemOperand result directly (style). NFC.
Commit: dea855de46bd4d3e103646a7f459856d88dd7488
https://github.com/llvm/llvm-project/commit/dea855de46bd4d3e103646a7f459856d88dd7488
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M mlir/include/mlir/Conversion/SCFToEmitC/SCFToEmitC.h
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
Log Message:
-----------
[mlir][EmitC] Drop unused code (NFC) (#80325)
To register the conversion the autogenerated function
`registerSCFToEmitC()` calls `createSCFToEmitC()`, which itself is also
autogenerated. The removed function, however, isn't used in the upstream
codebase.
Commit: 859b09da08c2a47026ba0a7d2f21b7dca705864d
https://github.com/llvm/llvm-project/commit/859b09da08c2a47026ba0a7d2f21b7dca705864d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rv64-legal-i32/vararg.ll
Log Message:
-----------
[RISCV] Promote i32 ISD::VAARG to i64 for -riscv-experimental-rv64-legal-i32.
Commit: 9ff83f12fe406f9c3c6b2cd0ee96660a7485f29f
https://github.com/llvm/llvm-project/commit/9ff83f12fe406f9c3c6b2cd0ee96660a7485f29f
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M lldb/include/lldb/DataFormatters/FormatCache.h
M lldb/source/DataFormatters/FormatCache.cpp
Log Message:
-----------
[lldb] Remove unnecessary FormatCache::GetEntry (NFC) (#80603)
The implementation of `FormatCache::Entry
&FormatCache::GetEntry(ConstString)` is effectively a duplication of
`std::map::operator[]`. This change deletes `GetEntry` and replaces its
use with `operator[]`.
Commit: 256200732111afd03bb7437564f3a3d77c0ec3f5
https://github.com/llvm/llvm-project/commit/256200732111afd03bb7437564f3a3d77c0ec3f5
Author: rmarker <37921131+rmarker at users.noreply.github.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Add Automatic and ExceptShortType options for AlwaysBreakAfterReturnType. (#78011)
The RTBS_None option in Clang-format avoids breaking after a short
return type.
However, there was an issue with the behaviour in that it wouldn't take
the leading indentation of the line into account.
This meant that the behaviour wasn't applying when intended.
In order to address this situation without breaking the existing
formatting, RTBS_None has been deprecated.
In its place are two new options for AlwaysBreakAfterReturnType.
The option RTBS_Automatic will break after the return type based on
PenaltyReturnTypeOnItsOwnLine.
The option RTBS_ExceptShortType will take the leading indentation into
account and prevent breaking after short return types.
This allows the inconsistent behaviour of RTBS_None to be avoided and
users to decide whether they want to allow breaking after short return
types or not.
Resolves #78010
Commit: 32b99617acbc4773caee45df10a7fd602b8db0ff
https://github.com/llvm/llvm-project/commit/32b99617acbc4773caee45df10a7fd602b8db0ff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
Log Message:
-----------
[RISCV] Custom promote i32 UADDSAT/USUBSAT for -riscv-experimental-rv64-legal-i32 with Zbb.
Commit: 146e5ce481f3a9232f2188cc664a65e98f8a0985
https://github.com/llvm/llvm-project/commit/146e5ce481f3a9232f2188cc664a65e98f8a0985
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
Log Message:
-----------
[RISCV] Add i32 zext.h pattern for -riscv-experimental-rv64-legal-i32.
Commit: ae36790be4a2a6c9dc8900f659c861647cab66d5
https://github.com/llvm/llvm-project/commit/ae36790be4a2a6c9dc8900f659c861647cab66d5
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.proftext
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.proftext
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.proftext
M llvm/test/tools/llvm-cov/mcdc-const.test
M llvm/test/tools/llvm-cov/mcdc-general-none.test
M llvm/test/tools/llvm-cov/mcdc-general.test
Log Message:
-----------
test/llvm-cov: Regenerate MC/DC tests (#80610)
* Revise instructions for regeneration, not to create executables.
* Add instructions to regenerate both object files and test vectors
(except for `mcdc-general-none.proftext`)
* Reformat
Commit: dcb83692cdeaf7fb620fd14992848b6cbc94f773
https://github.com/llvm/llvm-project/commit/dcb83692cdeaf7fb620fd14992848b6cbc94f773
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Log Message:
-----------
[Bitcode] Use range-based for loops (NFC)
Commit: 90e9c6e36e8b928240dfd61c2dfd30cf26108c07
https://github.com/llvm/llvm-project/commit/90e9c6e36e8b928240dfd61c2dfd30cf26108c07
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Object/COFFModuleDefinition.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/FormatVariadic.cpp
Log Message:
-----------
[llvm] Use StringRef::consume_front (NFC)
Commit: ffaedc2735cfcf2595fe65a75ed910a9c661391b
https://github.com/llvm/llvm-project/commit/ffaedc2735cfcf2595fe65a75ed910a9c661391b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
Log Message:
-----------
[Basic] Simplify uses of StringRef::consume_front (NFC)
Commit: e7d3a4f34adbe9ea183c2ec4aea97691d4ec06f5
https://github.com/llvm/llvm-project/commit/e7d3a4f34adbe9ea183c2ec4aea97691d4ec06f5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
Log Message:
-----------
[FileCheck] Simplify a use of StringRef::consume_front (NFC)
Commit: 92d5f644281cba56baa9b42dfc298db7f2c30003
https://github.com/llvm/llvm-project/commit/92d5f644281cba56baa9b42dfc298db7f2c30003
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
Log Message:
-----------
[clang-tidy] Use StringRef::contains (NFC)
Commit: f72da9f4fd389951c4d65055f5471e208f256212
https://github.com/llvm/llvm-project/commit/f72da9f4fd389951c4d65055f5471e208f256212
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[SelectionDAG] Use getShiftAmountConstant to simplify code. NFC (#80561)
Replace calls to getShiftAmountTy+getConstant with
getShiftAmountContant.
Commit: 6590d0fed5180a403c32c991baed56f9d39e045a
https://github.com/llvm/llvm-project/commit/6590d0fed5180a403c32c991baed56f9d39e045a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/ARM/shift-combine.ll
M llvm/test/CodeGen/X86/h-registers-2.ll
Log Message:
-----------
[DAGCombiner][ARM] Teach reduceLoadWidth to handle (and (srl (load), C, ShiftedMask)) (#80342)
If we have a shifted mask, we may be able to reduce the load width
to the width of the non-zero part of the mask and use an offset
to the base address to remove the srl. The offset is given by
C+trailingzeros(ShiftedMask).
Then we add a final shl to restore the trailing zero bits.
I've use the ARM test because that's where the existing (and (srl
(load))) tests were.
The X86 test was modified to keep the H register.
Commit: 34c4a0fa2b9c2181bfdbd3009e7956a50a28dab6
https://github.com/llvm/llvm-project/commit/34c4a0fa2b9c2181bfdbd3009e7956a50a28dab6
Author: ZijunZhaoCCK <88353225+ZijunZhaoCCK at users.noreply.github.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-char.cpp
M clang/lib/Driver/Driver.cpp
M clang/test/CodeGen/fp128_complex.c
M clang/test/Driver/mips-features.c
M clang/test/Frontend/fixed_point_bit_widths.c
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
Log Message:
-----------
[Driver] Report invalid target triple versions for all environment types. (#78655)
Followup for https://github.com/llvm/llvm-project/pull/75373
1. Make this feature not just available for android, but everyone.
2. Correct some target triples.
3. Add opencl to the environment type list.
Commit: b53169dfec89d89b292c550d6f6dec3ed6a61ba5
https://github.com/llvm/llvm-project/commit/b53169dfec89d89b292c550d6f6dec3ed6a61ba5
Author: Sheng <ox59616e at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/AffineMap.h
Log Message:
-----------
[NFC][mlir] Fix Typo.
Commit: 067882cfe970a4ad7fef1432f5fa24fa33150d25
https://github.com/llvm/llvm-project/commit/067882cfe970a4ad7fef1432f5fa24fa33150d25
Author: Anton Korobeynikov <anton at korobeynikov.info>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
A .github/workflows/email-check.yaml
Log Message:
-----------
Add github workflow that checks if a private email address was used to contribute to the repo and warn in this case (#80514)
Following the Discourse discussion, warn in case of a private email address was used in a PR.
Commit: 4926f12ff53fd4e67ac08b7355aeffed15584088
https://github.com/llvm/llvm-project/commit/4926f12ff53fd4e67ac08b7355aeffed15584088
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
[Coverage] ProfileData: Handle MC/DC Bitmap as BitVector. NFC. (#80608)
* `getFunctionBitmap()` stores not `std::vector<uint8_t>` but
`BitVector`.
* `CounterMappingContext` holds `Bitmap` (instead of the ref of bytes)
* `Bitmap` and `BitmapIdx` are used instead of `evaluateBitmap()`.
FIXME: `InstrProfRecord` itself should handle `Bitmap` as `BitVector`.
Commit: 115c0c6513d538ace464887414d1d8f1da7d7208
https://github.com/llvm/llvm-project/commit/115c0c6513d538ace464887414d1d8f1da7d7208
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
A llvm/test/CodeGen/X86/fold-broadcast.ll
Log Message:
-----------
[X86][test] Remove useless pattern for VDPBF16PSZmb and add a test for broadcast folding (#80629)
llvm-issue: https://github.com/llvm/llvm-project/issues/68810
Commit: db060ab0531dd7d8fce9003c0047fb51ec7e4b5d
https://github.com/llvm/llvm-project/commit/db060ab0531dd7d8fce9003c0047fb51ec7e4b5d
Author: Chia <sun1011jacobi at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
A llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
Log Message:
-----------
[RISCV][ISel] Remove redundant vmerge for vwsub(u).wv. (#80523)
Commit: 4b34558f43121df9b863ff2492f74fb2e65a5af1
https://github.com/llvm/llvm-project/commit/4b34558f43121df9b863ff2492f74fb2e65a5af1
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[Github] Fix triggers formatting in code format action
A recent comment modified the job to only run on the main branch, but
the formatting was slightly off, causing the job to not run. This patch
fixes the formatting so the job will run as expected.
Commit: 5afeba051e5c3ad1860cf1642a99e60452d514de
https://github.com/llvm/llvm-project/commit/5afeba051e5c3ad1860cf1642a99e60452d514de
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat_plus.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat_plus.ll
Log Message:
-----------
[RISCV] Custom legalize i32 UADDSAT/USUBSAT for -riscv-experimental-rv64-legal-i32 with Zbb.
This matches the codegen we get from type legalization without
-riscv-experimental-rv64-legal-i32.
Commit: a9670fb0de1cb87fb1556e8cf28d528171f5bd9b
https://github.com/llvm/llvm-project/commit/a9670fb0de1cb87fb1556e8cf28d528171f5bd9b
Author: Kai Luo <lkail at cn.ibm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Fix assertion of InstDisp for local-exec TLS. NFC.
Fixes https://github.com/llvm/llvm-project/issues/80557.
Commit: f035c018a6a581c38680651d4856631d9c6ccb0a
https://github.com/llvm/llvm-project/commit/f035c018a6a581c38680651d4856631d9c6ccb0a
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
InstrProf::getFunctionBitmap: Fix BE hosts (#80608)
Commit: ae5ed2a5d873e1785f06bd74cb583a4e88604317
https://github.com/llvm/llvm-project/commit/ae5ed2a5d873e1785f06bd74cb583a4e88604317
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Sema/SemaRISCVVectorLookup.cpp
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
M clang/test/Sema/rvv-required-features-invalid.c
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[RISCV][clang] Add Zvfbfwma C intrinsics support (#79615)
Commit: 8ed046fc15eae08a9cf7ec02974330d52606c663
https://github.com/llvm/llvm-project/commit/8ed046fc15eae08a9cf7ec02974330d52606c663
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
Log Message:
-----------
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
While working on -riscv-experimental-rv64-legal-i32, I noticed this
missed optimization in our current codegen.
This expands to SADDO/SSUBO+select while still in i32. These will
be type legalized individually.
Commit: 500846d2f542c93e349161a39a1baae0f1f6fad0
https://github.com/llvm/llvm-project/commit/500846d2f542c93e349161a39a1baae0f1f6fad0
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/CodeGenCUDA/amdgpu-code-object-version-linking.cu
M clang/test/CodeGenCUDA/amdgpu-code-object-version.cu
M clang/test/CodeGenCUDA/amdgpu-workgroup-size.cu
A clang/test/Driver/Inputs/rocm/amdgcn/bitcode/oclc_abi_version_600.bc
M clang/test/Driver/hip-code-object-version.hip
M clang/test/Driver/hip-device-libs.hip
M clang/test/Misc/warning-flags.c
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/test/Lower/AMD/code-object-version.f90
M lld/ELF/Arch/AMDGPU.cpp
M lld/test/ELF/amdgpu-tid.s
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/Support/AMDGPUMetadata.h
M llvm/include/llvm/Support/ScopedPrinter.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.s
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.test
R llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[AMDGPU] Introduce Code Object V6 (#76954)
Introduce Code Object V6 in Clang, LLD, Flang and LLVM. This is the same
as V5 except a new "generic version" flag can be present in EFLAGS. This
is related to new generic targets that'll be added in a follow-up patch.
It's also likely V6 will have new changes (possibly new metadata
entries) added later.
Docs change are part of the follow-up patch #76955
Commit: 6e3e8856d442295d8912d8e0c87f6018b4553972
https://github.com/llvm/llvm-project/commit/6e3e8856d442295d8912d8e0c87f6018b4553972
Author: Dani <DanielKristofKiss at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[NFC][Clang] Replace Arch with Triplet. (#80465)
Commit: 0f8680b9d87fa9e8839bd8e39ce605d64148ace6
https://github.com/llvm/llvm-project/commit/0f8680b9d87fa9e8839bd8e39ce605d64148ace6
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.s
Log Message:
-----------
[llvm-readobj] Require AMDGPU target for generic_version.s
Commit: cfa0833ccc7450a322e709583e894e4c96ce682e
https://github.com/llvm/llvm-project/commit/cfa0833ccc7450a322e709583e894e4c96ce682e
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
A llvm/utils/TableGen/GlobalISel/CombinerUtils.cpp
M llvm/utils/TableGen/GlobalISel/CombinerUtils.h
A llvm/utils/TableGen/GlobalISel/PatternParser.cpp
A llvm/utils/TableGen/GlobalISel/PatternParser.h
M llvm/utils/TableGen/GlobalISel/Patterns.cpp
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
[NFC][TableGen][GlobalISel] Move MIR Pattern Parsing out of Combiner Impl (#80257)
This just moves code around so the MIR pattern parsing logic is
separated and reusable.
Commit: a73baf620b8374805b7e927cc79cc157a30e0ac8
https://github.com/llvm/llvm-project/commit/a73baf620b8374805b7e927cc79cc157a30e0ac8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/Analysis/ReachableCode.cpp
A clang/test/SemaCXX/coroutine-unreachable-warning.cpp
Log Message:
-----------
[coroutine] Suppress unreachable-code warning on coroutine statements. (#77454)
This fixes #69219.
Consider an example:
```
CoTask my_coroutine() {
std::abort();
co_return 1; // unreachable code warning.
}
```
Clang emits a CFG-based unreachable warning on the `co_return` statement
(precisely the `1` subexpr). If we remove this statement, the program
semantic is changed (my_coroutine is not a coroutine anymore).
This patch fixes this issue by never considering coroutine statements as
dead statements.
Commit: ab460797f3af80bd262648d4dd306ef751d4e0f6
https://github.com/llvm/llvm-project/commit/ab460797f3af80bd262648d4dd306ef751d4e0f6
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
[TableGen] Trying fix for PatternParser linker error
There is an implicit dependency here and we can't call CodeGenIntrinsics.cpp functions from PatternParser.cpp reliably, so some build bots were failing.
Try to add LLVMTableGenCommon to the list of source files to see if it fixes it, if it doesn't , I'll revert.
Commit: 0a888fade2600dce737bc356a158e44c8f59b616
https://github.com/llvm/llvm-project/commit/0a888fade2600dce737bc356a158e44c8f59b616
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
Log Message:
-----------
[clangd] Handle IndirectFieldDecl in kindForDecl (#80588)
Fixes https://github.com/clangd/clangd/issues/1925
Commit: d11c912f42113764074cf3c8f0aae49f2d288303
https://github.com/llvm/llvm-project/commit/d11c912f42113764074cf3c8f0aae49f2d288303
Author: David Green <david.green at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/uadd_sat.ll
M llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat.ll
M llvm/test/CodeGen/AArch64/usub_sat_plus.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
Log Message:
-----------
[AArch64][GlobalISel] Addition GISel testing for u/s add_sat and sub_sat. NFC
Commit: 722db781d090fc2fd636c299e5f75a0b72c22372
https://github.com/llvm/llvm-project/commit/722db781d090fc2fd636c299e5f75a0b72c22372
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
[TableGen] Exclude LLVMTableGenGlobalISel from "all"
Commit: 991d04d7213bf2747583413ac9b98c7163cf679d
https://github.com/llvm/llvm-project/commit/991d04d7213bf2747583413ac9b98c7163cf679d
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
R llvm/utils/TableGen/GlobalISel/CombinerUtils.cpp
M llvm/utils/TableGen/GlobalISel/CombinerUtils.h
R llvm/utils/TableGen/GlobalISel/PatternParser.cpp
R llvm/utils/TableGen/GlobalISel/PatternParser.h
M llvm/utils/TableGen/GlobalISel/Patterns.cpp
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
Revert "[NFC][TableGen][GlobalISel] Move MIR Pattern Parsing out of Combiner Impl (#80257)"
This reverts commit cfa0833ccc7450a322e709583e894e4c96ce682e.
Commit: d2b0e23247832c472fe9a96a6bb5784addc92de5
https://github.com/llvm/llvm-project/commit/d2b0e23247832c472fe9a96a6bb5784addc92de5
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
Revert "[TableGen] Trying fix for PatternParser linker error"
This reverts commit ab460797f3af80bd262648d4dd306ef751d4e0f6.
Commit: 6deb7cfd74cacda4b460a7f8e1e7a1be012b1b9e
https://github.com/llvm/llvm-project/commit/6deb7cfd74cacda4b460a7f8e1e7a1be012b1b9e
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
Revert "[TableGen] Exclude LLVMTableGenGlobalISel from "all""
This reverts commit 722db781d090fc2fd636c299e5f75a0b72c22372.
Commit: 7d2b6f0b355bc98bbe3aa5bae83316a708da33ee
https://github.com/llvm/llvm-project/commit/7d2b6f0b355bc98bbe3aa5bae83316a708da33ee
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/test/Transforms/IndVarSimplify/pr55925.ll
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[IndVarSimplify] Fix poison-safety when reusing instructions (#80458)
IndVars may replace an instruction with one of its operands, if they
have the same SCEV expression. However, such a replacement may be more
poisonous.
First, check whether the operand being poison implies that the
instruction is also poison, in which case the replacement is always
safe. If this fails, check whether SCEV can determine that reusing the
instruction is safe, using the same check as SCEVExpander.
Fixes https://github.com/llvm/llvm-project/issues/79861.
Commit: 0a45d172d3229074d414e1942d6bafa2b4ae9126
https://github.com/llvm/llvm-project/commit/0a45d172d3229074d414e1942d6bafa2b4ae9126
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/nullify-polymorphic.f90
Log Message:
-----------
[flang] Do not instantiate runtime info globals in functions (#80447)
Runtime globals are compiler generated globals injected in user scopes.
They are never referred to directly in lowering code, we only need th
fur.global for them. Yet lowering was creating hlfir.declare for them in
module procedures. In modern fortran apps, this blows up the generated
IR for nothing (Types with dozens of components, type bound procedures
and parents can create in the order of 10 000 runtime info globals to
describe them, if there is a 100 module procedure, that is that is a few
million operations generated and processed in each pass for nothing).
Commit: d91bb2fcd35e6fc8fe325d5da035295e34b146ca
https://github.com/llvm/llvm-project/commit/d91bb2fcd35e6fc8fe325d5da035295e34b146ca
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
M llvm/test/Assembler/incomplete-ir-declarations.ll
Log Message:
-----------
[AsmParser] Check whether use is callee when determining function type
The code ended up treating a use in a call argument as if it were
a call. Make sure this is actually the callee use.
Commit: 25ab2fc06b6780335c291fa1fc23c2aec01c34a6
https://github.com/llvm/llvm-project/commit/25ab2fc06b6780335c291fa1fc23c2aec01c34a6
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
Log Message:
-----------
[libc][NFC] Make FPRep more testable (#80453)
Commit: f33a0a483550e3441aae4059d6b3d81eab6a398c
https://github.com/llvm/llvm-project/commit/f33a0a483550e3441aae4059d6b3d81eab6a398c
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/NVGPU/tmaload-transform.mlir
Log Message:
-----------
[mlir][nvgpu] Improve `tensormap.descriptor` Type Verifier (#77904)
This PR improves the verifier for the `nvgpu.tensormap.descriptor` type.
The descriptor contains information for TMA, and the compile-time check
ensures its restrictions, such as the last memory dimension being
128-byte. This prevents runtime crashes.
See cuda driver for more explanation:
https://docs.nvidia.com/cuda/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html#group__CUDA__TENSOR__MEMORY_1ga7c7d2aaac9e49294304e755e6f341d7
Commit: 3e230bb6e1a2668e920ee496121e5e40baeb4552
https://github.com/llvm/llvm-project/commit/3e230bb6e1a2668e920ee496121e5e40baeb4552
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
Log Message:
-----------
[CodeGen] Return ArrayRef from TargetRegisterClass::getRegisters. NFCI. (#80411)
This will allow future patches to use indexing and methods like
drop_front on the result.
Commit: 95403b42da0de500f4f86add7a60b0daf8ec98d0
https://github.com/llvm/llvm-project/commit/95403b42da0de500f4f86add7a60b0daf8ec98d0
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.yaml
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.yaml
A clang-tools-extra/test/clang-apply-replacements/format-header.cpp
Log Message:
-----------
Apply format only if --format is specified (#79466)
clang-apply-replacements used to apply format even without --format is
specified. This because, methods like createReplacementsForHeaders only
takes the Spec.Style and would re-order the headers even when it was not
requested. The fix is to set up Spec.Style only if --format is provided.
Also added note to ReleaseNotes.rst
Based on https://github.com/llvm/llvm-project/pull/70801
---------
Co-authored-by: Kugan <34810920+kuganv at users.noreply.github.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: b05ba231bf79c43ac7914920b893511b5e362eb2
https://github.com/llvm/llvm-project/commit/b05ba231bf79c43ac7914920b893511b5e362eb2
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Add `next_toward_inf` fo `FPBits` (#80654)
It is needed to provide correct rounding when building FPRep from
greater precision representations.
Commit: 04c1cce33cc9a3f78898a86567459481f02068bb
https://github.com/llvm/llvm-project/commit/04c1cce33cc9a3f78898a86567459481f02068bb
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
Log Message:
-----------
[docs][RISCV] Remove Zicond from release notes now it was backported
Zicond's graduation to non-experimental was backported to 18.x in #80018,
so remove the release note.
Commit: 7d879bc85129cba6608145d9ae5ccfc9d2fcfa1c
https://github.com/llvm/llvm-project/commit/7d879bc85129cba6608145d9ae5ccfc9d2fcfa1c
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/sign-return-address-tailcall.ll
Log Message:
-----------
[AArch64][PAC] Refine authenticated pointer check methods (#74074)
Align the values of the immediate operand of BRK instruction with those
used by the existing arm64e implementation.
Make AuthCheckMethod::DummyLoad use the requested register
instead of LR.
Commit: 2d69827c5c754f0eca98e497ecf0e52ed54b4fd3
https://github.com/llvm/llvm-project/commit/2d69827c5c754f0eca98e497ecf0e52ed54b4fd3
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
M llvm/test/Transforms/ArgumentPromotion/X86/thiscall.ll
M llvm/test/Transforms/ArgumentPromotion/store-into-inself.ll
M llvm/test/Transforms/Attributor/convergent.ll
M llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
M llvm/test/Transforms/Attributor/dereferenceable-2.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
M llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-infinite-loop-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-start-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-coro-id-async-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-end-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-no-cse-swift-async-context-addr.ll
M llvm/test/Transforms/Coroutines/coro-async-phi.ll
M llvm/test/Transforms/Coroutines/coro-async-unreachable.ll
M llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
M llvm/test/Transforms/CorrelatedValuePropagation/minmaxabs.ll
M llvm/test/Transforms/CorrelatedValuePropagation/range.ll
M llvm/test/Transforms/CorrelatedValuePropagation/select.ll
M llvm/test/Transforms/CorrelatedValuePropagation/sub.ll
M llvm/test/Transforms/DeadArgElim/byref.ll
M llvm/test/Transforms/DeadArgElim/fct_ptr.ll
M llvm/test/Transforms/GVN/condprop-memdep-invalidation.ll
M llvm/test/Transforms/GVN/pr17732.ll
M llvm/test/Transforms/GVNHoist/hoist-recursive-geps.ll
M llvm/test/Transforms/GVNHoist/infinite-loop-direct.ll
M llvm/test/Transforms/GVNHoist/infinite-loop-indirect.ll
M llvm/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll
M llvm/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll
M llvm/test/Transforms/GlobalOpt/GSROA-section.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-gep-constexpr.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-other-constexpr.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-ptrtoint-add-constexpr.ll
M llvm/test/Transforms/GlobalOpt/externally-initialized-aggregate.ll
M llvm/test/Transforms/GlobalOpt/globalsra-partial.ll
M llvm/test/Transforms/GlobalOpt/globalsra.ll
M llvm/test/Transforms/GlobalOpt/invariant.ll
M llvm/test/Transforms/GlobalOpt/malloc-promote-opaque-ptr.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores-initializers.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores-once.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores.ll
M llvm/test/Transforms/IROutliner/nooutline-attribute.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/insert-pos-assert.ll
M llvm/test/Transforms/Inline/call-intrinsic-objectsize.ll
M llvm/test/Transforms/Inline/inline-byval-bonus.ll
M llvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll
M llvm/test/Transforms/Inline/inlined-loop-metadata.ll
M llvm/test/Transforms/InstCombine/alloca.ll
M llvm/test/Transforms/InstCombine/call.ll
M llvm/test/Transforms/InstCombine/fmul.ll
M llvm/test/Transforms/InstCombine/memchr-8.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoopDistribute/symbolic-stride.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-negative.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-version.ll
M llvm/test/Transforms/LoopFlatten/widen-iv.ll
M llvm/test/Transforms/LoopIdiom/lir-heurs-multi-block-loop.ll
M llvm/test/Transforms/LoopInterchange/profitability.ll
M llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
M llvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll
M llvm/test/Transforms/LoopSimplify/do-preheader-dbg.ll
M llvm/test/Transforms/LoopStrengthReduce/Power/memory-intrinsic.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll
M llvm/test/Transforms/LoopUnroll/ARM/mve-nounroll.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/MoveAutoInit/clobber.ll
M llvm/test/Transforms/NewGVN/flags-simplify.ll
M llvm/test/Transforms/NewGVN/no_speculative_loads_with_asan.ll
M llvm/test/Transforms/NewGVN/pr17732.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
M llvm/test/Transforms/PGOProfile/coverage.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-abs.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
M llvm/test/Transforms/SROA/invariant-group.ll
M llvm/test/Transforms/SROA/phi-gep.ll
M llvm/test/Transforms/SROA/scalable-vector-struct.ll
M llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/streaming-compatible-expand-masked-gather-scatter.ll
M llvm/test/Transforms/Util/pr49185.ll
M llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
M llvm/test/Transforms/VectorCombine/X86/load-widening.ll
Log Message:
-----------
[Transforms] Convert tests to opaque pointers (NFC)
Commit: ddd95b15d102331ecb7ce94dcf3a7280e0a133fa
https://github.com/llvm/llvm-project/commit/ddd95b15d102331ecb7ce94dcf3a7280e0a133fa
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
Log Message:
-----------
[RemoveDIs] Handle DPValues in hoistCommonCodeFromSuccessors (#79476)
Hoist DPValues attached to each instruction being considered for hoisting if
they are identical in lock-step. This includes the final instructions which
are considered but not hoisted, because the corresponding dbg.values would
appear before those instruction and thus hoisted if identical.
Identical debug records hoisted:
llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
Non-identical debug records not hoisted:
llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll
Debug records attached to first not-hoisted instructions are hoisted:
llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll
Commit: 9dd40f8c85a30b247dfa47d7ec4353eb69522876
https://github.com/llvm/llvm-project/commit/9dd40f8c85a30b247dfa47d7ec4353eb69522876
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
Log Message:
-----------
[docs][RISCV] Update release notes to include Zalasr and S* extensions from profiles spec
Also reflow the line for Zabha, as we normally line-wrap this file.
Commit: 1aee1e1f4c4b504becc06521546de992a662694b
https://github.com/llvm/llvm-project/commit/1aee1e1f4c4b504becc06521546de992a662694b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/assume-index-positive.ll
M llvm/test/Analysis/BasicAA/index-size.ll
M llvm/test/Analysis/BasicAA/noalias-bugs.ll
M llvm/test/Analysis/BasicAA/vscale.ll
M llvm/test/Analysis/BlockFrequencyInfo/basic.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_pgo.ll
M llvm/test/Analysis/BlockFrequencyInfo/loop_with_invoke.ll
M llvm/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll
M llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
M llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
M llvm/test/Analysis/Dominators/invoke.ll
M llvm/test/Analysis/FunctionPropertiesAnalysis/matmul.ll
M llvm/test/Analysis/IVUsers/deep_recursion_in_scev.ll
M llvm/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll
M llvm/test/Analysis/LazyValueAnalysis/invalidation.ll
M llvm/test/Analysis/LoopAccessAnalysis/forked-pointers.ll
M llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/LoopnestFixedSize.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/loads-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matvecmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/single-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
M llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-complex.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-simple.ll
M llvm/test/Analysis/LoopNestAnalysis/duplicate-successors.ll
M llvm/test/Analysis/LoopNestAnalysis/imperfectnest.ll
M llvm/test/Analysis/LoopNestAnalysis/infinite.ll
M llvm/test/Analysis/LoopNestAnalysis/perfectnest.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/atomics.ll
Log Message:
-----------
[Analysis] Convert tests to opaque pointers (NFC)
Commit: 0940be158104e055ab255ccb5c1af9c7ccc7358f
https://github.com/llvm/llvm-project/commit/0940be158104e055ab255ccb5c1af9c7ccc7358f
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/docs/Bufferization.md
M mlir/include/mlir/Dialect/Bufferization/Pipelines/Passes.h
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-callop-interface.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-function-boundaries.mlir
Log Message:
-----------
[mlir][bufferization] Never pass ownership to functions (#80655)
Even when `private-function-dynamic-ownership` is set, ownership should
never be passed to the callee. This can lead to double deallocs (#77096)
or use-after-free in the caller because ownership is currently passed
regardless of whether there are any further uses of the buffer in the
caller or not.
Note: This is consistent with the fact that ownership is never passed to
nested regions.
This commit fixes #77096.
Commit: 13e52b32790e3c3d2fb16139f082a588b4e0f4db
https://github.com/llvm/llvm-project/commit/13e52b32790e3c3d2fb16139f082a588b4e0f4db
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
Log Message:
-----------
[docs][RISCV] Add missed release note for Zimop codegen support
Commit: 84ea236af9f36d409d2c45c66f8a8b6eb027935d
https://github.com/llvm/llvm-project/commit/84ea236af9f36d409d2c45c66f8a8b6eb027935d
Author: David Green <david.green at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/AliasSet/memloc-vscale.ll
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] Handle scalable type sizes with constant offsets (#80445)
This is a separate, but related issue to #69152 that was attempting to improve
AA with scalable dependency distances. This patch attempts to improve when
there are scalable accesses with a constant offset between them. We happen to
get a report of such a thing recently, where so long as the vscale_range is
known, the maximum size of the access can be assessed and better aliasing
results can be returned.
The Upper range of the vscale_range, along with known part of the typesize are
used to prove that Off >= CR.upper * LSize. It does not try to produce
PartialAlias results at the moment from the lower vscale_range. It also enables
the added benefit of allowing better alias analysis when the RHS of the two
values is scalable, but the LHS is normal and can be treated like any other
aliasing query.
Commit: 1ee315ae7964c8433b772e0b5d667834994ba753
https://github.com/llvm/llvm-project/commit/1ee315ae7964c8433b772e0b5d667834994ba753
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global-pic.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-xclass-copies.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
M llvm/test/CodeGen/AArch64/PBQP-csr.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
M llvm/test/CodeGen/AArch64/add-i256.ll
M llvm/test/CodeGen/AArch64/addrsig-macho.ll
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-bad-outline.mir
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
M llvm/test/CodeGen/AArch64/arm64-ldp.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
M llvm/test/CodeGen/AArch64/compute-call-frame-size-unreachable-pass.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
M llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/divrem.ll
M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/fmov-imm-licm.ll
M llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/irg-nomem.mir
M llvm/test/CodeGen/AArch64/ldradr.ll
M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
M llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
M llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
M llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
M llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
M llvm/test/CodeGen/AArch64/merge-store.ll
M llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
M llvm/test/CodeGen/AArch64/sched-movprfx.ll
M llvm/test/CodeGen/AArch64/settag-merge.mir
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
M llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
M llvm/test/CodeGen/AArch64/speculation-hardening.mir
M llvm/test/CodeGen/AArch64/spillfill-sve.ll
M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
M llvm/test/CodeGen/AArch64/stack-guard-sve.ll
M llvm/test/CodeGen/AArch64/stack-probing-64k.ll
M llvm/test/CodeGen/AArch64/stack-tagging-cfi.ll
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
M llvm/test/CodeGen/AArch64/sub-of-bias.ll
M llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
M llvm/test/CodeGen/AArch64/sve-alloca.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
M llvm/test/CodeGen/AArch64/sve-fp.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
M llvm/test/CodeGen/AArch64/sve-gep.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-setcc.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-varargs-callee-broken.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-ld1-single.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-loads.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll
M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
M llvm/test/CodeGen/AArch64/taildup-addrtaken.mir
M llvm/test/CodeGen/AArch64/tailmerging_in_mbp.ll
M llvm/test/CodeGen/AArch64/tiny-model-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-static.ll
M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
M llvm/test/CodeGen/AArch64/v3f-to-int.ll
M llvm/test/CodeGen/AArch64/win-catchpad-nested-cxx.ll
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
M llvm/test/CodeGen/AArch64/zero-reg.ll
Log Message:
-----------
[AArch64] Convert tests to opaque pointers (NFC)
Commit: 1d3d8936baf9f15e23603bbb1cfe0a5610d458d3
https://github.com/llvm/llvm-project/commit/1d3d8936baf9f15e23603bbb1cfe0a5610d458d3
Author: Yi Wu <yi.wu2 at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/atan2d.f90
A flang/test/Lower/Intrinsics/atan2pi.f90
M flang/test/Lower/Intrinsics/atand.f90
A flang/test/Lower/Intrinsics/atanpi.f90
Log Message:
-----------
[flang] Fix for atand(Y,X), and implment atan2d(Y,X), atanpi(X), atanpi(Y,X), atan2pi(Y,X) (#79002)
Fix: https://github.com/llvm/llvm-project/issues/78568
---------
Co-authored-by: jeanPerier <jean.perier.polytechnique at gmail.com>
Commit: 00a4e248dc65d3a60fd900b342d4ba410bf70af0
https://github.com/llvm/llvm-project/commit/00a4e248dc65d3a60fd900b342d4ba410bf70af0
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
Log Message:
-----------
[AMDGPU] Convert tests to opaque pointers (NFC)
Commit: 6e83c0a1cbfdb0c0f13c282312c47c7945970f55
https://github.com/llvm/llvm-project/commit/6e83c0a1cbfdb0c0f13c282312c47c7945970f55
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/AMX/amx-combine.ll
M llvm/test/CodeGen/X86/AMX/amx-tile-complex-internals.ll
M llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
M llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
M llvm/test/CodeGen/X86/PR37310.mir
M llvm/test/CodeGen/X86/atomic-dagsched.ll
M llvm/test/CodeGen/X86/atomic-nocx16.ll
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir
M llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir
M llvm/test/CodeGen/X86/avoid-sfb-offset.mir
M llvm/test/CodeGen/X86/avx512f-256-set0.mir
M llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
M llvm/test/CodeGen/X86/basic-block-labels-mir-parse.mir
M llvm/test/CodeGen/X86/basic-block-sections-module1.ll
M llvm/test/CodeGen/X86/basic-block-sections-module2.ll
M llvm/test/CodeGen/X86/block-placement.ll
M llvm/test/CodeGen/X86/callbr-asm-sink.ll
M llvm/test/CodeGen/X86/cmp.ll
M llvm/test/CodeGen/X86/code-model-kernel.ll
M llvm/test/CodeGen/X86/code_placement.ll
M llvm/test/CodeGen/X86/complex-asm.ll
M llvm/test/CodeGen/X86/crash.ll
M llvm/test/CodeGen/X86/fastisel-memset-flush.ll
M llvm/test/CodeGen/X86/function-alias.ll
M llvm/test/CodeGen/X86/funnel-shift.ll
M llvm/test/CodeGen/X86/large-constants-x32.ll
M llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/memcpy-scoped-aa.ll
M llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr44140.ll
M llvm/test/CodeGen/X86/pr48064.mir
M llvm/test/CodeGen/X86/pre-coalesce-2.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/CodeGen/X86/select-neg.ll
M llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/stack-protector-dbginfo.ll
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
M llvm/test/CodeGen/X86/tailcc-dwarf.ll
M llvm/test/CodeGen/X86/threadlocal_address.ll
M llvm/test/CodeGen/X86/win64-byval.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppCondiTemps.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll
Log Message:
-----------
[X86] Convert tests to opaque pointers (NFC)
Commit: 60732c0fae56829c5475091de678ad46f0ce6287
https://github.com/llvm/llvm-project/commit/60732c0fae56829c5475091de678ad46f0ce6287
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/EvaluationResult.cpp
Log Message:
-----------
[clang][Interp][NFC] Remove superfluous return statement
Commit: 69ffa7be3bda5547d7a41233f86b88539616e386
https://github.com/llvm/llvm-project/commit/69ffa7be3bda5547d7a41233f86b88539616e386
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sadd_sat_vec.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/sse41.ll
M llvm/test/CodeGen/X86/ssub_sat_vec.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_cmp_sint-128.ll
M llvm/test/CodeGen/X86/vec_compare-sse4.ll
M llvm/test/CodeGen/X86/vec_minmax_sint.ll
M llvm/test/CodeGen/X86/vec_saddo.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_ssubo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect-post-combine.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - load+zero vector constants that can be stored in a truncated form (#80428)
Further develops the vsextload support added in #79815 / b5d35feacb7246573c6a4ab2bddc4919a4228ed5 - reduces the size of the vector constant by storing it in the constant pool in a truncated form, and zero-extend it as part of the load.
Commit: bc82d1a6b7f8a795e923b10e8ef0fdc34628a48e
https://github.com/llvm/llvm-project/commit/bc82d1a6b7f8a795e923b10e8ef0fdc34628a48e
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-teams.mlir
Log Message:
-----------
[OpenMPIRBuilder][MLIR] Pass target-cpu and target-features to outlined functions (#80283)
This patch adds support for forwarding the target-cpu and
target-features attributes to functions outlined in the OpenMPIRBuilder.
This, in turn, results in the addition of these attributes for functions
created during the translation of the `omp.parallel`, `omp.task` and
`omp.teams` operations, and for the `omp.wsloop` operation when doing
codegen for an OpenMP target device.
Commit: c391f285afdfd800a251b4ef6d0bbadbbe9069ff
https://github.com/llvm/llvm-project/commit/c391f285afdfd800a251b4ef6d0bbadbbe9069ff
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A clang/test/AST/Interp/atomic.cpp
Log Message:
-----------
[clang][Interp][NFC] Add simple test case for atomic types
Commit: 6ba9d2988ba471d3a1620da64d5a08f2edfe91ed
https://github.com/llvm/llvm-project/commit/6ba9d2988ba471d3a1620da64d5a08f2edfe91ed
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
A libc/src/math/ceilf128.h
A libc/src/math/floorf128.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/ceilf128.cpp
A libc/src/math/generic/floorf128.cpp
A libc/src/math/generic/roundf128.cpp
A libc/src/math/generic/truncf128.cpp
A libc/src/math/roundf128.h
A libc/src/math/truncf128.h
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/ceilf128_test.cpp
A libc/test/src/math/smoke/floorf128_test.cpp
A libc/test/src/math/smoke/roundf128_test.cpp
A libc/test/src/math/smoke/truncf128_test.cpp
Log Message:
-----------
[libc][math] Add float128 rounding functions (ceilf128, floorf128, roundf128, truncf128). (#80634)
Commit: d4ef4b818929732bcb68a536ef2c91891c0ad179
https://github.com/llvm/llvm-project/commit/d4ef4b818929732bcb68a536ef2c91891c0ad179
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/float128.h
M libc/spec/spec.td
M libc/spec/stdc.td
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/macros/properties/CMakeLists.txt
M libc/src/__support/macros/properties/float.h
Log Message:
-----------
[libc] Fix generated float128 header for aarch64 target. (#78017)
Commit: 7bdc80f35c325d148b1ddbdfce7dea8c6ba7af84
https://github.com/llvm/llvm-project/commit/7bdc80f35c325d148b1ddbdfce7dea8c6ba7af84
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
M llvm/test/CodeGen/AVR/ctors.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/elpm.ll
M llvm/test/CodeGen/AVR/features/avr-tiny.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
M llvm/test/CodeGen/AVR/inline-asm/loadstore.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lpmx.ll
M llvm/test/CodeGen/AVR/pr43443-ctor-alias.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-trait-object.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/struct.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
Log Message:
-----------
[AVR] Convert tests to opaque pointers (NFC)
Commit: b31fffbc7f1e0491bf599e82b7195e320d26e140
https://github.com/llvm/llvm-project/commit/b31fffbc7f1e0491bf599e82b7195e320d26e140
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
M llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
M llvm/test/CodeGen/ARM/Windows/wineh-basic.ll
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/aliases.ll
M llvm/test/CodeGen/ARM/code-placement.ll
M llvm/test/CodeGen/ARM/constant-island-movwt.mir
M llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
M llvm/test/CodeGen/ARM/debug-info-blocks.ll
M llvm/test/CodeGen/ARM/debug-info-d16-reg.ll
M llvm/test/CodeGen/ARM/debug-info-s16-reg.ll
M llvm/test/CodeGen/ARM/dwarf-eh.ll
M llvm/test/CodeGen/ARM/ldrcppic.ll
M llvm/test/CodeGen/ARM/misched-copy-arm.ll
M llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
M llvm/test/CodeGen/ARM/readonly-aliases.ll
M llvm/test/CodeGen/ARM/tail-dup-kill-flags.ll
M llvm/test/CodeGen/Thumb/PR36658.mir
M llvm/test/CodeGen/Thumb/branch-to-return.ll
M llvm/test/CodeGen/Thumb/tbb-reuse.mir
M llvm/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout-unknown-lanes.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-revert-placement.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
M llvm/test/CodeGen/Thumb2/mve-phireg.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
M llvm/test/CodeGen/Thumb2/mve-qrintrsplat.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-add-combine.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
M llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
M llvm/test/CodeGen/Thumb2/mve-vmovlloop.ll
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
M llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir
Log Message:
-----------
[ARM] Convert tests to opaque pointers (NFC)
Commit: 89ec940b4a8020e1399e019d845be1a2d2217f69
https://github.com/llvm/llvm-project/commit/89ec940b4a8020e1399e019d845be1a2d2217f69
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
A llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
Log Message:
-----------
[AMDGPU] Insert spill codes for the SGPRs used for EXEC copy (#79428)
The SGPR registers used for preserving EXEC mask while lowering the
whole-wave register spills and copies should be preserved at the prolog
and epilog if they are in the CSR range. It isn't happening when there
is only wwm-copy lowered and there are no wwm-spills. This patch
addresses that problem.
Commit: 06f711a906be85e141bcce9a88ab304dc81e74ef
https://github.com/llvm/llvm-project/commit/06f711a906be85e141bcce9a88ab304dc81e74ef
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
Log Message:
-----------
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.
TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.
patch 3 from: https://github.com/llvm/llvm-project/pull/73337
Commit: ff9af4c43ad71eeba2cabe99609cfaa0fd54c1d0
https://github.com/llvm/llvm-project/commit/ff9af4c43ad71eeba2cabe99609cfaa0fd54c1d0
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/BPF/BTF/builtin-btf-type-id.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-2.ll
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M llvm/test/CodeGen/BPF/reloc.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/Generic/DbgValueAggregate.ll
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M llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
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M llvm/test/CodeGen/Hexagon/autohvx/hfsplat.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
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M llvm/test/CodeGen/Hexagon/swp-new-phi.ll
M llvm/test/CodeGen/Hexagon/v5_insns.ll
M llvm/test/CodeGen/Hexagon/v60Vasr.ll
M llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
M llvm/test/CodeGen/Hexagon/vect-regpairs.ll
M llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll
M llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
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M llvm/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
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M llvm/test/CodeGen/Lanai/peephole-compare.mir
M llvm/test/CodeGen/Lanai/set_and_hi.ll
M llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
M llvm/test/CodeGen/Lanai/subword.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
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M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
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M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
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M llvm/test/CodeGen/MSP430/2009-05-17-Shift.ll
M llvm/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
M llvm/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
M llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
M llvm/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
M llvm/test/CodeGen/MSP430/2009-12-21-FrameAddr.ll
M llvm/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
M llvm/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
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M llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
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M llvm/test/CodeGen/MSP430/Inst16mi.ll
M llvm/test/CodeGen/MSP430/Inst16mm.ll
M llvm/test/CodeGen/MSP430/Inst16mr.ll
M llvm/test/CodeGen/MSP430/Inst16rm.ll
M llvm/test/CodeGen/MSP430/Inst8mi.ll
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M llvm/test/CodeGen/MSP430/InstII.ll
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M llvm/test/CodeGen/MSP430/byval.ll
M llvm/test/CodeGen/MSP430/callee-saved.ll
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M llvm/test/CodeGen/MSP430/hwmult32.ll
M llvm/test/CodeGen/MSP430/hwmultf5.ll
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M llvm/test/CodeGen/MSP430/inlineasm-output-template.ll
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M llvm/test/CodeGen/MSP430/jumptable.ll
M llvm/test/CodeGen/MSP430/libcalls.ll
M llvm/test/CodeGen/MSP430/memset.ll
M llvm/test/CodeGen/MSP430/misched-msp430.ll
M llvm/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
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M llvm/test/CodeGen/MSP430/promote-i8-mul.ll
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M llvm/test/CodeGen/MSP430/stacksave_restore.ll
M llvm/test/CodeGen/MSP430/struct-return.ll
M llvm/test/CodeGen/MSP430/struct_layout.ll
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M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
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M llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll
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M llvm/test/CodeGen/PowerPC/preincprep-nontrans-crash.ll
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M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
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M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
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M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/rvv/zve32-types.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/xtheadfmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
M llvm/test/CodeGen/SPARC/2009-08-28-PIC.ll
M llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
M llvm/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
M llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
M llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
M llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll
M llvm/test/CodeGen/SPARC/2011-12-03-TailDuplication.ll
M llvm/test/CodeGen/SPARC/2012-05-01-LowerArguments.ll
M llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll
M llvm/test/CodeGen/SPARC/32abi.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SPARC/64atomics.ll
M llvm/test/CodeGen/SPARC/64bit.ll
M llvm/test/CodeGen/SPARC/64cond.ll
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll
M llvm/test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll
M llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll
M llvm/test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll
M llvm/test/CodeGen/SPARC/atomics.ll
M llvm/test/CodeGen/SPARC/basictest.ll
M llvm/test/CodeGen/SPARC/bigreturn.ll
M llvm/test/CodeGen/SPARC/blockaddr.ll
M llvm/test/CodeGen/SPARC/cast-sret-func.ll
M llvm/test/CodeGen/SPARC/constructor.ll
M llvm/test/CodeGen/SPARC/exception.ll
M llvm/test/CodeGen/SPARC/fail-alloca-align.ll
M llvm/test/CodeGen/SPARC/float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
M llvm/test/CodeGen/SPARC/func-addr.ll
M llvm/test/CodeGen/SPARC/globals.ll
M llvm/test/CodeGen/SPARC/inlineasm-output-template.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
M llvm/test/CodeGen/SPARC/leafproc.ll
M llvm/test/CodeGen/SPARC/missing-sret.ll
M llvm/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
M llvm/test/CodeGen/SPARC/obj-relocs.ll
M llvm/test/CodeGen/SPARC/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/SPARC/pic.ll
M llvm/test/CodeGen/SPARC/private.ll
M llvm/test/CodeGen/SPARC/reserved-regs.ll
M llvm/test/CodeGen/SPARC/select-mask.ll
M llvm/test/CodeGen/SPARC/setjmp.ll
M llvm/test/CodeGen/SPARC/spillsize.ll
M llvm/test/CodeGen/SPARC/sret-secondary.ll
M llvm/test/CodeGen/SPARC/stack-align.ll
M llvm/test/CodeGen/SPARC/stack-protector.ll
M llvm/test/CodeGen/SPARC/tailcall.ll
M llvm/test/CodeGen/SPARC/thread-pointer.ll
M llvm/test/CodeGen/SPARC/tls.ll
M llvm/test/CodeGen/SPARC/varargs-v8.ll
M llvm/test/CodeGen/SPARC/varargs.ll
M llvm/test/CodeGen/SPARC/vector-extract-elt.ll
M llvm/test/CodeGen/SPARC/zerostructcall.ll
M llvm/test/CodeGen/SystemZ/Large/branch-01.ll
M llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
M llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
M llvm/test/CodeGen/SystemZ/cond-move-04.mir
M llvm/test/CodeGen/SystemZ/cond-move-05.mir
M llvm/test/CodeGen/SystemZ/cond-move-08.mir
M llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir
M llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
M llvm/test/CodeGen/SystemZ/dag-combine-02.ll
M llvm/test/CodeGen/SystemZ/debuginstr-00.mir
M llvm/test/CodeGen/SystemZ/debuginstr-01.mir
M llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir
M llvm/test/CodeGen/SystemZ/foldmemop-imm-02.mir
M llvm/test/CodeGen/SystemZ/foldmemop-msc.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-binops.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-cc.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-cmp.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-fusedfp.mir
M llvm/test/CodeGen/SystemZ/fp-conv-17.mir
M llvm/test/CodeGen/SystemZ/frame-26.mir
M llvm/test/CodeGen/SystemZ/int-cmp-56.mir
M llvm/test/CodeGen/SystemZ/isel-debug.ll
M llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir
M llvm/test/CodeGen/SystemZ/loop-04.ll
M llvm/test/CodeGen/SystemZ/multiselect-02.mir
M llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir
M llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir
M llvm/test/CodeGen/SystemZ/selectcc-04.ll
M llvm/test/CodeGen/SystemZ/subregliveness-06.mir
M llvm/test/CodeGen/SystemZ/zos-landingpad.ll
M llvm/test/CodeGen/VE/Scalar/pic_access_data.ll
M llvm/test/CodeGen/VE/Scalar/pic_indirect_func_call.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
M llvm/test/CodeGen/WebAssembly/global.ll
M llvm/test/CodeGen/WebAssembly/userstack.ll
M llvm/test/CodeGen/WinCFGuard/cfguard-cast.ll
M llvm/test/CodeGen/WinCFGuard/cfguard-giats.ll
M llvm/test/CodeGen/WinCFGuard/cfguard.ll
M llvm/test/CodeGen/XCore/threads.ll
Log Message:
-----------
[CodeGen] Convert tests to opaque pointers (NFC)
Commit: 4e958abf2f44d08129eafd5b6a4ee2bd3584ed22
https://github.com/llvm/llvm-project/commit/4e958abf2f44d08129eafd5b6a4ee2bd3584ed22
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
Log Message:
-----------
[AMDGPU][PromoteAlloca] Support memsets to ptr allocas (#80678)
Fixes #80366
Commit: a5d206df792b61a0b6c5ac44343a97696fc6071d
https://github.com/llvm/llvm-project/commit/a5d206df792b61a0b6c5ac44343a97696fc6071d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/div_i128.ll
A llvm/test/CodeGen/AMDGPU/div_v2i128.ll
Log Message:
-----------
AMDGPU: Set max supported div/rem size to 64 (#80669)
This enables IR expansion for i128 divisions. The vector case is still
broken because ExpandLargeDivRem doesn't try to handle them.
Fixes: SWDEV-426193
Commit: a826a0c234c38eab194119bebcab91aabc2e3759
https://github.com/llvm/llvm-project/commit/a826a0c234c38eab194119bebcab91aabc2e3759
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
A llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Log Message:
-----------
[RISCV] Add tests for reduce.fmaximum/fminimum. NFC (#80553)
This is to add test coverage for crash report in #80340
Commit: 66397435ed83c2247f49d302246ba5a87f4dd85f
https://github.com/llvm/llvm-project/commit/66397435ed83c2247f49d302246ba5a87f4dd85f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Add common getSrcIdx helper to determine source index after AVX512 masked predicates. NFC.
Commit: bc6370abd3f1e6b02100927095a2797472d6ff70
https://github.com/llvm/llvm-project/commit/bc6370abd3f1e6b02100927095a2797472d6ff70
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] addConstantComments - split VPERMILPS/VPERMILPD handling to reduce repeated switch cases etc. NFC.
Commit: 992d8527585817af685bba0d82ed4e808bc613bb
https://github.com/llvm/llvm-project/commit/992d8527585817af685bba0d82ed4e808bc613bb
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Flang.cpp
A flang/test/Driver/aarch64-outline-atomics.f90
M flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
A flang/test/Integration/aarch64-outline-atomics.f90
Log Message:
-----------
[flang]Add support for -moutline-atomics and -mno-outline-atomics (#78755)
This adds the support to add the target-feature to outline atomic operations (calling the
runtime library instead).
Commit: 825658856d94776889399a07a3939610ee1aa299
https://github.com/llvm/llvm-project/commit/825658856d94776889399a07a3939610ee1aa299
Author: Hui <hui.xie1990 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/semaphore
A libcxx/test/std/thread/thread.semaphore/lost_wakeup.pass.cpp
Log Message:
-----------
[libc++] fix `counting_semaphore` lost wakeups (#79265)
Fixes #77659
Fixes #46357
Picked up from https://reviews.llvm.org/D114119
Commit: a40d68b6de30a7fda44a2905e83df3d80fca2abf
https://github.com/llvm/llvm-project/commit/a40d68b6de30a7fda44a2905e83df3d80fca2abf
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/docs/index.rst
A libc/docs/libc_search.rst
R libc/docs/search.rst
M libc/docs/stdbit.rst
Log Message:
-----------
[libc] tiny fix for doc (#80512)
Commit: 8e00fc33ebabccf60388288c07201706ca3efd71
https://github.com/llvm/llvm-project/commit/8e00fc33ebabccf60388288c07201706ca3efd71
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
Log Message:
-----------
[mlir][ArmSME][nfc] Fix docs for 2-way ops
The "Refer to" and table shouldn't be in the example code sequence.
Commit: 5f5b3bb22b2e4ffcd14a8fc8a5edc14bc098a47e
https://github.com/llvm/llvm-project/commit/5f5b3bb22b2e4ffcd14a8fc8a5edc14bc098a47e
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/test/Dialect/ArmSME/outer-product-fusion.mlir
Log Message:
-----------
[mlir][ArmSME] Add rewrites to swap extract of extend (#80407)
In mixed matmul lowering (e.g., i8 to i32) we're seeing the following
sequence:
%0 = arith.extsi %src : vector<4x[8]xi8> to vector<4x[8]xi32>
%1 = vector.extract %0[0] : vector<[8]xi32> from vector<4x[8]xi32>
%lhs = vector.scalable.extract %1[0] : vector<[4]xi32> from
vector<[8]xi32>
... (same for rhs)
%2 = vector.outerproduct %lhs, %rhs, %acc vector<[4]xi32>,
vector<[4]xi32>
// x4 chained by accumulator
This chain of 4 outer products can be fused into a single 4-way widening
variant but the pass doesn't match on the IR, as it expects the source
of the inputs to be an extend and it can't look through the extracts.
This patch fixes this with two rewrites that swaps extract(extend) into
extend(extract).
Related to #78975, #79288.
Commit: abea3b27991dd73cad251f623a2a8f25a3e786ff
https://github.com/llvm/llvm-project/commit/abea3b27991dd73cad251f623a2a8f25a3e786ff
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/RDFGraph.cpp
Log Message:
-----------
[RDF] Skip over NoRegister. NFCI. (#80672)
This just avoids useless work of adding NoRegister to BaseSet, for
consistency with other places that iterate over all physical registers.
Commit: daea0820829bf5bbca9ab50fc118012a2508fab3
https://github.com/llvm/llvm-project/commit/daea0820829bf5bbca9ab50fc118012a2508fab3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__support/xlocale/__posix_l_fallback.h
Log Message:
-----------
[libc++] Add missing include of <string.h> in POSIX fallbacks for locale
Commit: 1af05363d6353d7edd0d00e37ae0eb70f54b4b64
https://github.com/llvm/llvm-project/commit/1af05363d6353d7edd0d00e37ae0eb70f54b4b64
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] getShuffleComment - use MI description to determine AVX512 masked predicates instead of src index offsets.
Commit: d15c454bedc05775b5080e1d2130b0554d5e5a81
https://github.com/llvm/llvm-project/commit/d15c454bedc05775b5080e1d2130b0554d5e5a81
Author: Kevin P. Neal <kevin.neal at sas.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
Log Message:
-----------
[FPEnv][AMDGPU] Correct strictfp tests.
Correct AMDGPU strictfp tests to follow the rules documented in the
LangRef:
https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics
These tests needed the strictfp attribute added to function calls and
some declarations.
Some of the tests now pass with D146845, others get farther along and
fail with D146845. The tests revealed that further work is required
in mostly AMDGPU atomics to get the tests passing.
Since I was here anyway I removed the strictfp attribute from some
constrained intrinsic declarations. They have this attribute by default.
Test changes verified with D146845.
Commit: 3bf881635c9ca7398ba6a451e30a2156b22d59b5
https://github.com/llvm/llvm-project/commit/3bf881635c9ca7398ba6a451e30a2156b22d59b5
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Frontend/Offloading/Utility.cpp
Log Message:
-----------
[Offload] Fix entry global names on NVPTX target
Summary:
The PTX language rejects globals with `.` in the name. We need to change
the global name if we are targeting NVPTX to prevent the toolchain from
complaining.
Commit: 5249379d742148728f654665e113084c6b93cdf2
https://github.com/llvm/llvm-project/commit/5249379d742148728f654665e113084c6b93cdf2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave64.cl
Log Message:
-----------
[AMDGPU] Allow w64 ballot to be used on w32 targets (#80183)
Summary:
Currently we cannot compile `__builtin_amdgcn_ballot_w64` on non-wave64
targets even though it is valid. This is relevant for making library
code that can handle both without needing to check the wavefront size.
This patch relaxes the semantic check for w64 so it can be used
normally.
Commit: e4f1ef85fd60c08c9ece4982fccf76e8101011b8
https://github.com/llvm/llvm-project/commit/e4f1ef85fd60c08c9ece4982fccf76e8101011b8
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/PrimType.h
A clang/test/AST/Interp/atomic.c
M clang/test/Sema/atomic-expr.c
Log Message:
-----------
[clang][Interp] Reject bitcasts to atomic types
The current interpreter does this, so follow suit to match its
diagnostics.
Commit: de46dc97b11b06c7efc225cfa08cf3cb68a8a75e
https://github.com/llvm/llvm-project/commit/de46dc97b11b06c7efc225cfa08cf3cb68a8a75e
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/spirv-tests.yml
Log Message:
-----------
[SPIR-V] Include SPIRV-Tools tests in CI (#80479)
Commit: e524ada6cbc6912156a713ffa179cb92e5362ebb
https://github.com/llvm/llvm-project/commit/e524ada6cbc6912156a713ffa179cb92e5362ebb
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp] Support zero init for complex types (#79728)
Initialize both elements to 0.
Commit: d1722868d34a69df8466b72098176f54a7af8823
https://github.com/llvm/llvm-project/commit/d1722868d34a69df8466b72098176f54a7af8823
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave64.cl
Log Message:
-----------
[Clang] Make AMDGPU OpenCL tests require AMD registered target
Summary:
These tests likely always failed but was hidden by the expected return
value. Simply make them require AMDGPU as a registered target so they
don't fail on other machines.
Commit: ae92f6e8aeb97e39b95a40fde8a176f6aff94063
https://github.com/llvm/llvm-project/commit/ae92f6e8aeb97e39b95a40fde8a176f6aff94063
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/docs/use/python-reference.rst
Log Message:
-----------
[lldb][Docs] Remove unnecessary colon in title
Commit: 2614672cc12258d2b07db2657e475ad70e01d5ba
https://github.com/llvm/llvm-project/commit/2614672cc12258d2b07db2657e475ad70e01d5ba
Author: elhewaty <mohamedatef1698 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and.ll
Log Message:
-----------
[InstCombine] Fold ((cst << x) & 1) --> x == 0 when cst is odd (#79772)
Fold ((cst << x) & 1) to zext(x == 0) when cst is odd.
Fixes: https://github.com/llvm/llvm-project/issues/73384
Alive2: https://alive2.llvm.org/ce/z/5RbaK6
Commit: 41ea02261224446dadb1b1561d70137699255518
https://github.com/llvm/llvm-project/commit/41ea02261224446dadb1b1561d70137699255518
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Type.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
Log Message:
-----------
[Clang] Fix crash when recovering from an invalid pack indexing type. (#80652)
If the pattern of a pack indexing type did not contain a pack, we would
still construct a pack indexing type (to improve error messages) but we
would fail to make the type as dependent, leading to infinite recursion
when trying to extract a canonical type.
Commit: 4881cbd407e73f940a8e9ede501c2eee190ec9dd
https://github.com/llvm/llvm-project/commit/4881cbd407e73f940a8e9ede501c2eee190ec9dd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/cxx98.cpp
M clang/test/SemaCXX/pr72025.cpp
Log Message:
-----------
[clang][Interp] Fix MemberExpr initializing an existing value (#79973)
This is similar to c1ad363e6eba308fa94c47374ee98b3c79693a35, but with
the additional twist that initializing an existing value from a
`MemberExpr` was not working correctly.
Commit: 8cb2de7faecdd4e053dfc8468b2be84e2d8afb4e
https://github.com/llvm/llvm-project/commit/8cb2de7faecdd4e053dfc8468b2be84e2d8afb4e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
Log Message:
-----------
[VPlan] Implement type inference for ICmp.
This fixes a crash in the attached test case due to missing type
inference for ICmp VPInstructions.
Commit: 0881d0f009427427509e5592b875d3fd702c595a
https://github.com/llvm/llvm-project/commit/0881d0f009427427509e5592b875d3fd702c595a
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/startup/gpu/CMakeLists.txt
M libc/startup/gpu/amdgpu/CMakeLists.txt
M libc/startup/gpu/nvptx/CMakeLists.txt
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/src/CMakeLists.txt
Log Message:
-----------
[libc] Refactor _build_gpu_objects cmake function. (#80631)
Commit: 702664e7870c27f197dfb744a4db54aa259ce452
https://github.com/llvm/llvm-project/commit/702664e7870c27f197dfb744a4db54aa259ce452
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-8.fir
Log Message:
-----------
[flang] Improve alias analysis to be precise for box and box.base_addr (#80335)
After PR#68727 the source for both the fir.box_addr and a box became the
same. Thus the detection that only one of the sources was direct and the
special logic around it was being skipped. As a result, the test
included would show a "MayAlias" result instead of a "NoAlias" result.
Commit: 9a87c5d440ec16a1116e060829df10bc2a6965ce
https://github.com/llvm/llvm-project/commit/9a87c5d440ec16a1116e060829df10bc2a6965ce
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Target/Cpp/func.mlir
Log Message:
-----------
[mlir][EmitC] Add support for external functions (#80547)
This adds a conversion from an externaly defined `func.func`, a
`func.func` without function body, to an `emitc.func` with an `extern`
specifier.
Commit: 0ac44385603ca67ceb969eb271d8c2075a8c14b4
https://github.com/llvm/llvm-project/commit/0ac44385603ca67ceb969eb271d8c2075a8c14b4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M openmp/libomptarget/include/Shared/PluginAPI.h
M openmp/libomptarget/include/Shared/PluginAPI.inc
M openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/libomptarget/src/omptarget.cpp
Log Message:
-----------
[Libomptarget] Remove unused 'SupportsEmptyImages' API function (#80316)
Summary:
This function is always false in the current implementation and is not
even considered required. Just remove it and if someone needs it in the
future they can add it back in. This is done to simplify the interface
prior to other changes
Commit: ae354c5a45d319b3117c2822b8f6988461f3cb33
https://github.com/llvm/llvm-project/commit/ae354c5a45d319b3117c2822b8f6988461f3cb33
Author: Loïc Joly <loic.joly at sonarsource.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/BuiltinFunctionChecker.cpp
M clang/test/Analysis/builtin-functions.cpp
Log Message:
-----------
[analyzer] Model Microsoft "__assume" in the same way as clang "__builtin_assume"
Commit: f2c84211d2834c73ff874389c6bb47b1c76d391a
https://github.com/llvm/llvm-project/commit/f2c84211d2834c73ff874389c6bb47b1c76d391a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/version
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Add missing conditionals for feature-test macros (#80168)
We noticed that some feature-test macros were not conditional on
configuration flags like _LIBCPP_HAS_NO_FILESYSTEM. As a result, code
attempting to use FTMs would not work as intended.
This patch adds conditionals for a few feature-test macros, but more
issues may exist.
rdar://122020466
Commit: fee204f0c9b3b77898c1faa2a7415b0f64f5e7f0
https://github.com/llvm/llvm-project/commit/fee204f0c9b3b77898c1faa2a7415b0f64f5e7f0
Author: NagyDonat <donat.nagy at ericsson.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
M clang/test/Analysis/out-of-bounds-diagnostics.c
A clang/test/Analysis/out-of-bounds-notes.c
Log Message:
-----------
[analyzer] Support interestingness in ArrayBoundV2 (#78315)
This commit improves alpha.security.ArrayBoundV2 in two connected areas:
(1) It calls `markInteresting()` on the symbolic values that are
responsible for the out of bounds access.
(2) Its index-is-in-bounds assumptions are reported in note tags if they
provide information about the value of an interesting symbol.
This commit is limited to "display" changes: it introduces new
diagnostic pieces (potentially to bugs found by other checkers), but
ArrayBoundV2 will make the same assumptions and detect the same bugs
before and after this change.
As a minor unrelated change, this commit also updates/removes some very
old comments which became obsolete due to my previous changes.
Commit: 78a12f94904b69dd8b13f3e3fd258334b77ee7b8
https://github.com/llvm/llvm-project/commit/78a12f94904b69dd8b13f3e3fd258334b77ee7b8
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/libc_search.rst
M libc/spec/posix.td
M libc/src/__support/CMakeLists.txt
A libc/src/__support/intrusive_list.h
M libc/src/search/CMakeLists.txt
A libc/src/search/insque.cpp
A libc/src/search/insque.h
A libc/src/search/remque.cpp
A libc/src/search/remque.h
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/insque_test.cpp
Log Message:
-----------
[libc] implement insque and remque (#80305)
This PR implements the `insque` and `remque` entrypoint functions.
Commit: 30f776f8149dcbda0b6467176488e6551d068e40
https://github.com/llvm/llvm-project/commit/30f776f8149dcbda0b6467176488e6551d068e40
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__thread/support/c11.h
Log Message:
-----------
[libc++] Add missing <errno.h> include in threading support headers (#80311)
This was incorrectly removed when I split up the header.
Commit: c08d972a0043fe67de65ba331a144425c8cea449
https://github.com/llvm/llvm-project/commit/c08d972a0043fe67de65ba331a144425c8cea449
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Pipelines/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bufferization][NFC] Pass `DeallocationOptions` instead of flags (#80675)
Pass `DeallocationOptions` instead of `privateFuncDynamicOwnership`.
This will make it easier to add new options in the future.
Commit: 58f3a77efb633d56a48e031240fc8a37ba2b7557
https://github.com/llvm/llvm-project/commit/58f3a77efb633d56a48e031240fc8a37ba2b7557
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxxabi/src/private_typeinfo.cpp
Log Message:
-----------
[libc++abi] Replace usage of raw assert by _LIBCXXABI_ASSERT (#80689)
We strive not to use raw assert(...) anymore in libc++abi in preparation
for using the hardening framework.
Commit: de9a87301aefda9538eab7fcd563cc6ceec44e0a
https://github.com/llvm/llvm-project/commit/de9a87301aefda9538eab7fcd563cc6ceec44e0a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Split up getShuffleComment into printShuffleMask and printDstRegisterName helpers. NFC.
This will allow us to easily use printDstRegisterName for other mask predicate destination registers, and printout shuffle masks from other instruction types.
Commit: f4714204d0527269e037d85ed998a54678e3895f
https://github.com/llvm/llvm-project/commit/f4714204d0527269e037d85ed998a54678e3895f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] printExtend - add support for mask predicated instructions
Remove handling from EmitAnyX86InstComments and handle all VPMOVSX/VPMOVZX comments in addConstantComments now that we can generically handle the destination + mask register and shuffle mask comment
Commit: 47dcf5d5dc54e62c59fedbef1e8ec3a02c77cb83
https://github.com/llvm/llvm-project/commit/47dcf5d5dc54e62c59fedbef1e8ec3a02c77cb83
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
Log Message:
-----------
[X86] printBroadcast - add support for mask predicated instructions
Handle masked predicated load/broadcasts in addConstantComments now that we can generically handle the destination + mask register
This will more significantly help improve 'fixup constant' comments from #73509
Commit: f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3
https://github.com/llvm/llvm-project/commit/f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
Log Message:
-----------
[X86] printZeroUpperMove - add support for mask predicated instructions
Handle masked predicated movss/movsd in addConstantComments now that we can generically handle the destination + mask register
This will more significantly help improve 'fixup constant' comments from #73509
Commit: 66cd768504b349f7bd16d236a3b4f611ffabf78f
https://github.com/llvm/llvm-project/commit/66cd768504b349f7bd16d236a3b4f611ffabf78f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/InterpBuiltin.cpp
M clang/test/AST/Interp/builtins.cpp
Log Message:
-----------
[clang][Interp] Handle __assume like __builtin_assume.
Commit: 29d47513b3ce706b5df66409170e40ba39f3795a
https://github.com/llvm/llvm-project/commit/29d47513b3ce706b5df66409170e40ba39f3795a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
A flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[mlir][openacc] Add legalize data pass for compute operation (#80351)
This patch adds a simple pass to replace the uses inside compute
operation. It replaces the `varPtr` values with their corresponding
`accPtr` values gathered through the dataClauseOperands.
private and reductions variables are not included in this pass since
they will normally be replace when they are materialized.
---------
Co-authored-by: Slava Zakharin <szakharin at nvidia.com>
Commit: 1ec252298925de50b27930c557ba9de3cc397afe
https://github.com/llvm/llvm-project/commit/1ec252298925de50b27930c557ba9de3cc397afe
Author: Dimitry Andric <dimitry at andric.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__bit_reference
Log Message:
-----------
[libc++] Rename __bit_reference template parameter to avoid conflict (#80661)
As of 4d20cfcf4eb08217ed37c4d4c38dc395d7a66d26, `__bit_reference`
contains a template `__fill_n` with a bool `_FillValue` parameter.
Unfortunately there is a relatively widely used piece of scientific
software called NetCDF, which exposes a (C) macro `_FillValue` in its
public headers.
When building the NetCDF C++ bindings, this quickly leads to compilation
errors when the macro interferes with the template in `__bit_reference`.
Rename the parameter to `_FillVal` to avoid the conflict.
Commit: 341d3a59999dec56f51804a5356b2e38256ab55c
https://github.com/llvm/llvm-project/commit/341d3a59999dec56f51804a5356b2e38256ab55c
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/scoped_allocator
M libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.cnstr/allocs.pass.cpp
Log Message:
-----------
[libc++] Fix ambiguity when using std::scoped_allocator constructor (#80261)
Fixes #78754
Commit: e2bb91b25c8740625fecd127c1d908a2fabd0102
https://github.com/llvm/llvm-project/commit/e2bb91b25c8740625fecd127c1d908a2fabd0102
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
R flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
R mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
R mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
R mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
Revert "[mlir][openacc] Add legalize data pass for compute operation" (#80710)
Reverts llvm/llvm-project#80351
Breaks some buildbot
Commit: 09531e34eec121e9c2319d58bb9fb7edc304027e
https://github.com/llvm/llvm-project/commit/09531e34eec121e9c2319d58bb9fb7edc304027e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__support/xlocale/__posix_l_fallback.h
Log Message:
-----------
[libc++] Add missing include of <wchar.h> in POSIX locale fallbacks
Commit: 2d416219af5c0091f7887e4d4463e63f5a37d811
https://github.com/llvm/llvm-project/commit/2d416219af5c0091f7887e4d4463e63f5a37d811
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/docs/fstack-arrays.md
Log Message:
-----------
[flang][docs] fix stack arrays docs page name (#80708)
The website renders this `<h1>` as the page title in the index. This
patch updates the title to better fit with the names of the other pages.
See the index here https://flang.llvm.org/docs/
Commit: 04f99bec9af495c2571c9e7dcb14face3cfea4ce
https://github.com/llvm/llvm-project/commit/04f99bec9af495c2571c9e7dcb14face3cfea4ce
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/docs/Status/Cxx20Issues.csv
Log Message:
-----------
[libc++][doc] Updates LWG3346 status. (#80536)
The issue addresses an obvious wording issue. Implementing the
constructors as specified in the synposis, as libc++ did, already
implements the fixed behaviour.
Updates:
- LWG3346 pair and tuple copy and move constructor have backwards
specification
Commit: c5f68a711c62aa1748c03215d95ad9b8c7dff9dd
https://github.com/llvm/llvm-project/commit/c5f68a711c62aa1748c03215d95ad9b8c7dff9dd
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxxabi/src/cxa_exception_storage.cpp
M libcxxabi/src/cxa_guard_impl.h
M libcxxabi/src/cxa_thread_atexit.cpp
M libcxxabi/src/fallback_malloc.cpp
M libcxxabi/test/test_fallback_malloc.pass.cpp
Log Message:
-----------
[libc++abi] Revert temporary workaround to unblock Chrome
This reverts commit 372f7dd48f016, which is not needed by Chrome anymore.
Commit: 5e8626c920a8cffff4e286cd8521528cc80c0a3e
https://github.com/llvm/llvm-project/commit/5e8626c920a8cffff4e286cd8521528cc80c0a3e
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/c.c
M clang/test/AST/Interp/literals.cpp
M clang/test/Sema/objc-bool-constant-conversion.m
Log Message:
-----------
[clang][Interp] Handle ObjCBoolLiteralExprs
Emit them just like the others, but these are integer typed.
Commit: 8f070144e3711ad0e5556eaebc72069c0d869342
https://github.com/llvm/llvm-project/commit/8f070144e3711ad0e5556eaebc72069c0d869342
Author: Billy Laws <blaws05 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
Log Message:
-----------
[AArch64] Fix generated types for ARM64EC variadic entry thunk targets (#80595)
ISel handles filling in x4/x5 when calling variadic functions as they
don't correspond to the 5th/6th X64 arguments but rather to the end of
the shadow space on the stack and the size in bytes of all stack
parameters (ignored and written as 0 for calls from entry thunks).
Will PR a follow up with ISel handling after this is merged.
Commit: 8f4d8945536e9fc45db0e349b91c2f4b3a9cae29
https://github.com/llvm/llvm-project/commit/8f4d8945536e9fc45db0e349b91c2f4b3a9cae29
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port d4ef4b818929732bcb68a536ef2c91891c0ad179
Commit: cb8d83a77c25e529f58eba17bb1ec76069a04e90
https://github.com/llvm/llvm-project/commit/cb8d83a77c25e529f58eba17bb1ec76069a04e90
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
A llvm/test/Transforms/InstCombine/pr80597.ll
Log Message:
-----------
[InstCombine] Fix assertion failure in issue80597 (#80614)
The assertion in #80597 failed when we were trying to compute known bits
of a value in an unreachable BB.
https://github.com/llvm/llvm-project/blob/859b09da08c2a47026ba0a7d2f21b7dca705864d/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L749-L810
In this case, `SignBits` is 30 (deduced from instr info), but `Known` is
`10000101010111010011110101000?0?00000000000000000000000000000000`
(deduced from dom cond). Setting high bits of `lshr Known, 1` will lead
to conflict.
This patch masks out high bits of `Known.Zero` to address this problem.
Fixes #80597.
Commit: b4c7152eb4f7971c111e3e2f60b55892def58d5d
https://github.com/llvm/llvm-project/commit/b4c7152eb4f7971c111e3e2f60b55892def58d5d
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
Log Message:
-----------
Revert "[mlir][vector] Drop inner unit dims for transfer ops on dynamic shapes." (#80712)
Reverts llvm/llvm-project#79752 because it is causing regressions in
downstream projects.
Commit: d0b5d32ce6a6287ddab96b028db534cc1bd9a929
https://github.com/llvm/llvm-project/commit/d0b5d32ce6a6287ddab96b028db534cc1bd9a929
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
[AMDGPU] Fixed byte_sel of v_cvt_f32_bf8/v_cvt_f32_fp8 (#80502)
Opsel bits are swapped. Actual byte select table:
Byte OPSEL
0 0
1 2
2 1
3 3
Commit: ea9276d47efb22e26483bd5ad31c2e249ed9846f
https://github.com/llvm/llvm-project/commit/ea9276d47efb22e26483bd5ad31c2e249ed9846f
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
[AMDGPU] GlobalISel for f8 conversions (#80503)
Commit: 95fe47ca7e99d999108705640e49075f4c5f39a7
https://github.com/llvm/llvm-project/commit/95fe47ca7e99d999108705640e49075f4c5f39a7
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A flang/docs/OpenMP-descriptor-management.md
A flang/include/flang/Optimizer/CodeGen/CodeGenOpenMP.h
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
A flang/lib/Optimizer/CodeGen/CodeGenOpenMP.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/OMPDescriptorMapInfoGen.cpp
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M flang/test/Lower/OpenMP/FIR/array-bounds.f90
M flang/test/Lower/OpenMP/FIR/target.f90
A flang/test/Lower/OpenMP/allocatable-array-bounds.f90
A flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
A flang/test/Transforms/omp-descriptor-map-info-gen.fir
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Target/LLVMIR/omptarget-fortran-allocatable-types-host.mlir
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-array-section-1d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-array-section-3d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-map-scopes.f90
A openmp/libomptarget/test/offloading/fortran/target-map-enter-exit-allocatables.f90
A openmp/libomptarget/test/offloading/fortran/target-map-enter-exit-array.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-scopes-enter-exit.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-target-array-section-3d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-target-scopes.f90
Log Message:
-----------
[Flang][OpenMP] Initial mapping of Fortran pointers and allocatables for target devices (#71766)
This patch seeks to add an initial lowering for pointers and allocatable variables
captured by implicit and explicit map in Flang OpenMP for Target operations that
take map clauses e.g. Target, Target Update. Target Exit/Enter etc.
Currently this is done by treating the type that lowers to a descriptor
(allocatable/pointer/assumed shape) as a map of a record type (e.g. a structure) as that's
effectively what descriptor types lower to in LLVM-IR and what they're represented as
in the Fortran runtime (written in C/C++). The descriptor effectively lowers to a structure
containing scalar and array elements that represent various aspects of the underlying
data being mapped (lower bound, upper bound, extent being the main ones of interest
in most cases) and a pointer to the allocated data. In this current iteration of the mapping
we map the structure in it's entirety and then attach the underlying data pointer and map
the data to the device, this allows most of the required data to be resident on the device
for use. Currently we do not support the addendum (another block of pointer data), but
it shouldn't be too difficult to extend this to support it.
The MapInfoOp generation for descriptor types is primarily handled in an optimization
pass, where it expands BoxType (descriptor types) map captures into two maps, one for
the structure (scalar elements) and the other for the pointer data (base address) and
links them in a Parent <-> Child relationship. The later lowering processes will then treat
them as a conjoined structure with a pointer member map.
Commit: 1a6426067fb33a8a789978f6e229108787a041be
https://github.com/llvm/llvm-project/commit/1a6426067fb33a8a789978f6e229108787a041be
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[workflows] Use /mnt as the build directory on Linux (#80583)
There is more space available on /mnt (~56G) than on / (~30G), and we
are starting to see some of the CI jobs run out of disk space on Linux.
Commit: bdc5a87f158577fd65fde555d956637f3f2b10ac
https://github.com/llvm/llvm-project/commit/bdc5a87f158577fd65fde555d956637f3f2b10ac
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
[GitHub][Workflows] Prevent multiple private email comments (temporarily) (#80648)
Seems the easiest way to quiet this workflow while we figure out the final form of it.
Commit: ee06678a7500d5d8f6aa8d2442389cdb90417c38
https://github.com/llvm/llvm-project/commit/ee06678a7500d5d8f6aa8d2442389cdb90417c38
Author: Anton Korobeynikov <anton at korobeynikov.info>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
Add some clarification to email check message
Commit: 5942868a215ce4dbd927a7f0b06432e1eeaed698
https://github.com/llvm/llvm-project/commit/5942868a215ce4dbd927a7f0b06432e1eeaed698
Author: Mészáros Gergely <gergely at streamhpc.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGGPUBuiltin.cpp
A clang/test/CodeGenCUDA/printf-builtin.cu
A clang/test/CodeGenHIP/printf-builtin.hip
Log Message:
-----------
[clang][AMDGPU][CUDA] Handle __builtin_printf for device printf (#68515)
Previously `__builtin_printf` would result to emitting call to `printf`,
even though directly calling `printf` was translated.
Ref: #68478
Commit: 8fa1e5771bbd080c8a2a11c0579a3082cedbf94a
https://github.com/llvm/llvm-project/commit/8fa1e5771bbd080c8a2a11c0579a3082cedbf94a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
M llvm/test/CodeGen/X86/avx512-bugfix-23634.ll
M llvm/test/CodeGen/X86/avx512-cmp.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/divrem-by-select.ll
M llvm/test/CodeGen/X86/fp128-cast.ll
M llvm/test/CodeGen/X86/fp128-i128.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vselect-zero.ll
Log Message:
-----------
[X86] Regenerate some vector constant comments missed in recent patches to improve mask predicate handling in addConstantComments
These were missed as filecheck just ignores what's after the end of the check pattern for each line
Commit: 2096e57905a20903f668848ffd11e6130bfa58e2
https://github.com/llvm/llvm-project/commit/2096e57905a20903f668848ffd11e6130bfa58e2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll
Log Message:
-----------
[X86] addConstantComments - add FP16 MOVSH asm comments support
Commit: dd70aef05a86bb0c1e04c49cc1bd0457ca362ce3
https://github.com/llvm/llvm-project/commit/dd70aef05a86bb0c1e04c49cc1bd0457ca362ce3
Author: Alex Lorenz <arphaman at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/test/CodeGen/X86/swift-async-win64.ll
Log Message:
-----------
[x86_64][windows][swift] do not use Swift async extended frame for wi… (#80468)
…ndows x86_64
targets that use windows 64 prologue
Windows x86_64 stack frame layout is currently not compatible with
Swift's async extended frame, which reserves the slot right below RBP
(RBP-8) for the async context pointer, as it doesn't account for the
fact that a stack object in a win64 frame can be allocated at the same
location. This can cause issues at runtime, for instance, Swift's TCA
test code has functions that fail because of this issue, as they spill a
value to that slack slot, which then gets overwritten by a store into
address returned by the @llvm.swift.async.context.addr() intrinsic (that
ends up being RBP - 8), leading to an incorrect value being used at a
later point when that stack slot is being read from again. This change
drops the use of async extended frame for windows x86_64 subtargets and
instead uses the x32 based approach of allocating a separate stack slot
for the stored async context pointer.
Additionally, LLDB which is the primary consumer of the extended frame
makes assumptions like checking for a saved previous frame pointer at
the current frame pointer address, which is also incompatible with the
windows x86_64 frame layout, as the previous frame pointer is not
guaranteed to be stored at the current frame pointer address. Therefore
the extended frame layout can be turned off to fix the current
miscompile without introducing regression into LLDB for windows x86_64
as it already doesn't work correctly. I am still investigating what
should be made for LLDB to support using an allocated stack slot to
store the async frame context instead of being located at RBP - 8 for
windows.
Commit: 930996e9e442d69a321cd5c945543d37c97f4c0e
https://github.com/llvm/llvm-project/commit/930996e9e442d69a321cd5c945543d37c97f4c0e
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Log Message:
-----------
[ValueTracking][NFC] Pass `SimplifyQuery` to `computeKnownFPClass` family (#80657)
This patch refactors the interface of the `computeKnownFPClass` family
to pass `SimplifyQuery` directly.
The motivation of this patch is to compute known fpclass with
`DomConditionCache`, which was introduced by
https://github.com/llvm/llvm-project/pull/73662. With
`DomConditionCache`, we can do more optimization with context-sensitive
information.
Example (extracted from
[fmt/format.h](https://github.com/fmtlib/fmt/blob/e17bc67547a66cdd378ca6a90c56b865d30d6168/include/fmt/format.h#L3555-L3566)):
```
define float @test(float %x, i1 %cond) {
%i32 = bitcast float %x to i32
%cmp = icmp slt i32 %i32, 0
br i1 %cmp, label %if.then1, label %if.else
if.then1:
%fneg = fneg float %x
br label %if.end
if.else:
br i1 %cond, label %if.then2, label %if.end
if.then2:
br label %if.end
if.end:
%value = phi float [ %fneg, %if.then1 ], [ %x, %if.then2 ], [ %x, %if.else ]
%ret = call float @llvm.fabs.f32(float %value)
ret float %ret
}
```
We can prove the signbit of `%value` is always zero. Then the fabs can
be eliminated.
Commit: 214536b0d8b68f826589600472e28bbb903d6d7a
https://github.com/llvm/llvm-project/commit/214536b0d8b68f826589600472e28bbb903d6d7a
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/test/Driver/target-cpu-features.f90
Log Message:
-----------
Fix broken ARM processor features test (#80717)
This should fix failed build bots, so pushing before Windows build is done.
Commit: 032a70ee1183dba5b942778f855e1d58244e8077
https://github.com/llvm/llvm-project/commit/032a70ee1183dba5b942778f855e1d58244e8077
Author: stephenpeckham <118857872+stephenpeckham at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
Log Message:
-----------
[NFC] Fix typo (#80703)
Commit: d00e6d07b18dbc80b843e332a66d2777c6564523
https://github.com/llvm/llvm-project/commit/d00e6d07b18dbc80b843e332a66d2777c6564523
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/test/Dialect/SparseTensor/external.mlir
A mlir/test/Dialect/SparseTensor/torch_linalg.mlir
Log Message:
-----------
[mlir][sparse] refine sparse assembler strategy (#80521)
Rewrite *all* public methods, making original internal, private methods,
and exposing wrappers under the original name. This works a bit better
in practice (when combined with c-interface mechanism of torch-mlir for
example).
Commit: ac585ab71470d4f20c96a95b49e852ee1c967003
https://github.com/llvm/llvm-project/commit/ac585ab71470d4f20c96a95b49e852ee1c967003
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
Log Message:
-----------
[lldb] Remove unused private TypeCategoryMap methods (NFC) (#80602)
Commit: 0c02ea05c8414e72339e2521d1fdae54e91569bb
https://github.com/llvm/llvm-project/commit/0c02ea05c8414e72339e2521d1fdae54e91569bb
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
Log Message:
-----------
[lldb] Cleanup regex in libcxx formatters (NFC) (#80618)
I noticed a number of regex for libcxx formatters use an unnecessary regex grouping.
This change removes those parentheses.
Commit: 0bf165e383ac9c58dcb1764aef9f35334afa0cc7
https://github.com/llvm/llvm-project/commit/0bf165e383ac9c58dcb1764aef9f35334afa0cc7
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add support for RISC-V Pointer Masking (#79929)
This patch implements the v0.8.1 specification. This patch reports
version 0.8 in llvm since `RISCVISAInfo::ExtensionVersion` only has a
`Major` and `Minor` version number. This patch includes includes support
of the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make
up RISC-V pointer masking.
All of these extensions require emitting attribute containing correct
`march` string.
`Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a 2-bit WARL field (PMM).
The extension does not specify how PMM is set, and therefore this patch
does not need to address this. One example of how it *could* be set is
using the Zicsr instructions to update the PMM bits of the described
registers.
The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
Commit: 9805c051f7d3a09a629c51461b49f8070c01de62
https://github.com/llvm/llvm-project/commit/9805c051f7d3a09a629c51461b49f8070c01de62
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[workflows] Close issues used for backports once the PR has been created (#80394)
This will allow us to track the state of the backport request in the PR,
rather than in the issue. The state updates for PRs can be automated, so
this will save us some triage work.
Commit: 37462944513731af2743d95e5dd40bdbeefd6460
https://github.com/llvm/llvm-project/commit/37462944513731af2743d95e5dd40bdbeefd6460
Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/cos-1.ll
Log Message:
-----------
[Transforms] Add more cos combinations to SimplifyLibCalls and InstCombine (#79699)
Add cos(fabs(x)) -> cos(x) and cos(copysign(x, y)) -> cos(x).
Commit: 93fd05c0891caa8c68cb37b64217467a0ef60412
https://github.com/llvm/llvm-project/commit/93fd05c0891caa8c68cb37b64217467a0ef60412
Author: Andrew Gozillon <Andrew.Gozillon at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
Log Message:
-----------
[Flang][OpenMP] Attempt to make map-types-and-sizes.f90 test more agnostic to other architectures
This test was updated by me recently, however, the newly
added CHECK-LABEL checks are breaking one of the RHEL
PowerPC buildbots as the functions appear to be generated
slightly different (in this case added attributes I think).
Commit: 64a317ad0765a2b3748d2b74b9a0d4738250787a
https://github.com/llvm/llvm-project/commit/64a317ad0765a2b3748d2b74b9a0d4738250787a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
Log Message:
-----------
[libc++][NFC] Fix typo in comment
Commit: 22544e2a54370a3c0b12765981c312f9ec04f1cc
https://github.com/llvm/llvm-project/commit/22544e2a54370a3c0b12765981c312f9ec04f1cc
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/test/Driver/func-attr-fast-math.f90
Log Message:
-----------
[flang] Set fast math related function attributes for -Ofast/-ffast-math (#79301)
The implemented logic matches the logic used for Clang in emitting these
attributes. Although it's hoped that function attributes won't be needed
in the future (vs using fast math flags in individual IR instructions),
there are codegen differences currently with/without these attributes,
as can be seen in issues like #79257 or by hacking Clang to avoid
producing these attributes and observing codegen changes.
Commit: b99163fe8feeacba7797d5479bbcd5d8f327dd2d
https://github.com/llvm/llvm-project/commit/b99163fe8feeacba7797d5479bbcd5d8f327dd2d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Fix description of Ssstrict to have a closing parenthesis.
Commit: dd22140e21f2ef51cf031354966a3d41c191c6e7
https://github.com/llvm/llvm-project/commit/dd22140e21f2ef51cf031354966a3d41c191c6e7
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
Log Message:
-----------
[Profile][Windows] Drop extern for __buildid. (#80700)
Commit: fa7d0d3e35f74486ccb0faa88ec706defe7dd2d2
https://github.com/llvm/llvm-project/commit/fa7d0d3e35f74486ccb0faa88ec706defe7dd2d2
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
A flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[mlir][openacc] Add legalize data pass for compute operation (#80351)
This patch adds a simple pass to replace the uses inside compute operation. It
replaces the `varPtr` values with their corresponding `accPtr` values gathered
through the dataClauseOperands.
private and reductions variables are not included in this pass since they will
normally be replace when they are materialized.
Commit: 9ac6eb5bec2367b34f4b839a051e49318adf9dd1
https://github.com/llvm/llvm-project/commit/9ac6eb5bec2367b34f4b839a051e49318adf9dd1
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
Log Message:
-----------
[mlir][openacc] Add MLIRSupport to MLIROpenACCTransforms
Commit: 152325d342ae430872bb587ed3892253f23f782a
https://github.com/llvm/llvm-project/commit/152325d342ae430872bb587ed3892253f23f782a
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXIL.td
M llvm/utils/TableGen/DXILEmitter.cpp
Log Message:
-----------
[DirectX][NFC] Change all DXIL TableGen tokens to CamelCase (#80714)
These changes are in preparation for potential improvement of DXIL
operation description and addition of more DXIL operations to `DXIL.td`.
Commit: 4b6062619acf1cdc7b426520dd908d9fab70ed49
https://github.com/llvm/llvm-project/commit/4b6062619acf1cdc7b426520dd908d9fab70ed49
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
R flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
R mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
R mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
R mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
Revert "[mlir][openacc] Add legalize data pass for compute operation (#80351)"
This reverts commit fa7d0d3e35f74486ccb0faa88ec706defe7dd2d2.
Commit: 76706090c2f672ae933798292bfa889f9e3dac3d
https://github.com/llvm/llvm-project/commit/76706090c2f672ae933798292bfa889f9e3dac3d
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBStructuredData.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/CommandObject.cpp
M lldb/source/Target/Statistics.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
M lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py
Log Message:
-----------
Add commands frequency to statistics dump (#80375)
Adding command interpreter statistics into "statistics dump" command so
that we can track the command usage frequency for telemetry purpose.
This is useful to answer questions like what is the most frequently used
lldb commands across all our users.
---------
Co-authored-by: jeffreytan81 <jeffreytan at fb.com>
Commit: c166a43c6e6157b1309ea757324cc0a71c078e66
https://github.com/llvm/llvm-project/commit/c166a43c6e6157b1309ea757324cc0a71c078e66
Author: weiguozhi <57237827+weiguozhi at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang-c/Index.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/Specifiers.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/CodeGen/debug-info-cc.c
M clang/test/CodeGen/preserve-call-conv.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/Sema/no_callconv.cpp
A clang/test/Sema/preserve-none-call-conv.c
M clang/tools/libclang/CXType.cpp
M llvm/docs/LangRef.rst
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/IR/CallingConv.h
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/Target/X86/X86CallingConv.td
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/test/Bitcode/compatibility.ll
A llvm/test/CodeGen/X86/dynamic-regmask-preserve-none.ll
M llvm/test/CodeGen/X86/ipra-reg-usage.ll
M llvm/test/CodeGen/X86/ipra-transform.ll
A llvm/test/CodeGen/X86/preserve_none_swift.ll
A llvm/test/CodeGen/X86/preserve_nonecc64-ret-double.ll
A llvm/test/CodeGen/X86/preserve_nonecc64.ll
A llvm/test/CodeGen/X86/preserve_nonecc_call.ll
A llvm/test/CodeGen/X86/preserve_nonecc_musttail.ll
Log Message:
-----------
New calling convention preserve_none (#76868)
The new experimental calling convention preserve_none is the opposite
side of existing preserve_all. It tries to preserve as few general
registers as possible. So all general registers are caller saved
registers. It can also uses more general registers to pass arguments.
This attribute doesn't impact floating-point registers. Floating-point
registers still follow the c calling convention.
Currently preserve_none is supported on X86-64 only. It changes the c
calling convention in following fields:
* RSP and RBP are the only preserved general registers, all other
general registers are caller saved registers.
* We can use [RDI, RSI, RDX, RCX, R8, R9, R11, R12, R13, R14, R15, RAX]
to pass arguments.
It can improve the performance of hot tailcall chain, because many
callee saved registers' save/restore instructions can be removed if the
tail functions are using preserve_none. In my experiment in protocol
buffer, the parsing functions are improved by 3% to 10%.
Commit: 0d091206dd656c2a9d31d6088a4aa6f9c2cc7156
https://github.com/llvm/llvm-project/commit/0d091206dd656c2a9d31d6088a4aa6f9c2cc7156
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
A flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[mlir][openacc] Add legalize data pass for compute operation (#80351)
This patch adds a simple pass to replace the uses inside compute operation. It
replaces the `varPtr` values with their corresponding `accPtr` values gathered
through the dataClauseOperands.
private and reductions variables are not included in this pass since they will
normally be replace when they are materialized.
Reland with fix for dependencies
Commit: cd481fa827b76953cd12dae9319face96670c0b3
https://github.com/llvm/llvm-project/commit/cd481fa827b76953cd12dae9319face96670c0b3
Author: Yinying Li <107574043+yinying-lisa-li at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/SparseTensor.h
M mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
M mlir/lib/Bindings/Python/DialectSparseTensor.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenUtils.h
M mlir/test/CAPI/sparse_tensor.c
M mlir/test/Dialect/SparseTensor/conversion.mlir
M mlir/test/Dialect/SparseTensor/sparse_fill_zero.mlir
M mlir/test/python/dialects/sparse_tensor/dialect.py
Log Message:
-----------
[mlir][sparse] Change LevelType enum to 64 bit (#80501)
1. C++ enum is set through enum class LevelType : uint_64.
2. C enum is set through typedef uint_64 level_type. It is due to the
limitations in Windows build: setting enum width to ui64 is not
supported in C.
Commit: ae9e1fd2edb6eb11dfd6816d1e9013e39e21aa04
https://github.com/llvm/llvm-project/commit/ae9e1fd2edb6eb11dfd6816d1e9013e39e21aa04
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
Log Message:
-----------
[clang] Fix extractAPI typo in comments, NFC
Commit: 6b42625b1f983f6aafb9f4fe2953970c73963603
https://github.com/llvm/llvm-project/commit/6b42625b1f983f6aafb9f4fe2953970c73963603
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-update.f90
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/test/Dialect/OpenACC/canonicalize.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/legalize-data.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
Log Message:
-----------
[mlir][openacc] Simplify IR with acc.loop control (#80387)
When the new `acc.loop` design was introduced some of the loop
information like `gang`/`vector`/`worker` were also updated to support
`device_type`.
With a conflict in parsing/printing, the keyword only value for
`async`/`gang`/`vector`/`worker` were printed/parsed with an empty set
of parenthesis `()`. To make the IR clearer to read and similar across
the operations, the loop control part of is now prefixed by `control`
and this allow to remove the need of the empty `()`.
Commit: e722d9662dd8cdd3be9e434b057593e97a7d4417
https://github.com/llvm/llvm-project/commit/e722d9662dd8cdd3be9e434b057593e97a7d4417
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/RISCV/and-add-lsr.ll
Log Message:
-----------
[DAG] Avoid a crash when checking size of scalable type in visitANDLike
Fixes https://github.com/llvm/llvm-project/issues/80744. This transform
doesn't handled vectors at all, The fixed length ones pass the first
check, but would fail the constant operand checks which immediate follow.
This patch takes the simplest approach, and just guards the transform
for scalar integers.
Commit: dfdea4d5fb18ddf928b043a359e50c3f015dae71
https://github.com/llvm/llvm-project/commit/dfdea4d5fb18ddf928b043a359e50c3f015dae71
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/MC/RISCV/attribute-arch.s
Log Message:
-----------
[RISCV] Update llvm/test/MC/RISCV/attribute-arch.s for RISC-V Pointer Masking (#80748)
I forgot to update this test in #79929
Commit: 8ce036d539cdaaee50ce7c63f963b7d68c43282e
https://github.com/llvm/llvm-project/commit/8ce036d539cdaaee50ce7c63f963b7d68c43282e
Author: ChiaHungDuan <chiahungduan at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/tsd_test.cpp
M compiler-rt/lib/scudo/standalone/tsd_exclusive.h
M compiler-rt/lib/scudo/standalone/tsd_shared.h
Log Message:
-----------
[scudo] Add ScopedTSD to avoid releasing TSD manually (#80061)
This makes the use of TSD be RAII style and avoid the exposing of the
type of TSDs.
Also move some thread safety analyses from static to runtime because of
its limitation. Even we mark some code path as NO_THREAD_SAFETY_ANALYSIS
but we still have the `assertLocked()` cover the correctness.
Commit: a7bc9cb6ffa91ff0ebabc45c0c7263c7c2c3a4de
https://github.com/llvm/llvm-project/commit/a7bc9cb6ffa91ff0ebabc45c0c7263c7c2c3a4de
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Sema/Lookup.h
M clang/test/CXX/class.derived/class.member.lookup/p11.cpp
Log Message:
-----------
[Clang][Sema] Fix regression due to missing ambiguity check before attempting access check. (#80730)
Previously when fixing ambiguous lookup diagnostics in
cc1b6668c57170cd440d321037ced89d6a61a9cb The change refactored
`LookupResult` to split out diagnosing access and ambiguous lookups. The
call to `getSema().CheckLookupAccess(...)` should have guarded by a
check for isAmbiguous(). This change adds that guard.
Fixes: https://github.com/llvm/llvm-project/issues/80435
Commit: 6ce03ff3fef8fb6fa9afe8eb22c6d98bced26d48
https://github.com/llvm/llvm-project/commit/6ce03ff3fef8fb6fa9afe8eb22c6d98bced26d48
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
Revert "[IR] Use range-based for loops (NFC)"
This reverts commit e8512786fedbfa6ddba70ceddc29d7122173ba5e.
This revert is done because llvm::drop_begin over an empty ArrayRef
doesn't return an empty range, and therefore can lead to an invalid
address returned instead.
See discussion in https://github.com/llvm/llvm-project/pull/80737 for
more context.
Commit: e2cfdf7b6a09a2159a2ce3cf4fff022b6d98b928
https://github.com/llvm/llvm-project/commit/e2cfdf7b6a09a2159a2ce3cf4fff022b6d98b928
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__memory/uninitialized_algorithms.h
A libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp
Log Message:
-----------
[libc++] Fix vector<const T> (#80711)
#80558 introduced code that assumed that the element type of `vector` is
never const. This fixes it and adds a test. Eventually we should remove
the `allocator<const T>` extension.
Commit: dbed89814e5b9ba25a349a5b9acf4a7164e33834
https://github.com/llvm/llvm-project/commit/dbed89814e5b9ba25a349a5b9acf4a7164e33834
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
Log Message:
-----------
[AMDGPU] Add missing `__builtin_amdgcn_wavefrontsize` builtin (#80741)
Summary:
The backend supports the wavefrontsize intrinsic, and suggests that it
is tied to a corresponding clang builtin, but it is not actually
present. This simply adds it in so it can be used from clang. This
attribute likely isn't the best to rely on, but for the `libc` use-case
we will need to detect a struct's differing size in a way that will
depend on the wavefront size.
Commit: 5a9af39aab40bba52d4e46cabf4b1ab47f614fa2
https://github.com/llvm/llvm-project/commit/5a9af39aab40bba52d4e46cabf4b1ab47f614fa2
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp
M mlir/test/Dialect/SparseTensor/sparse_vector_mv.mlir
Log Message:
-----------
[mlir][sparse] made sparse vectorizer more robust on position of invariants (#80766)
Because the sparse vectorizer relies on the code coming out of the
sparsifier, the "patterns" are not always made very general. However, a
recent change in the generated code revealed an obvious situation where
the subscript analysis could be made a bit more robust.
Fixes:
https://github.com/llvm/llvm-project/issues/79897
Commit: 792d928e15aa30c8b686eff465598ceea0b03891
https://github.com/llvm/llvm-project/commit/792d928e15aa30c8b686eff465598ceea0b03891
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/libclc-tests.yml
M .github/workflows/lldb-tests.yml
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[workflows] Fix lldb-tests and libclc-tests (#80751)
This was broken by d25022bb689b9bf48a24c0ae6c29c1d3c2f32823, which
caused the workflow to pass an empty string to ninja as the target. The
'all' target is probably not the right target for these tests, but this
is what the behavior was before
d25022bb689b9bf48a24c0ae6c29c1d3c2f32823.
Commit: eff77d8456a5ba9a05a0c3a29113643fbb180230
https://github.com/llvm/llvm-project/commit/eff77d8456a5ba9a05a0c3a29113643fbb180230
Author: Florian Mayer <fmayer at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
M compiler-rt/lib/scudo/standalone/platform.h
M compiler-rt/lib/scudo/standalone/stack_depot.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp
Log Message:
-----------
[scudo] [MTE] resize stack depot for allocation ring buffer (#74515)
Co-authored-by: ChiaHungDuan <f103119 at gmail.com>
Commit: c175157dc158d1e4ebdf60c6af75a5106c474780
https://github.com/llvm/llvm-project/commit/c175157dc158d1e4ebdf60c6af75a5106c474780
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
Log Message:
-----------
[mlir][sparse] fix windows build issue with hex literals (#80770)
Fixes:
https://github.com/llvm/llvm-project/issues/73828
Commit: c3291253c3b5d1794492ccebe39b7c2c5f74c378
https://github.com/llvm/llvm-project/commit/c3291253c3b5d1794492ccebe39b7c2c5f74c378
Author: Florian Mayer <fmayer at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/fuzz/get_error_info_fuzzer.cpp
M compiler-rt/lib/scudo/standalone/platform.h
M compiler-rt/lib/scudo/standalone/stack_depot.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/wrappers_c_bionic.cpp
Log Message:
-----------
Revert "[scudo] [MTE] resize stack depot for allocation ring buffer" (#80777)
Reverts llvm/llvm-project#74515
Broke build: https://lab.llvm.org/buildbot/#/builders/75/builds/42512
Commit: 99ddd77ed9e12f55f8d4b66eec02154a0b3a6bf0
https://github.com/llvm/llvm-project/commit/99ddd77ed9e12f55f8d4b66eec02154a0b3a6bf0
Author: modiking <modiking213 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
A llvm/test/Transforms/LoopUnroll/pr77842.ll
Log Message:
-----------
[LoopUnroll] Introduce PragmaUnrollFullMaxIterations as a hard cap on how many iterations we try to unroll (#78648)
Fixes [PR77842](https://github.com/llvm/llvm-project/issues/77842) where
UBSAN causes pragma full unroll to try and unroll INT_MAX times. This
sets a cap to make sure we don't attempt this and crash the compiler.
Testing:
ninja check-all with new test
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: a71147dd28c6676fc46e4ec0a5d6e0b0823cced5
https://github.com/llvm/llvm-project/commit/a71147dd28c6676fc46e4ec0a5d6e0b0823cced5
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
A llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll
Log Message:
-----------
[WebAssembly] improve getRegForPromotedValue to avoid meanless value copy (#80469)
When promoted value, it is meaningless to copy value from reg to another
reg with the same type.
This PR add additional check for this cases to reduce the code size.
Fixes: #80053.
Commit: 06a728f3feab876f9195738b5774e82dadc0f3a7
https://github.com/llvm/llvm-project/commit/06a728f3feab876f9195738b5774e82dadc0f3a7
Author: Jinyang He <hejinyang at loongson.cn>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
A lld/test/ELF/loongarch-relax-align.s
A lld/test/ELF/loongarch-relax-emit-relocs.s
Log Message:
-----------
[lld][ELF] Support relax R_LARCH_ALIGN (#78692)
Refer to commit 6611d58f5bbc ("Relax R_RISCV_ALIGN"), we can relax
R_LARCH_ALIGN by same way. Reuse `SymbolAnchor`, `RISCVRelaxAux` and
`initSymbolAnchors` to simplify codes. As `riscvFinalizeRelax` is an
arch-specific function, put it override on `TargetInfo::finalizeRelax`,
so that LoongArch can override it, too.
The flow of relax R_LARCH_ALIGN is almost consistent with RISCV. The
difference is that LoongArch only has 4-bytes NOP and all executable
insn is 4-bytes aligned. So LoongArch not need rewrite NOP sequence.
Alignment maxBytesEmit parameter is supported in psABI v2.30.
Commit: abe102b87204a8b5bb637b675ed58ee6695016af
https://github.com/llvm/llvm-project/commit/abe102b87204a8b5bb637b675ed58ee6695016af
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M compiler-rt/lib/asan/asan_descriptions.cpp
M compiler-rt/lib/hwasan/hwasan_report.cpp
M compiler-rt/lib/memprof/memprof_descriptions.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
Log Message:
-----------
[Sanitizer][NFC] Replaces a few `InternalScopedString::AppendF` with `InternalScopedString::Append` (#80574)
Commit: c1c5b854adc9414ee3d8c55ddd07bdb4cc5b7171
https://github.com/llvm/llvm-project/commit/c1c5b854adc9414ee3d8c55ddd07bdb4cc5b7171
Author: Nilanjana Basu <n_basu at apple.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_estimated_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/interleave_count_for_known_tc.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-inductions-unusual-types.ll
M llvm/test/Transforms/LoopVectorize/SystemZ/zero_unroll.ll
M llvm/test/Transforms/LoopVectorize/X86/imprecise-through-phis.ll
M llvm/test/Transforms/LoopVectorize/X86/interleave_short_tc.ll
M llvm/test/Transforms/LoopVectorize/X86/limit-vf-by-tripcount.ll
M llvm/test/Transforms/LoopVectorize/X86/load-deref-pred.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/strided_load_cost.ll
M llvm/test/Transforms/LoopVectorize/X86/unroll-small-loops.ll
M llvm/test/Transforms/LoopVectorize/X86/vect.omp.force.small-tc.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks-loopid-dbg.ll
M llvm/test/Transforms/LoopVectorize/X86/vectorization-remarks.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
Log Message:
-----------
[LV] Remove loop trip count threshold for deciding whether to interleave a loop (#67725)
A set of microbenchmarks (https://github.com/llvm/llvm-test-suite/pull/26) showed that loop interleaving can be beneficial for loops with low trip count as well. Loop interleaving count computation is updated accordingly in prior patches while this patch removes the loop trip count threshold for interleaving.
Commit: c0cb0be85ca7aa3f9c14f2c8272f581a20474619
https://github.com/llvm/llvm-project/commit/c0cb0be85ca7aa3f9c14f2c8272f581a20474619
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/WebAssembly/immediates.ll
Log Message:
-----------
Mark llvm/test/CodeGen/WebAssembly/immediates.ll as passing on MIPS (#80771)
Fixes #80533
Commit: 0123cefc00177e4fc7daa0dadf98ca8336760785
https://github.com/llvm/llvm-project/commit/0123cefc00177e4fc7daa0dadf98ca8336760785
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/include/lldb/API/SBProcess.h
M lldb/include/lldb/Target/PostMortemProcess.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/ProcessTrace.h
M lldb/source/API/SBProcess.cpp
M lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp
M lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.h
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.h
M lldb/source/Target/ProcessTrace.cpp
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
Log Message:
-----------
Add a new SBProcess:: GetCoreFile() API (#80767)
We have a Python script that needs to locate coredump path during
debugging so that we can retrieve certain metadata files associated with
it. Currently, there is no API for this.
This patch adds a new `SBProcess::GetCoreFile()` to retrieve target dump
file spec used for dump debugging. Note: this is different from the main
executable module spec. To achieve this, the patch hoists m_core_file
into PostMortemProcess for sharing.
---------
Co-authored-by: jeffreytan81 <jeffreytan at fb.com>
Commit: 2c2d291b4568381999442e47fc77f949f19be0bc
https://github.com/llvm/llvm-project/commit/2c2d291b4568381999442e47fc77f949f19be0bc
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
Log Message:
-----------
[concepts] Extract function template pack arguments from the current instantiation if possible (#80594)
Before the constraint substitution, we employ
`getTemplateInstantiationArgs`, which in turn attempts to inspect
`TemplateArgument`s from the function template. For parameter packs from
their parent contexts, we used to extract the arguments from the
specialization type, in which could result in non-canonical argument
types e.g. `PackExpansionType`.
This may break the contract that, during a tree transformation, in
`TreeTransform::TryExpandParameterPacks`, the corresponding
`TemplateArgument`s for an `UnexpandedParameterPack` are expected to be
of `Pack` kinds if we're expanding template parameters.
Fixes https://github.com/llvm/llvm-project/issues/72557.
Commit: 62838b872f1d8c6ffd88c355ece9324258169bdd
https://github.com/llvm/llvm-project/commit/62838b872f1d8c6ffd88c355ece9324258169bdd
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/test/CAPI/sparse_tensor.c
Log Message:
-----------
[mlir][test] Fix -Wformat in sparse_tensor.c (NFC)
llvm-project/mlir/test/CAPI/sparse_tensor.c:50:42:
error: format specifies type 'unsigned long' but the argument has type 'MlirSparseTensorLevelType' (aka 'unsigned long long') [-Werror,-Wformat]
50 | fprintf(stderr, "level_type: %lu\n", lvlTypes[l]);
| ~~~ ^~~~~~~~~~~
| %llu
1 error generated.
Commit: 8f80df0f52c4294d23d0510b01be6d6491714058
https://github.com/llvm/llvm-project/commit/8f80df0f52c4294d23d0510b01be6d6491714058
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/build-ci-container.yml
R .github/workflows/containers/github-action-ci/Dockerfile
A .github/workflows/containers/github-action-ci/bootstrap.patch
A .github/workflows/containers/github-action-ci/stage1.Dockerfile
A .github/workflows/containers/github-action-ci/stage2.Dockerfile
A .github/workflows/containers/github-action-ci/storage.conf
Log Message:
-----------
[Github] Use building LLVM as perf-training for CI container (#80713)
This patch adjusts the build process for building the toolchain for the
CI container to perform more rigorous perf-training for PGO,
particularly building the entirety of LLVM as that is what showed the
best results while benchmarking. This patch also splits the job into two
stages to avoid timeouts due to the large increase in buildtime. There
are a couple other hacks added in here to make things work that we can
do away with eventually once we're able to run jobs like this on more
powerful self-hosted runners.
Commit: 5953532615595918d006ace2ad83fe33d1cd3915
https://github.com/llvm/llvm-project/commit/5953532615595918d006ace2ad83fe33d1cd3915
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/docs/lldb-gdb-remote.txt
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
M lldb/source/Breakpoint/WatchpointAlgorithms.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py
M lldb/tools/debugserver/source/RNBRemote.cpp
Log Message:
-----------
[lldb] Add QSupported key to report watchpoint types supported (#80376)
debugserver on arm64 devices can manage both Byte Address Select
watchpoints (1-8 bytes) and MASK watchpoints (8 bytes-2 gigabytes). This
adds a SupportedWatchpointTypes key to the QSupported response from
debugserver with a list of these, so lldb can take full advantage of
them when creating larger regions with a single hardware watchpoint.
Also add documentation for this, and two other lldb extensions, to the
lldb-gdb-remote.txt documentation.
Re-enable TestLargeWatchpoint.py on Darwin systems when testing with the
in-tree built debugserver. I can remove the "in-tree built debugserver"
in the future when this new key is handled by an Xcode debugserver.
Commit: 87ff65b07c82337d99b0dc0ca562e394ecedc11b
https://github.com/llvm/llvm-project/commit/87ff65b07c82337d99b0dc0ca562e394ecedc11b
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/test/CAPI/sparse_tensor.c
Log Message:
-----------
[mlir][test] Fix -Wformat in sparse_tensor.c (NFC)
llvm-project/mlir/test/CAPI/sparse_tensor.c:50:43:
error: format specifies type 'unsigned long long' but the argument has type 'MlirSparseTensorLevelType' (aka 'unsigned long') [-Werror,-Wformat]
fprintf(stderr, "level_type: %llu\n", lvlTypes[l]);
~~~~ ^~~~~~~~~~~
%lu
1 error generated.
Commit: c1ac2cfac7f160107041758f458aaf1087f5cac2
https://github.com/llvm/llvm-project/commit/c1ac2cfac7f160107041758f458aaf1087f5cac2
Author: Oleksandr "Alex" Zinenko <zinenko at google.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/docs/Dialects/Affine.md
Log Message:
-----------
Use a markdown list in Affine dialect docs
Commit: 9a5fb74fd162da70609fe5f81864d01cdc776df1
https://github.com/llvm/llvm-project/commit/9a5fb74fd162da70609fe5f81864d01cdc776df1
Author: Artem Tyurin <artem.tyurin at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SPIRV/IR/SPIRVDialect.cpp
M mlir/test/Dialect/SPIRV/Transforms/inlining.mlir
Log Message:
-----------
[mlir][spirv] Handle a missing case when inlining spirv.ReturnValue (#80733)
Fixes https://github.com/llvm/llvm-project/issues/73285.
Commit: d193ac4f7180d8242c25d941cf3ff8a150538af6
https://github.com/llvm/llvm-project/commit/d193ac4f7180d8242c25d941cf3ff8a150538af6
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
Log Message:
-----------
[mlir][vector] Drop inner unit dims for xWrite on dynamic shapes. (#80725)
This is part of
https://github.com/llvm/llvm-project/commit/66347e516e22f9159b86024071fb92f364ac4418
The regression in downstream projects is about transfer_read patterns,
which needs more investigation. Add the support for transfer_write for
now.
Commit: 942cb2427a0e19f63b2f5b7da3d3fa6a594df3fe
https://github.com/llvm/llvm-project/commit/942cb2427a0e19f63b2f5b7da3d3fa6a594df3fe
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/TargetMachine.h
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/unittests/MIR/PassBuilderCallbacksTest.cpp
Log Message:
-----------
[CodeGen][NewPM] Consolidate PASS_NAME and CONSTRUCTOR in MachinePassRegistry.def (#80779)
This matches the optimization pipeline's PassRegistry.def.
I ran into a bug where CONSTRUCTOR wasn't always being used (in
PassBuilder::registerMachineFunctionAnalyses()).
Make DUMMY_* just accept a pass name, there's no point in having proper
constructors if the generated dummy class has a templated constructor
accepting arbitrary arguments.
Remove unused getPassNameFromLegacyName() as it was using this but for
no purpose.
Remove DUMMY_MACHINE_FUNCTION_ANALYSIS, we can just add those as we port
them.
This for some reason exposed missing mock calls in existing unittests.
Commit: 617602d4f23e89e56afd0f550bcf72deb83ed0cb
https://github.com/llvm/llvm-project/commit/617602d4f23e89e56afd0f550bcf72deb83ed0cb
Author: sstwcw <su3e8a96kzlver at posteo.net>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Handle generic selections inside parentheses (#79785)
new
```C
while (_Generic(x, //
long: x)(x) > x) {
}
while (_Generic(x, //
long: x)(x)) {
}
```
old
```C
while (_Generic(x, //
long: x)(x) > x) {
}
while (_Generic(x, //
long: x)(x)) {
}
```
In the first case above, the second line previously aligned to the open
parenthesis. The 4 spaces did not get added by the fallback line near
the end of getNewLineColumn because there was already some indentaton.
Now the spaces get added explicitly.
In the second case above, without the fake parentheses, the second line
did not respect the outer parentheses, because the LastSpace field did
not get set without the fake parentheses. Now the indentation of the
outer level is used instead.
Commit: 1442b0e65370b603dcd4c7cfc300f19937c3bc79
https://github.com/llvm/llvm-project/commit/1442b0e65370b603dcd4c7cfc300f19937c3bc79
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Remove redundant buffer copies for ULEB128 decode calls. (#80199)
This patch removes a couple of redundant buffer copies in emitTable for
setting up calls to decodeULEB128. Instead, provide the Table.data
buffer directly to the calls-- where decodeULEB128 does its own buffer
overflow checking.
Factor out 7 explicit loops to emit ULEB128 bytes into emitULEB128. Also
factor out 4 copies of 24-bit numtoskip emission into emitNumToSkip.
The functionality is already covered by existing unit tests and by
virtue of most of the in-tree back-ends exercising the decoder emitter.
Commit: fa70b5d1309f15244cb5528d545d42865cbf8e18
https://github.com/llvm/llvm-project/commit/fa70b5d1309f15244cb5528d545d42865cbf8e18
Author: Yuxuan Chen <yuxuanchen1997 at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
Log Message:
-----------
[Coroutines][NFC] Refactor CoroSplit for Switch Resume ABI (#80758)
Commit: 397e91f0f387bf2db0cc320a9078a60d2334545e
https://github.com/llvm/llvm-project/commit/397e91f0f387bf2db0cc320a9078a60d2334545e
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M compiler-rt/lib/memprof/memprof_mapping.h
Log Message:
-----------
[MemProf][NFC] Compute SHADOW_ENTRY_SIZE from MEM_GRANULARITY and SHA… (#80589)
…DOW_SCALE
As MEM_GRANULARITY represents the size of memory block mapped to a
single shadow entry, and SHADOW_SCALE represents the scale of shadow
mapping, so the single shadow entry size can be computed as
(MEM_GRANULARITY >> SHADOW_SCALE).
This patch replaces the hardcoded SHADOW_ENTRY_SIZE with
(MEM_GRANULARITY >> SHADOW_SCALE).
Commit: 0716d31649c44dd622cca6632b0c46a8dcafaa2d
https://github.com/llvm/llvm-project/commit/0716d31649c44dd622cca6632b0c46a8dcafaa2d
Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
Log Message:
-----------
[RISCV][NFC] Use maybe_unused instead of casting to void to fix unused variable warning. (#80651)
Commit: d53043fa8b2223a1c985e4c74794aa248b4c9e6b
https://github.com/llvm/llvm-project/commit/d53043fa8b2223a1c985e4c74794aa248b4c9e6b
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][Bazel] Adjust BUILD.bazel according to 0d091206dd656c2a9d31d6088a4aa6f9c2cc7156
Commit: 7d055af14b7dd7e782b87fb883205eda65e8bd44
https://github.com/llvm/llvm-project/commit/7d055af14b7dd7e782b87fb883205eda65e8bd44
Author: Joshua Cao <cao.joshua at yahoo.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/SymbolInterfaces.td
M mlir/test/Dialect/LLVMIR/global.mlir
M mlir/test/Dialect/Linalg/transform-op-replace.mlir
M mlir/test/Dialect/Transform/ops-invalid.mlir
M mlir/test/IR/invalid-func-op.mlir
M mlir/test/IR/region.mlir
M mlir/test/IR/traits.mlir
M mlir/test/Transforms/canonicalize-dce.mlir
M mlir/test/Transforms/canonicalize.mlir
M mlir/test/Transforms/constant-fold.mlir
M mlir/test/Transforms/cse.mlir
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/python/ir/value.py
Log Message:
-----------
[mlir][Symbol] Add verification that symbol's parent is a SymbolTable (#80590)
Following the discussion in
https://discourse.llvm.org/t/symboltable-and-symbol-parent-child-relationship/75446,
we should enforce that a symbol's immediate parent is a symbol table.
I changed some tests to pass the verification. In most cases, we can
wrap the func with a module, change the func to another op with regions
i.e. scf.if, or change the expected error message.
---------
Co-authored-by: Mehdi Amini <joker.eph at gmail.com>
Commit: 47a12cca442cb52c33fc592183998f3b7bdd5094
https://github.com/llvm/llvm-project/commit/47a12cca442cb52c33fc592183998f3b7bdd5094
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
Log Message:
-----------
CoverageMapping.cpp: s/MaxBitmapID/MaxBitmapIdx/ in getMaxBitmapSize()
Commit: 03881dc0a7695f4c499cc07042b8c59ad7b7335a
https://github.com/llvm/llvm-project/commit/03881dc0a7695f4c499cc07042b8c59ad7b7335a
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
A mlir/test/Target/Cpp/declare_func.mlir
Log Message:
-----------
[mlir][emitc] Add a `declare_func` operation (#80297)
This adds the `emitc.declare_func` operation that allows to emit the
declaration of an `emitc.func` at a specific location.
Commit: 38476b063f164995b85e47472e3c2e0a9c5f9075
https://github.com/llvm/llvm-project/commit/38476b063f164995b85e47472e3c2e0a9c5f9075
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A llvm/utils/count_running_jobs.py
Log Message:
-----------
[Github] Add script to count running jobs (#80250)
This patch adds a script to automatically query the number of running
jobs and print them to the terminal as this functionality isn't
available through the Github UI (unless you are a Github administrator).
Commit: 0b62218110f0945c6957e549f9fc1a2f2f87a604
https://github.com/llvm/llvm-project/commit/0b62218110f0945c6957e549f9fc1a2f2f87a604
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
Log Message:
-----------
Anonymize `MCDCRecordProcessor`
Commit: 933247d9d6a2aee66de49e84077ce116630e76cd
https://github.com/llvm/llvm-project/commit/933247d9d6a2aee66de49e84077ce116630e76cd
Author: Anton Sidorenko <anton.sidorenko at syntacore.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/sqrt.ll
Log Message:
-----------
[SimplifyLibCalls] Merge sqrt into the power of exp (#79146)
Under fast-math flags it's possible to convert `sqrt(exp(X)) `into
`exp(X * 0.5)`. I suppose that this transformation is always profitable.
This is similar to the optimization existing in GCC.
Commit: 984dd15d4da33337b2800d4776aa8ecc168b145e
https://github.com/llvm/llvm-project/commit/984dd15d4da33337b2800d4776aa8ecc168b145e
Author: j-jorge <j-jorge at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
M clang/lib/Format/Format.cpp
M clang/lib/Tooling/Inclusions/HeaderIncludes.cpp
M clang/lib/Tooling/Inclusions/IncludeStyle.cpp
M clang/unittests/Format/SortIncludesTest.cpp
Log Message:
-----------
[clang-format] Add MainIncludeChar option. (#78752)
Resolves #27008, #39735, #53013, #63619.
Hello, this PR adds the MainIncludeChar option to clang-format, allowing
to select which include syntax must be considered when searching for the
main header: quotes (`#include "foo.hpp"`, the default), brackets
(`#include <foo.hpp>`), or both.
The lack of support for brackets has been reported many times, see the
linked issues, so I am pretty sure there is a need for it :)
A short note about why I did not implement a regex approach as discussed
in #53013: while a regex would have allowed many extra ways to describe
the main header, the bug descriptions listed above suggest a very simple
need: support brackets for the main header. This PR answers this needs
in a quite simple way, with a very simple style option. IMHO the feature
space covered by the regex (again, for which there is no demand :)) can
be implemented latter, in addition to the proposed option.
The PR also includes tests for the option with and without grouped
includes.
Commit: edfc21a5759e9f5f5025885da9b0b879204aff22
https://github.com/llvm/llvm-project/commit/edfc21a5759e9f5f5025885da9b0b879204aff22
Author: vigbalu <70995650+vigbalu at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M openmp/runtime/src/include/omp-tools.h.var
Log Message:
-----------
[OMPD] Runtime Entry Point functions for OMPD in libomp.so need C linkage as per standard. (#79246)
Adding extern "C" to all the entry point functions to make sure that
these functions are not mangled.
Commit: 42b5b720caf62e0710b9c1e32e894d8606106a19
https://github.com/llvm/llvm-project/commit/42b5b720caf62e0710b9c1e32e894d8606106a19
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll
Log Message:
-----------
AMDGPU/GlobalISel: Fix not running -global-isel in global isel test
Commit: 0473e322f67228a9c2dbf462357e5b4a2b3799be
https://github.com/llvm/llvm-project/commit/0473e322f67228a9c2dbf462357e5b4a2b3799be
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
Log Message:
-----------
[mlir][ArmSME] Add rewrite to lift illegal vector.transposes to memory (#80170)
When unrolling the reduction dimension of something like a matmul for
SME, you can end up with transposed reads of illegal types, like so:
```mlir
%illegalRead = vector.transfer_read %memref[%a, %b]
: memref<?x?xf32>, vector<[8]x4xf32>
%legalType = vector.transpose %illegalRead, [1, 0]
: vector<[8]x4xf32> to vector<4x[8]xf32>
```
Here the `vector<[8]x4xf32>` is an illegal type, there's no way to lower
a scalable vector of fixed vectors. However, as the final type
`vector<4x[8]xf32>` is legal, we can instead lift the transpose to
memory (producing a strided memref), and eliminate all the illegal
types. This is shown below.
```mlir
%readSubview = memref.subview %memref[%a, %b] [%c8_vscale, %c4] [%c1, %c1]
: memref<?x?xf32> to memref<?x?xf32>
%transpose = memref.transpose %readSubview (d0, d1) -> (d1, d0)
: memref<?x?xf32> to memref<?x?xf32>
%legalType = vector.transfer_read %transpose[%c0, %c0]
: memref<?x?xf32>, vector<4x[8]xf32>
```
Commit: 3eb1e6d8e930f5aff17b8d6bcc160f5bbf8cabc7
https://github.com/llvm/llvm-project/commit/3eb1e6d8e930f5aff17b8d6bcc160f5bbf8cabc7
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/src/errno/libc_errno.cpp
M libc/src/errno/libc_errno.h
M libc/test/IntegrationTest/test.h
M libc/test/UnitTest/ErrnoSetterMatcher.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/UnitTest/FuchsiaTest.h
M libc/test/UnitTest/LibcTest.h
M libc/test/integration/src/pthread/pthread_create_test.cpp
M libc/test/integration/src/pthread/pthread_join_test.cpp
M libc/test/integration/src/unistd/getcwd_test.cpp
M libc/test/src/__support/str_to_double_test.cpp
M libc/test/src/__support/str_to_float_test.cpp
M libc/test/src/__support/str_to_fp_test.h
M libc/test/src/dirent/dirent_test.cpp
M libc/test/src/errno/errno_test.cpp
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/acosf_test.cpp
M libc/test/src/math/acoshf_test.cpp
M libc/test/src/math/asinf_test.cpp
M libc/test/src/math/asinhf_test.cpp
M libc/test/src/math/atanf_test.cpp
M libc/test/src/math/atanhf_test.cpp
M libc/test/src/math/cosf_test.cpp
M libc/test/src/math/coshf_test.cpp
M libc/test/src/math/exp10_test.cpp
M libc/test/src/math/exp10f_test.cpp
M libc/test/src/math/exp2_test.cpp
M libc/test/src/math/exp2f_test.cpp
M libc/test/src/math/exp_test.cpp
M libc/test/src/math/expf_test.cpp
M libc/test/src/math/expm1_test.cpp
M libc/test/src/math/expm1f_test.cpp
M libc/test/src/math/log10_test.cpp
M libc/test/src/math/log1p_test.cpp
M libc/test/src/math/log1pf_test.cpp
M libc/test/src/math/log2_test.cpp
M libc/test/src/math/log2f_test.cpp
M libc/test/src/math/log_test.cpp
M libc/test/src/math/powf_test.cpp
M libc/test/src/math/sincosf_test.cpp
M libc/test/src/math/sinf_test.cpp
M libc/test/src/math/sinhf_test.cpp
M libc/test/src/math/smoke/RoundToIntegerTest.h
M libc/test/src/math/smoke/acosf_test.cpp
M libc/test/src/math/smoke/acoshf_test.cpp
M libc/test/src/math/smoke/asinf_test.cpp
M libc/test/src/math/smoke/asinhf_test.cpp
M libc/test/src/math/smoke/atanf_test.cpp
M libc/test/src/math/smoke/atanhf_test.cpp
M libc/test/src/math/smoke/cosf_test.cpp
M libc/test/src/math/smoke/coshf_test.cpp
M libc/test/src/math/smoke/exp10f_test.cpp
M libc/test/src/math/smoke/exp2f_test.cpp
M libc/test/src/math/smoke/expf_test.cpp
M libc/test/src/math/smoke/expm1f_test.cpp
M libc/test/src/math/smoke/sincosf_test.cpp
M libc/test/src/math/smoke/sinf_test.cpp
M libc/test/src/math/smoke/sinhf_test.cpp
M libc/test/src/math/smoke/tanf_test.cpp
M libc/test/src/math/smoke/tanhf_test.cpp
M libc/test/src/math/tanf_test.cpp
M libc/test/src/math/tanhf_test.cpp
M libc/test/src/sched/affinity_test.cpp
M libc/test/src/sched/cpu_count_test.cpp
M libc/test/src/sched/get_priority_test.cpp
M libc/test/src/sched/param_and_scheduler_test.cpp
M libc/test/src/sched/sched_rr_get_interval_test.cpp
M libc/test/src/sched/yield_test.cpp
M libc/test/src/signal/sigaltstack_test.cpp
M libc/test/src/signal/signal_test.cpp
M libc/test/src/signal/sigprocmask_test.cpp
M libc/test/src/stdio/fgetc_test.cpp
M libc/test/src/stdio/fgetc_unlocked_test.cpp
M libc/test/src/stdio/fgets_test.cpp
M libc/test/src/stdio/fileop_test.cpp
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdio/setvbuf_test.cpp
M libc/test/src/stdio/unlocked_fileop_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/stdlib/atof_test.cpp
M libc/test/src/stdlib/strtod_test.cpp
M libc/test/src/stdlib/strtof_test.cpp
M libc/test/src/stdlib/strtoint32_test.cpp
M libc/test/src/stdlib/strtoint64_test.cpp
M libc/test/src/stdlib/strtold_test.cpp
M libc/test/src/string/strdup_test.cpp
M libc/test/src/sys/mman/linux/madvise_test.cpp
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mmap_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/prctl/linux/prctl_test.cpp
M libc/test/src/sys/random/linux/getrandom_test.cpp
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/sys/select/select_ui_test.cpp
M libc/test/src/sys/sendfile/sendfile_test.cpp
M libc/test/src/sys/stat/chmod_test.cpp
M libc/test/src/sys/stat/fchmod_test.cpp
M libc/test/src/sys/stat/fchmodat_test.cpp
M libc/test/src/sys/stat/fstat_test.cpp
M libc/test/src/sys/stat/lstat_test.cpp
M libc/test/src/sys/stat/stat_test.cpp
M libc/test/src/termios/termios_test.cpp
M libc/test/src/time/gmtime_test.cpp
M libc/test/src/time/nanosleep_test.cpp
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
Log Message:
-----------
[libc] Move libc_errno inside of LIBC_NAMESPACE (#80774)
Having libc_errno outside of the namespace causes versioning issues when
trying to link the tests against LLVM-libc. Most of this patch is just
moving libc_errno inside the namespace in tests. This isn't necessary in
the function implementations since those are already inside the
namespace.
Commit: 6ec926df739b0f0ac0d970b0181d62ad6e564784
https://github.com/llvm/llvm-project/commit/6ec926df739b0f0ac0d970b0181d62ad6e564784
Author: wangpc <wangpengcheng.pp at bytedance.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-mca.rst
Log Message:
-----------
[llvm-mca] Fix doc error
Commit: 168002ece26269a4a6fcfce96ac8e66f6414c9e7
https://github.com/llvm/llvm-project/commit/168002ece26269a4a6fcfce96ac8e66f6414c9e7
Author: Nilanjana Basu <n_basu at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/Transforms/LoopDistribute/basic-with-memchecks.ll
Log Message:
-----------
[Tests][LoopDistribute] Fixes failing unit test (#80809)
Removed target-triple in target-independent test case to fix failing test caused by https://github.com/llvm/llvm-project/pull/67725.
Commit: c9fd738388810aeaac99454989a150eb29f08521
https://github.com/llvm/llvm-project/commit/c9fd738388810aeaac99454989a150eb29f08521
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
A llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
Log Message:
-----------
[CodeGen] Port DeadMachineInstructionElim to new pass manager (#80582)
A simple enough op pass so we can test standard instrumentations in
future.
Commit: c6b5ea339d9f257b64f4ca468e447f0e29a909a4
https://github.com/llvm/llvm-project/commit/c6b5ea339d9f257b64f4ca468e447f0e29a909a4
Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
R llvm/test/Transforms/InstCombine/tan-nofastmath.ll
R llvm/test/Transforms/InstCombine/tan.ll
A llvm/test/Transforms/InstCombine/trig.ll
Log Message:
-----------
[Transforms] Expand optimizeTan to fold more inverse trig pairs (#77799)
optimizeTan has been renamed to optimizeTrigInversionPairs as a result.
Sadly, this is not mathematically true that all inverse pairs fold to x.
For example, asin(sin(x)) does not fold to x if x is over 2pi.
Commit: 35904ec4e1fca8d26c37a7f6aafd6c32f0ef9b09
https://github.com/llvm/llvm-project/commit/35904ec4e1fca8d26c37a7f6aafd6c32f0ef9b09
Author: Sjoerd Meijer <smeijer at nvidia.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
Log Message:
-----------
[AArch64] MI Scheduler STP combine (#80188)
Add opcodes for different store instructions to the target hook that can
enable more STP pairs. This is split off from the patch that does the
same for some load instructions (#79003).
Patch co-authored by Cameron McInally.
Commit: 2f7d9abf7c2ba1e697d46ffca0bf2f5a2bf8ba0c
https://github.com/llvm/llvm-project/commit/2f7d9abf7c2ba1e697d46ffca0bf2f5a2bf8ba0c
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
Log Message:
-----------
[mlir][ArmSME][nfc] Fix broken doc links to fmopa_2way op
Commit: bc569f6eb3848361ae637de0a873e1c442958a71
https://github.com/llvm/llvm-project/commit/bc569f6eb3848361ae637de0a873e1c442958a71
Author: Luke Lau <luke at igalia.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Log Message:
-----------
[RISCV] Add test case for shufflevector that gets scalarized. NFC
This shufflevector gets scalarized into a build_vector of extract_vector_elts
because the output type doesn't match the input vector type.
Normally this is combined back into a vector_shuffle in DAGCombine, but this
one fails because we don't consider a extract_subvector to be cheap,
specifically because it's at an index > 31.
This should be canonicalized back into a vector_shuffle at some point so we can
lower it as a vrgather.vv.
Commit: 726cf604569d893d3bcb2c50d7905a95db92ddfd
https://github.com/llvm/llvm-project/commit/726cf604569d893d3bcb2c50d7905a95db92ddfd
Author: wangpc <wangpengcheng.pp at bytedance.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-mca.rst
Log Message:
-----------
[llvm-mca] Add an empty line to fix doc error
Commit: 292d9e869fcfc2ece694848db4022b0b939847e3
https://github.com/llvm/llvm-project/commit/292d9e869fcfc2ece694848db4022b0b939847e3
Author: Qiu Chaofan <qiucofan at cn.ibm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
A llvm/test/CodeGen/PowerPC/pr59074.ll
Log Message:
-----------
[PowerPC] Mask constant operands in ValueBit tracking (#67653)
In IR or C code, shift amount larger than value size is undefined
behavior. But in practice, backend lowering for shift_parts produces
add/sub of shift amounts, thus constant shift amounts might be
negative or larger than value size, which depends on ISA definition.
PowerPC ISA says, the lowest 7 bits (6 bits for 32-bit instruction)
will be taken, and if the highest among them is 1, result will be
zero, otherwise the low 6 bits (or 5 on 32-bit) are used as shift
amount.
This commit emulates the behavior and avoids array overflow in bit
permutation's value bits calculator.
Commit: 6dfb31adf6ca17d05c3832f1e43252a4c0c9f2af
https://github.com/llvm/llvm-project/commit/6dfb31adf6ca17d05c3832f1e43252a4c0c9f2af
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp][NFC] Simplify test case
By checking using verify={ref,expected},both.
Commit: 3d186a77cf1aa979014a6443cb423a633c167d9f
https://github.com/llvm/llvm-project/commit/3d186a77cf1aa979014a6443cb423a633c167d9f
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/include/clang/Basic/arm_sme.td
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c
Log Message:
-----------
[Clang][AArch64] Fix some target guards and remove +sve from tests. (#80681)
The TargetGuard fields for 'svldr[_vnum]_za' and 'svstr[_vnum]_za' were
incorrectly set to `+sve` instead of `+sme`. This means that compiling
code that uses these intrinsics requires compiling for both `+sve` as
well as `+sme`.
This PR also fixes the target guards for the `svadd` and `svsub`
builtins that are enabled under `+sme2,+sme-i16i64` and
`+sme2,+sme-f64f64`, as it initially did the following:
```
let TargetGuard = "+sme2" in {
let TargetGuard = "+sme-i16i64" in {
// Builtins defined here will be predicated only by
// '+sme-i16i64', and not '+sme2,+sme-i16i64'.
}
}
```
This PR also removes `-target-feature +sve` from all the SME tests, to
ensure that the SME features are sufficient to build the tests.
Commit: c302909760d67a6d149fece3b79c90e47a25ba4d
https://github.com/llvm/llvm-project/commit/c302909760d67a6d149fece3b79c90e47a25ba4d
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/sink-common-code.ll
Log Message:
-----------
[RemoveDIs] Fix DPValue hoisting in hoistSuccIdenticalTerminatorToSwitchOrIf (#80822)
Follow up to #79476 - that patch added a call to hoistLockstepIdenticalDPValues
which hoists identical DPValues in lockstep, matching dbg intrinsic hoisting
behaviour. The code deleted in this patch, which unconditionally hoists
DPValues, should have been deleted in that patch.
Update test with --try-experimental-debuginfo-iterators to check the behaviour.
Follow up to #79476 - that change introduces a call to
hoistLockstepIdenticalDPValues.
Commit: 7f292b8fb12aed094b8422aad9fcb7b2907c54c9
https://github.com/llvm/llvm-project/commit/7f292b8fb12aed094b8422aad9fcb7b2907c54c9
Author: Rin Dobrescu <irina.dobrescu at arm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
A llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll
Log Message:
-----------
[AArch64] Convert concat(uhadd(a,b), uhadd(c,d)) to uhadd(concat(a,c), concat(b,d)) (#80674)
We can convert concat(v4i16 uhadd(a,b), v4i16 uhadd(c,d)) to v8i16
uhadd(concat(a,c), concat(b,d)), which can lead to further
simplifications.
Commit: 8924a9ffcb3696288cca3334cd60a099d3fcda79
https://github.com/llvm/llvm-project/commit/8924a9ffcb3696288cca3334cd60a099d3fcda79
Author: Simon Camphausen <simon.camphausen at iml.fraunhofer.de>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
Log Message:
-----------
[mlir][EmitC] Remove unreachable code and fix Windows build warning (#80677)
Commit: de8ba2f60334dc44f6906a0722435db41564b421
https://github.com/llvm/llvm-project/commit/de8ba2f60334dc44f6906a0722435db41564b421
Author: Francesco Petrogalli <francesco.petrogalli at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
Log Message:
-----------
[CodeGen] Update comments for ValueType.td. [NFC] (#80670)
The enums needed by the file MachineValueType.h are auto-generated since commit
ddaf085e7bcb903d5ae1cafc4667b8c3d302897e
Commit: 82950a695ddbd92beb07bf58b48067a1f67d57e3
https://github.com/llvm/llvm-project/commit/82950a695ddbd92beb07bf58b48067a1f67d57e3
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Pointer.h
M clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c
M clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c
M clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c
Log Message:
-----------
[clang][Interp] Protect ArrayElemPtr ops from dummy pointers
Change the semantics of Pointer::isDummy() to check for a null
Pointee and returnd false in that case. Then call CheckDummy()
in ArrayElemPtr{,Pop} to protect those ops from operating on
dummy pointers and enable a few tests in test/Sema/ that now
work with the new constant interpreter.
Commit: ccc77f1194f894db8ec93131124a7a2848e3e079
https://github.com/llvm/llvm-project/commit/ccc77f1194f894db8ec93131124a7a2848e3e079
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Pointer.h
Log Message:
-----------
[clang][Interp][NFC] Fix comment typos
Commit: cf94e0082e5e0a9be43a69d9fae588bc2aafab91
https://github.com/llvm/llvm-project/commit/cf94e0082e5e0a9be43a69d9fae588bc2aafab91
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for 0473e322f67228a9c2dbf462357e5b4a2b3799be
Commit: b8cdc2638e4c067fd633b345aba75fee81c4054f
https://github.com/llvm/llvm-project/commit/b8cdc2638e4c067fd633b345aba75fee81c4054f
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[DAG] visitCTPOP - if only the upper half of the ctpop operand is zero then see if its profitable to only count the lower half. (#80473)
Commit: 29fa64f845df6b1ba3f562564ab97a07aa7077ee
https://github.com/llvm/llvm-project/commit/29fa64f845df6b1ba3f562564ab97a07aa7077ee
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M flang/lib/Lower/OpenMP.cpp
Log Message:
-----------
[flang][OpenMP][NFC] Outline `genOpWithBody` & `createBodyOfOp` args (#80817)
This PR outlines the arguments of the open CodeGen functions into 2
separate structs. This was, in part, motivated by the delayed
privatization WIP #79862 where we had to extend the signatures of both
functions containing quite a bit of default values (`nullptr`, `false`).
This PR does not add any new arguments yet though, just outlines the
existing ones.
Commit: 2e3de997ab7cd8728c484bc39e24fecbb97dfae8
https://github.com/llvm/llvm-project/commit/2e3de997ab7cd8728c484bc39e24fecbb97dfae8
Author: David Green <david.green at arm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/test/CodeGen/AArch64/setcc_knownbits.ll
M llvm/test/CodeGen/WebAssembly/xor_reassociate.ll
M llvm/test/CodeGen/X86/lzcnt-cmp.ll
M llvm/test/CodeGen/X86/umul_fix_sat.ll
M llvm/test/CodeGen/X86/xor.ll
Log Message:
-----------
[DAG] Generalize setcc(setcc) fold to use known bits.
If we have a `SETCC (SETCC), 0, NE` and ZeroOrOneBooleanContent, we can remove
the outer setcc as it will produce the same value as the inner. This can be
generalized to anything where the top bits are known to be 0, as the value will
remain as 1 or 0.
Commit: a2e5287d5a499521aaf093f812cbedcbbc2a4bc8
https://github.com/llvm/llvm-project/commit/a2e5287d5a499521aaf093f812cbedcbbc2a4bc8
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lld/test/COFF/def-export-cpp.s
M lld/test/COFF/def-export-stdcall.s
M lld/test/COFF/dllexport.s
M llvm/include/llvm/Object/COFFImportFile.h
M llvm/lib/Object/COFFImportFile.cpp
M llvm/test/tools/llvm-dlltool/coff-decorated.def
M llvm/test/tools/llvm-dlltool/coff-exports.def
M llvm/test/tools/llvm-dlltool/coff-noname.def
M llvm/test/tools/llvm-dlltool/no-leading-underscore.def
M llvm/test/tools/llvm-lib/arm64ec-implib.test
M llvm/test/tools/llvm-readobj/COFF/file-headers.test
M llvm/tools/llvm-readobj/COFFImportDumper.cpp
Log Message:
-----------
[llvm-readobj][Object][COFF] Print COFF import library symbol export name. (#78769)
getExportName implementation is based on lld-link. In its current form,
it's mostly about convenience, but it will be more useful for EXPORTAS
support, for which export name is not possible to deduce from other
printed properties.
Commit: a18e92d020b895b712175a3b13a3d021608115a7
https://github.com/llvm/llvm-project/commit/a18e92d020b895b712175a3b13a3d021608115a7
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaExpr.cpp
M clang/test/Sema/warn-int-in-bool-context.c
Log Message:
-----------
[clang] Fix unexpected `-Wconstant-logical-operand` in C23 (#80724)
C23 has `bool`, but logical operators still return int. Check that
we're not in C to avoid false-positive -Wconstant-logical-operand.
Fixes https://github.com/llvm/llvm-project/issues/64356
Commit: e6866955f637634f439f7004a38be32b1c5185e2
https://github.com/llvm/llvm-project/commit/e6866955f637634f439f7004a38be32b1c5185e2
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
M flang/test/Semantics/OpenMP/copyprivate03.f90
Log Message:
-----------
[flang][OpenMP] Accept firstprivate vars in copyprivate (#80467)
This is patch 1 of 4, to add support for COPYPRIVATE.
Original PR: https://github.com/llvm/llvm-project/pull/73128
Commit: 48927e9592e8bb70f85ff6431c7bf514fe5d1c07
https://github.com/llvm/llvm-project/commit/48927e9592e8bb70f85ff6431c7bf514fe5d1c07
Author: Leandro Lupori <leandro.lupori at linaro.org>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M flang/lib/Lower/OpenMP.cpp
A flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90
Log Message:
-----------
[flang][OpenMP] Fix privatization of threadprivate common block (#77821)
In some cases, when privatizing a threadprivate common block, the
original symbol will correspond to the common block, instead of
its threadprivate version. This can happen, for instance, with a
common block, declared in a separate module, used by a parent
procedure and privatized in its child procedure. In this case,
symbol lookup won't find a symbol in the parent procedure, but
only in the module where the common block was defined.
Fixes https://github.com/llvm/llvm-project/issues/65028
Commit: b06568fa623c746d40638137504d52e19911bf32
https://github.com/llvm/llvm-project/commit/b06568fa623c746d40638137504d52e19911bf32
Author: Kevin P. Neal <kevin.neal at sas.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/remove-attributes-strictfp.ll
Log Message:
-----------
[FPEnv][llvm-reduce] Correct strictfp test.
Correct llvm-reduce strictfp test to follow the rules documented in the
LangRef:
https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics
This test needed the strictfp attribute added to a function call.
Note that attributes of intrinsics cannot be changed in declarations,
but attributes can be changed in call sites. Thus the changes to the
declarations. And the constrained intrinsics have strictfp attributes
by default.
Test changes verified with D146845.
Commit: 026f3c1bbc1fbd9d7c25fc3a97b1c29d7ae7e2b5
https://github.com/llvm/llvm-project/commit/026f3c1bbc1fbd9d7c25fc3a97b1c29d7ae7e2b5
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/src/__support/GPU/amdgpu/utils.h
M libc/src/math/gpu/vendor/amdgpu/platform.h
Log Message:
-----------
[libc] Remove CPU dependent AMDGPU instructions (#80707)
Summary:
Some recent changes allowed us to remove target level divergence one
these instructions. This patch removes the wavefront dependent
divergence for the ballot and thread ID functions, as well as the clock.
The changes to the "Vendor" library simply disables target specific
optimizations in the implementation. This should be removed in its
entirety when the LLVM `libm` is sufficiently implemented.
The remaining areas of divergence is only the RPC packet size and the
fixed frequency counter.
Commit: ddc493579fa1b7eed058c7ed8a5a6b5755a31953
https://github.com/llvm/llvm-project/commit/ddc493579fa1b7eed058c7ed8a5a6b5755a31953
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/IR/Instruction.h
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Don't allocate one DPMarker per instruction (#79345)
This is an optimisation patch that shouldn't have any functional effect.
There's no need for all instructions to have a DPMarker attached to them,
because not all instructions have adjacent DPValues (aka dbg.values).
This patch inserts the appropriate conditionals into functions like
BasicBlock::spliceDebugInfo to ensure we don't step on a null pointer when
there isn't a DPMarker allocated. Mostly, this is a case of calling
createMarker occasionally, which will create a marker on an instruction
if there isn't one there already.
Also folded into this is the use of adoptDbgValues, which is a natural
extension: if we have a sequence of instructions and debug records:
%foo = add i32 %0,...
# dbg_value { %foo, ...
# dbg_value { %bar, ...
%baz = add i32 %...
%qux = add i32 %...
and delete, for example, the %baz instruction, then the dbg_value records
would naturally be transferred onto the %qux instruction (they "fall down"
onto it). There's no point in creating and splicing DPMarkers in the case
shown when %qux doesn't have a DPMarker already, we can instead just change
the owner of %baz's DPMarker from %baz to %qux. This also avoids calling
setParent on every DPValue.
Update LoopRotationUtils: it was relying on each instruction having it's
own distinct end(), so that we could express ranges and lack-of-ranges.
That's no longer true though: so switch to storing the range of DPValues on
the next instruction when we want to consider it's range next time around
the loop (see the nearby comment).
Commit: 54c29e01c2bf6980bf999496e221f214e521d3ff
https://github.com/llvm/llvm-project/commit/54c29e01c2bf6980bf999496e221f214e521d3ff
Author: ostannard <oliver.stannard at arm.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/test/MC/AArch64/no-fp-errors.s
Log Message:
-----------
[AArch64] Set predicates for FP/SIMD InstAliases (#79033)
These are aliases for instructions which are are only available when the
fp-armv8 or neon features are enabled, so their predicates should be set
appropriately.
Commit: 26db3c3b72d3c915ad296a5a5313210bde8ce3e1
https://github.com/llvm/llvm-project/commit/26db3c3b72d3c915ad296a5a5313210bde8ce3e1
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/cxx20.cpp
M clang/test/SemaCXX/cxx11-default-member-initializers.cpp
Log Message:
-----------
[clang][Interp] Handle discarding ConstantExprs
Assume no side-effects in the presence of a cashed result in the form
of an APValue. This is also what the current interpreter does.
Commit: 83eb8126dd0c7457d43f5e6bce8911a528f93af9
https://github.com/llvm/llvm-project/commit/83eb8126dd0c7457d43f5e6bce8911a528f93af9
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/src/math/gpu/vendor/amdgpu/platform.h
Log Message:
-----------
[libc] Fix accidentally deleted braces after change
Summary:
Oops.
Commit: f89fe08d770d912bc1e7b9b52c1859a44abea69a
https://github.com/llvm/llvm-project/commit/f89fe08d770d912bc1e7b9b52c1859a44abea69a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/test/Transforms/LowerMatrixIntrinsics/dot-product-int.ll
Log Message:
-----------
[Matrix] Convert column-vector ops feeding dot product to row-vectors. (#72647)
Generalize the logic used to convert column-vector ops to row-vectors to
support converting chains of operations.
A potential next step is to further generalize this to convert
column-vector ops to row-vector ops in general, not just for operands of
dot products. Dot-product handling would then be driven by the general
conversion, rather than the other way around.
PR: https://github.com/llvm/llvm-project/pull/72647
Commit: ffd79b3312cea51c0787aad479ce285771470397
https://github.com/llvm/llvm-project/commit/ffd79b3312cea51c0787aad479ce285771470397
Author: Sergey Kachkov <109674256+skachkov-sc at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/test/Transforms/LoopUnroll/AMDGPU/unroll-cost-addrspacecast.ll
A llvm/test/Transforms/LoopUnroll/RISCV/unroll-Os.ll
Log Message:
-----------
[LoopUnroll] Consider simplified operands while retrieving TTI instruction cost (#70929)
Get more precise cost of instruction after LoopUnroll considering that
some operands of it can be simplified, e.g. induction variable will be
replaced by constant after full unrolling.
Commit: 62c352e13c145b5606ace88ecbe9164ff011b5cf
https://github.com/llvm/llvm-project/commit/62c352e13c145b5606ace88ecbe9164ff011b5cf
Author: Zahira Ammarguellat <zahira.ammarguellat at intel.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticDocs.td
M clang/include/clang/Lex/Preprocessor.h
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp
M clang/test/Sema/warn-infinity-nan-disabled-win.cpp
Log Message:
-----------
[CLANG] Fix INF/NAN warning. (#80290)
In https://github.com/llvm/llvm-project/pull/76873 a warning was added
when the macros INFINITY and NAN are used in binary expressions when
-menable-no-nans or -menable-no-infs are used. If the user uses an
option that nullifies these two options, the warning will still be
generated. This patch adds an additional information to the warning
comment to let the user know about this. It also suppresses the warning
when #ifdef INFINITY, #ifdef NAN, #ifdef NAN or #ifndef NAN are used in
the code.
Commit: d5a3de4aeef4f4f1c52692533ddb9fdf45aef9d3
https://github.com/llvm/llvm-project/commit/d5a3de4aeef4f4f1c52692533ddb9fdf45aef9d3
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/CMakeLists.txt
A libc/src/stdbit/stdc_trailing_zeros_uc.cpp
A libc/src/stdbit/stdc_trailing_zeros_uc.h
A libc/src/stdbit/stdc_trailing_zeros_ui.cpp
A libc/src/stdbit/stdc_trailing_zeros_ui.h
A libc/src/stdbit/stdc_trailing_zeros_ul.cpp
A libc/src/stdbit/stdc_trailing_zeros_ul.h
A libc/src/stdbit/stdc_trailing_zeros_ull.cpp
A libc/src/stdbit/stdc_trailing_zeros_ull.h
A libc/src/stdbit/stdc_trailing_zeros_us.cpp
A libc/src/stdbit/stdc_trailing_zeros_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/CMakeLists.txt
A libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp
Log Message:
-----------
[libc][stdbit] implement stdc_trailing_zeros (C23) (#80344)
Commit: ca1da36aec963c5504ae7ae2e834b37856c476db
https://github.com/llvm/llvm-project/commit/ca1da36aec963c5504ae7ae2e834b37856c476db
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/include/CMakeLists.txt
M libc/include/inttypes.h.def
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/inttypes-macros.h
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/sprintf_test.cpp
Log Message:
-----------
[libc] add inttypes macros (#80726)
Standard file:
https://pubs.opengroup.org/onlinepubs/9699919799.2018edition/
Notice that we are not quite the same as other implementations:
1. MUSL: https://github.com/bminor/musl/blob/master/include/inttypes.h
2. GLIBC:
https://github.com/bminor/glibc/blob/bbd248ac0d75efdef8fe61ea69b1fb25fb95b6e7/stdlib/inttypes.h#L57
3. CheriBSD:
https://github.com/CTSRD-CHERI/cheribsd/blob/698d1636dd1fe2322e5bc7029e415928c80b76b1/sys/arm64/include/_inttypes.h
fixes #80186
Commit: 364f781344e11d6a781ebdd0a4d9689bc9c51cfb
https://github.com/llvm/llvm-project/commit/364f781344e11d6a781ebdd0a4d9689bc9c51cfb
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
Log Message:
-----------
[GlobalIsel] Combine logic of icmps (#77855)
Inspired by InstCombinerImpl::foldAndOrOfICmpsUsingRanges with some
adaptations to MIR.
Commit: b1acb7a315e903ee340a33dbc9b2b61b0450bb67
https://github.com/llvm/llvm-project/commit/b1acb7a315e903ee340a33dbc9b2b61b0450bb67
Author: stephenpeckham <118857872+stephenpeckham at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/XCOFF.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/XCOFFObjectWriter.cpp
M llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll
M llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll
M llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll
M llvm/test/CodeGen/PowerPC/aix-extern-weak.ll
M llvm/test/CodeGen/PowerPC/aix-extern.ll
M llvm/test/CodeGen/PowerPC/aix-filename-c.ll
M llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll
M llvm/test/CodeGen/PowerPC/aix-filename-f.ll
M llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll
M llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll
M llvm/test/CodeGen/PowerPC/aix-overflow-toc.py
M llvm/test/CodeGen/PowerPC/aix-relro-section.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll
M llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll
M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll
M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll
M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll
M llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll
M llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll
M llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll
M llvm/test/CodeGen/PowerPC/aix-weak.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll
M llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll
M llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll
M llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll
M llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll
M llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll
M llvm/test/CodeGen/PowerPC/toc-data-const.ll
M llvm/test/MC/PowerPC/aix-file-symbols.s
M llvm/test/tools/llvm-objdump/XCOFF/symbol-table.test
Log Message:
-----------
[XCOFF] Add compiler version to an auxiliary symbol table entry (#80162)
C_FILE symbols. To match the behavior of the assembler and the legacy
compiler, this includes using the generic ".file" name for the C_FILE
symbol and generating the actual file name in an auxiliary entry.
Commit: d4c5acac99e83ffa12d2d720c9e502a181cbd7ea
https://github.com/llvm/llvm-project/commit/d4c5acac99e83ffa12d2d720c9e502a181cbd7ea
Author: Fraser Cormack <fraser at codeplay.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
Log Message:
-----------
[ExecutionEngine] Fix a couple of typos (NFC)
Commit: d6c7253d32e4bdff619c39708170f1c1fa01ff95
https://github.com/llvm/llvm-project/commit/d6c7253d32e4bdff619c39708170f1c1fa01ff95
Author: David Stuttard <david.stuttard at amd.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
Log Message:
-----------
[AMDGPU] Add pal metadata 3.0 support to callable pal funcs (#67104)
PAL Metadata 3.0 introduces an explicit structure in metadata for the
programmable registers written out by the compiler backend.
The previous approach used opaque registers which can change between different
architectures and required encoding the bitfield information in the backend,
which may change between versions.
This change is an extension the previously added support - which only handled
entry functions. This adds support for all functions.
The change also includes some re-factoring to separate common code.
Commit: 40fd17a90d4dcfb4bada663d73111a43c4c6ccb1
https://github.com/llvm/llvm-project/commit/40fd17a90d4dcfb4bada663d73111a43c4c6ccb1
Author: hlivin01 <110549819+hlivin01 at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/include/clang/Basic/arm_neon.td
M clang/test/CodeGen/aarch64-neon-intrinsics.c
Log Message:
-----------
[ARM][AARCH64][NEON]: Wrong return type of NEON intrinsic vqrshrunh_n_s16, vqrshruns_n_s32, and vqrshrund_n_s64 in arm_neon.h (#80819)
* fixes https://github.com/llvm/llvm-project/issues/71751
* changed return types in the table gen file responsible for generation
of the problematic intrinsics
* this is to ensure that the return type for the functions is the same
as specified in the Arm Developer Documentation and avoid casting
bugs
(https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)
* updated lit tests to reflect the change in return type, worth noting
that LLVM does not seems to differentiate signed and unsigned ints in
the IR, hence the change in type cannot be checked in IR as far as I am
aware
Commit: 9ea34be3e4c9deeabfc21cced1acb7f9593ffe93
https://github.com/llvm/llvm-project/commit/9ea34be3e4c9deeabfc21cced1acb7f9593ffe93
Author: Vinayak Dev <104419489+vinayakdsci at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/MC/MCObjectStreamer.cpp
Log Message:
-----------
[MC]: Fix typo in MCObjectStreamer.cpp (#80856)
Fixes a typo in llvm/lib/MC/MCObjectStreamer.cpp introduced in #80162
Commit: e5638c5a00682243b1ee012d7dd8292aa221dff8
https://github.com/llvm/llvm-project/commit/e5638c5a00682243b1ee012d7dd8292aa221dff8
Author: choikwa <5455710+choikwa at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll
M llvm/test/CodeGen/AMDGPU/bypass-div.ll
M llvm/test/CodeGen/AMDGPU/sdiv64.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
Log Message:
-----------
[AMDGPU] Use correct number of bits needed for div/rem shrinking (#80622)
There was an error where dividend of type i64 and actual used number of
bits of 32 fell into path that assumes only 24 bits being used. Check
that AtLeast field is used correctly when using computeNumSignBits and
add necessary extend/trunc for 32 bits path.
Regolden and update testcases.
@jrbyrnes @bcahoon @arsenm @rampitec
Commit: 36e8db7d8c9183c66363e76517772b074b4f53be
https://github.com/llvm/llvm-project/commit/36e8db7d8c9183c66363e76517772b074b4f53be
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Extract main part of GetGEPCostDiff to a function, NFC.
Commit: 388548359f5049b88a9738d8a9e67691503fbdef
https://github.com/llvm/llvm-project/commit/388548359f5049b88a9738d8a9e67691503fbdef
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lldb/unittests/TestingSupport/TestUtilities.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
Log Message:
-----------
[lldb][unittest] Add call_once flag to initialize debugger (#80786)
I tried adding a new unit test to the core test
suite (https://github.com/llvm/llvm-project/pull/79533) but it broke the
test suite on AArch64 Linux due to hitting an assertion for calling
`Debugger::Initialize` more than once. When the unit test suite is
invoked as a standalone binary the test suite state is shared, and
`Debugger::Initialize` gets called in `DiagnosticEventTest.cpp` before
being called in `ProgressReportTest.cpp`.
`DiagnosticEventTest.cpp` uses a call_once flag to initialize the
debugger but it's local to that test. This commit adds a once_flag to
`TestUtilities` so that `Debugger::Initialize` can be called once by the
tests that use it.
Commit: 299e5fef9dee3f2d3af8f9162075b8f1cfa34446
https://github.com/llvm/llvm-project/commit/299e5fef9dee3f2d3af8f9162075b8f1cfa34446
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Simplify/unify vectors for scattered/vectorized loads from
gathers, NFC.
Commit: 6ce418113746c1d8a85012d1f8e22270eb5fdaf1
https://github.com/llvm/llvm-project/commit/6ce418113746c1d8a85012d1f8e22270eb5fdaf1
Author: Jan Patrick Lehr <jplehr at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M openmp/libomptarget/test/lit.cfg
Log Message:
-----------
[OpenMP] HSA_ENABLE_SDMA visible in libomptarget tests (#80860)
Enable the environment variable inside the test environment. This allows
to disable SDMA engine transfers as a potential mitigation of flaky
OpenMP offloading tests on AMDGPU.
Motivated by the open ticket https://github.com/ROCm/ROCm/issues/2616
about a missed synchronization signal.
Commit: 93a2a8cb7f6ab815849e8320bff54c965edd09e7
https://github.com/llvm/llvm-project/commit/93a2a8cb7f6ab815849e8320bff54c965edd09e7
Author: Ryosuke Niwa <rniwa at webkit.org>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
A clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp
Log Message:
-----------
Fix a crash in clang::isGetterOfRefCounted by checking nullptr in tryToFindPtrOrigin (#80768)
Commit: 56900278b578b4f7beedb8ac1e52c541d347f401
https://github.com/llvm/llvm-project/commit/56900278b578b4f7beedb8ac1e52c541d347f401
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lldb/unittests/Core/DiagnosticEventTest.cpp
Log Message:
-----------
[lldb][unittest] Use shared once_flag in DiagnosticEventTest (#80788)
Incorporates the changes from
https://github.com/llvm/llvm-project/pull/80786 to use a once_flag from
`TestUtilities` instead of a local flag in order to prevent hitting an
assertion that the debugger was initialized again in another test.
Commit: a628f68a9c4ce6f3dcd0c8bb3650db45671ed15a
https://github.com/llvm/llvm-project/commit/a628f68a9c4ce6f3dcd0c8bb3650db45671ed15a
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/test/Format/clang-format-ignore.cpp
Log Message:
-----------
Revert "[clang] Mark clang-format-ignore.cpp as unsupported on Windows"
This reverts commit dc61ebb44c11d2f5d03b7dd9cb80a0644a30775e.
See https://github.com/llvm/llvm-project/pull/76733#issuecomment-1890311152.
Commit: 8ea858b96787578e814723a009f443808f446378
https://github.com/llvm/llvm-project/commit/8ea858b96787578e814723a009f443808f446378
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/TypeMetadataUtils.h
M llvm/lib/Analysis/TypeMetadataUtils.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
Log Message:
-----------
[CallPromotionUtil] See through function alias when devirtualizing a virtual call on an alloca. (#80736)
- Extract utility function from
`DevirtModule::tryFindVirtualCallTargets` [1], which sees through an alias to a function. Call this utility function in
the WPD callsite.
- For type profiling work, this helper function will be used by indirect-call-promotion pass to find the function pointer at a specified vtable offset (an example in [2])
[1] https://github.com/llvm/llvm-project/blob/b99163fe8feeacba7797d5479bbcd5d8f327dd2d/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp#L1069-L1082
[2] https://github.com/minglotus-6/llvm-project/blob/77a0ef12de82d11f448f7f9de6f2dcf87d9b74af/llvm/lib/Transforms/Instrumentation/IndirectCallPromotion.cpp#L347
Commit: 6b2fd7aed66d592738f26c76caa8fff95e168598
https://github.com/llvm/llvm-project/commit/6b2fd7aed66d592738f26c76caa8fff95e168598
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
M llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
M llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
M llvm/test/CodeGen/Mips/jump-table-mul.ll
M llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
Log Message:
-----------
[MIPS] Use generic isBlockOnlyReachableByFallthrough (#80799)
FastISel may create a redundant BGTZ terminal which fallthroughes.
```
BGTZ %2:gpr32, %bb.1, implicit-def $at
bb.1.bb1:
; predecessors: %bb.0
```
The `!I->isBarrier()` check in
MipsAsmPrinter::isBlockOnlyReachableByFallthrough
will incorrectly not print a label, leading to a `Undefined temporary
symbol `
error when we try assembling the output assembly file. See the updated
`Fast-ISel/pr40325.ll` and
https://github.com/rust-lang/rust/issues/108835
In addition, the `SwitchInst` condition is too conservative and prints
many unneeded labels (see the updated tests).
Just use the generic isBlockOnlyReachableByFallthrough, updated by
commit 1995b9fead62f2f6c0ad217bd00ce3184f741fdb for SPARC, which also
handles MIPS.
Commit: cca49663a56d90f6773f140269940d606aa61430
https://github.com/llvm/llvm-project/commit/cca49663a56d90f6773f140269940d606aa61430
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/fast-isel-fcmp.ll
M llvm/test/CodeGen/X86/fast-isel-ret-ext.ll
M llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/xaluo.ll
M llvm/test/CodeGen/X86/xmulo.ll
M llvm/test/DebugInfo/X86/convert-debugloc.ll
Log Message:
-----------
[FastISel][X86] Use getTypeForExtReturn in GetReturnInfo. (#80803)
The comment and code here seems to match getTypeForExtReturn. The
history shows that at the time this code was added, similar code existed
in SelectionDAGBuilder. SelectionDAGBuiler code has since been
refactored into getTypeForExtReturn.
This patch makes FastISel match SelectionDAGBuilder.
The test changes are because X86 has customization of
getTypeForExtReturn. So now we only extend returns to i8.
Stumbled onto this difference by accident.
Commit: 2a4f715b0797f235b58f6dfefbc369c2374c44c1
https://github.com/llvm/llvm-project/commit/2a4f715b0797f235b58f6dfefbc369c2374c44c1
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
Log Message:
-----------
[RISCV] Adjust a few vector scheduler class names. NFC (#80795)
Shortening Iota to Iot seemed strange to me.
I also remove the M from VMIota and VMIdx. The instruction for viota
does have an m at the end of it, but vid.v does not. The M didn't seem
very important for viota.
Commit: 0fb9f68bae4743dbabbccf3bbc575ac569730840
https://github.com/llvm/llvm-project/commit/0fb9f68bae4743dbabbccf3bbc575ac569730840
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
Log Message:
-----------
[SelectionDAG] Use getRegisterType instead of getTypeToTransformTo in ComputePHILiveOutRegInfo. (#80773)
Since we used getNumRegisters right before this, I think this is the
correct interface we should be using here.
I'm experimenting with making i32 legal on RISC-V 64, but using i64 for
the register type between basic blocks. This was one of the first issues
I found trying to do that.
Commit: 1833de3ee364a996d03bb23b19fe472e3e2ddf3b
https://github.com/llvm/llvm-project/commit/1833de3ee364a996d03bb23b19fe472e3e2ddf3b
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/test/Transforms/HotColdSplit/split-out-dbg-label.ll
M llvm/test/Transforms/IROutliner/gvn-phi-debug.ll
Log Message:
-----------
[Extractor][DebugInfo] Don't pick DebugLocs from dbg intrinsics (#80863)
When picking the source location for a branch instruction in the
CodeExtractor, we can end up picking the source location of a debugging
intrinsic. This never makes sense because any variable assignment
information (or labels) might originate from completely different
lexical scopes that have been inlined, and also makes the line tables
change between -g and -gmlt. Fix this by skipping debug intrinsics when
looking for branch source locations.
Detected because of test differences with RemoveDIs, the non-intrinsinc
form of debug-info -- fixing in intrinsic form to avoid there being
spurious test differences when we turn it on.
Commit: 6eb7273b11e6a3ec7c5ddb2d55bc585a25c0a923
https://github.com/llvm/llvm-project/commit/6eb7273b11e6a3ec7c5ddb2d55bc585a25c0a923
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/TextAPI/BinaryReader/DylibReader.cpp
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[readtapi] Ensure universal dylibs record the same input path location across slices (#80875)
resolves: https://github.com/llvm/llvm-project/issues/80868
Commit: 2faeea313fef284fa933e7adb1d4c44a33e943e5
https://github.com/llvm/llvm-project/commit/2faeea313fef284fa933e7adb1d4c44a33e943e5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add Ssqosid support to -march. (#80747)
Commit: c7d181cc67a7af122835bc51159baa0eb6c5ac7c
https://github.com/llvm/llvm-project/commit/c7d181cc67a7af122835bc51159baa0eb6c5ac7c
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[llvm][unittests] Put human-readable names on TargetParserTests. NFC (#80749)
Before:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/0 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/1 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/2 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/3 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/4 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/5 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/6 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/7 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/8
...
```
After:
```
[----------] 65 tests from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a34 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a35 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a53 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a55 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a510 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a520 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a57 (0 ms)
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms)
...
```
Which improves the experience of finding and running this:
```
$ ./unittests/TargetParser/TargetParserTests --gtest_filter=AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
Note: Google Test filter = AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[==========] Running 1 test from 1 test suite.
[----------] Global test environment set-up.
[----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture
[ RUN ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65
[ OK ] AArch64CPUTests/AArch64CPUTestFixture.testAArch64CPU/cortex_a65 (0 ms)
[----------] 1 test from AArch64CPUTests/AArch64CPUTestFixture (0 ms total)
[----------] Global test environment tear-down
[==========] 1 test from 1 test suite ran. (0 ms total)
[ PASSED ] 1 test.
```
Commit: a4531108da358500939af95b53794591432aaf74
https://github.com/llvm/llvm-project/commit/a4531108da358500939af95b53794591432aaf74
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/test/Transforms/Util/Debugify/loc-only-original-mode.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] Extend intrinsic-conversion in debugify (#80861)
A while back the entry/exit points of debugify were instrumented with
conversion functions to/from non-intrinsic-form debug-info. This is the
path of least resistance to incrementally converting parts of LLVM to
use the new format. However, it turns out that debugify registers
callbacks with the pass manager and can be fed non-intrinsic form
debug-info. Thus: this patch wraps each of the four major debugify
functions with the convertion utilities, and extends test coverage to a
test that exposes this problem.
(An alternative would be to put this code in the callback lambdas, but
then it would be fighting pass manager abstractions of what type the IR
has).
Handily debugify has been designed to record the /meaning/ of debug-info
rather than take pointers to intrinsics and the like, so the storage
mechanism for debug-info is transparent to it!
Commit: 33cfc1341fab1af8d0f2a8270332fcc91895f473
https://github.com/llvm/llvm-project/commit/33cfc1341fab1af8d0f2a8270332fcc91895f473
Author: Davide Italiano <davidino at fb.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[github][CODEOWNERS] Add BOLT.
Commit: f2508d0a406c8978636eafeb9a23e15984e68836
https://github.com/llvm/llvm-project/commit/f2508d0a406c8978636eafeb9a23e15984e68836
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[RISCV][Docs] Use double underscore for external links in RISCVUsage.rst.
Using a single underscore creates a reference target. If the target
name has the same name as another link, we get a "Duplicate target name"
warning. This is currently happening for Ssqosid.
Using __ prevents this. I've converted all links so no one trips over
this in the future.
One link was missing any underscores so wasn't a link at all in the
generated html.
Commit: 5ac2320824fd545a0d746a1d989543ec4bbd03fa
https://github.com/llvm/llvm-project/commit/5ac2320824fd545a0d746a1d989543ec4bbd03fa
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/src/errno/libc_errno.cpp
M libc/src/errno/libc_errno.h
Log Message:
-----------
[libc][NFC] Fix extraneous namespace on Errno (#80894)
The Errno type doesn't need to be explicitly namespaced now that it's
enclosed in a namespace.
Commit: a8ab8306069e8e53b5148ceec7624d7d36ffb459
https://github.com/llvm/llvm-project/commit/a8ab8306069e8e53b5148ceec7624d7d36ffb459
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lldb/unittests/Core/CMakeLists.txt
A lldb/unittests/Core/ProgressReportTest.cpp
Log Message:
-----------
Reland "[lldb][progress][NFC] Add unit test for progress reports" (#80791)
This file was previously approved and merged from this PR:
https://github.com/llvm/llvm-project/pull/79533 but caused a test
failure on the Linux AArch64 bots due to hitting an assertion that
`Debugger::Initialize` was already called.
To fix this, this commit uses the
changes made here: https://github.com/llvm/llvm-project/pull/80786 to
use a shared call_once flag to initialize the debugger.
Commit: cdd9221489ec4ed6afc0e5146c2fae4daa8ab260
https://github.com/llvm/llvm-project/commit/cdd9221489ec4ed6afc0e5146c2fae4daa8ab260
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
A llvm/test/Transforms/InstCombine/umulo-square.ll
Log Message:
-----------
[InstCombine] Simplify the overflow result of `umulov X, X` (#80796)
This patch does the following folds if only the overflow result is used:
```
extractvalue (umul.with.overflow iN X, X), 1 -> icmp ugt X, 2^(N/2)-1
```
Alive2: https://alive2.llvm.org/ce/z/a8yPC6
Commit: 6812bc40bd6c70f7cae10d1e0a2aeac31cfaef03
https://github.com/llvm/llvm-project/commit/6812bc40bd6c70f7cae10d1e0a2aeac31cfaef03
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/src/__support/float_to_string.h
Log Message:
-----------
[libc] Fix off by one in long double buffer size (#80889)
The size for the long double BLOCK_BUFFER_LEN is calculated based on the
properties of the long double type. Somewhere in the calculation, the
result was mis-rounded so that the buffer was one element too small.
This patch fixes the issue and adds asserts to catch it sooner in the
future.
Commit: 5f87957fefb21d454f2fd7e6b4891350170d8690
https://github.com/llvm/llvm-project/commit/5f87957fefb21d454f2fd7e6b4891350170d8690
Author: Adam Magier <83226568+AdamMagierFOSS at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
A clang/test/CodeGen/ubsan-shift-bitint.c
Log Message:
-----------
[clang][CodeGen][UBSan] Fixing shift-exponent generation for _BitInt (#80515)
Testing the shift-exponent check with small width _BitInt values exposed
a bug in ScalarExprEmitter::GetWidthMinusOneValue when using the result
to determine valid exponent sizes. False positives were reported for
some left shifts when width(LHS)-1 > range(RHS) and false negatives were
reported for right shifts when value(RHS) > range(LHS). This patch caps
the maximum value of GetWidthMinusOneValue to fit within range(RHS) to
fix the issue with left shifts and fixes a code generation in EmitShr to
fix the issue with right shifts and renames the function to
GetMaximumShiftAmount to better reflect the new behaviour.
Fixes #80135.
Co-authored-by: Adam Magier <adam.magier at ericsson.com>
Commit: c6691f689e9aa787b809fd3493bae8a5ca845cea
https://github.com/llvm/llvm-project/commit/c6691f689e9aa787b809fd3493bae8a5ca845cea
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/pread.cpp
Log Message:
-----------
[libc] Fix pread under msan (#80893)
The pread function wasn't properly unpoisoning its result under msan,
causing test failures downstream when I tried to roll it out. This patch
adds the msan unpoison call that fixes the issue.
Commit: ce00fdc91cb7a466054c3ffd8788ae2f9f5100f3
https://github.com/llvm/llvm-project/commit/ce00fdc91cb7a466054c3ffd8788ae2f9f5100f3
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/test/Driver/wasm-features.c
M clang/test/Preprocessor/wasm-target-features.c
Log Message:
-----------
[WebAssembly] Cleanup feature tests (#80780)
This adds missing features to the tests and removes a stale feature
(unimplemented_simd128) from them.
Commit: 5b780c8c6c558ec283a9eec485a4f172df0f9fe1
https://github.com/llvm/llvm-project/commit/5b780c8c6c558ec283a9eec485a4f172df0f9fe1
Author: PiJoules <6019989+PiJoules at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/include/clang/AST/Type.h
M clang/lib/Sema/SemaOverload.cpp
M clang/test/Frontend/fixed_point_errors.cpp
Log Message:
-----------
Diagnose invalid fixed point conversion (#80763)
Commit: 5ce2f73b2e5e6664d74b49ee45f11505f8306577
https://github.com/llvm/llvm-project/commit/5ce2f73b2e5e6664d74b49ee45f11505f8306577
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] Add some missing test coverage
In github PR #78731 it looks like I added test coverage for RemoveDIs to
either the wrong test, or not enough. Adding
--try-experimental-debuginfo-iterators to this particular test is enough to
restore some coverage it seems.
Commit: c13e271a38363d354294e2af1651470bed8facb3
https://github.com/llvm/llvm-project/commit/c13e271a38363d354294e2af1651470bed8facb3
Author: Bhuminjay Soni <Soni5Happy at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/readability/CMakeLists.txt
M clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp
A clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp
A clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst
A clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp
Log Message:
-----------
Add clang-tidy check to suggest replacement of conditional statement with std::min/std::max (#77816)
This pull request fixes #64914 where author suggests adding a
readability check to propose the replacement of conditional statements
with std::min/std::max for improved code readability. Additionally,
reference is made to PyLint's similar checks:
[consider-using-min-builtin](https://pylint.pycqa.org/en/latest/user_guide/messages/refactor/consider-using-min-builtin.html)
and
[consider-using-max-builtin](https://pylint.pycqa.org/en/latest/user_guide/messages/refactor/consider-using-max-builtin.html)
Commit: e197b957ce1061cb1bfbd586b703065367cce5dc
https://github.com/llvm/llvm-project/commit/e197b957ce1061cb1bfbd586b703065367cce5dc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
Log Message:
-----------
[RISCV] Fix typo in call to clearFeatureBits.
We had "+zca" instead of "zca". The previous line used "c", not "+c".
This may not be a functional change. I think the function we pass this
to strips any '+' or '-'.
Commit: 8bb827c0e67e51adba1252d23edc58197e025cf7
https://github.com/llvm/llvm-project/commit/8bb827c0e67e51adba1252d23edc58197e025cf7
Author: Shubham Sandeep Rastogi <srastogi22 at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
A llvm/test/Verifier/verify-dwarf-no-operands.ll
Log Message:
-----------
Add test for iterating over MDNode operands when they are empty (#80737)
With e8512786fedbfa6ddba70ceddc29d7122173ba5e the for loop that iterates
over MDNode operands was changed to a range-based for loop. This change
surfaces a bug where if the result of MD->operands() is an ArrayRef that
has a size of 0, then iterating over that ArrayRef leads to a
segmentation fault, due to accessing invalid addresses.
This was reverted with 6ce03ff3fef8fb6fa9afe8eb22c6d98bced26d48 but this
test should be added to test that codepath in the future.
Commit: 4858e9c9feb94d65acdb284fc2eaa5fe131c6584
https://github.com/llvm/llvm-project/commit/4858e9c9feb94d65acdb284fc2eaa5fe131c6584
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
A llvm/test/Transforms/InstCombine/fcmp-range-check-idiom.ll
Log Message:
-----------
[InstCombine] Canonicalize the fcmp range check idiom into `fabs + fcmp` (#76367)
This patch canonicalizes the fcmp range check idiom into `fabs + fcmp`
since the canonicalized form is better than the original form for the
backends.
Godbolt: https://godbolt.org/z/x3eqPb1fz
```
and (fcmp olt/ole/ult/ule x, C), (fcmp ogt/oge/ugt/uge x, -C) --> fabs(x) olt/ole/ult/ule C
or (fcmp ogt/oge/ugt/uge x, C), (fcmp olt/ole/ult/ule x, -C) --> fabs(x) ogt/oge/ugt/uge C
```
Alive2: https://alive2.llvm.org/ce/z/MRtoYq
Commit: 90e8dc0f7cbd09cc653b497eb2dfc68edd800f48
https://github.com/llvm/llvm-project/commit/90e8dc0f7cbd09cc653b497eb2dfc68edd800f48
Author: stephenpeckham <118857872+stephenpeckham at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll
M llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll
Log Message:
-----------
Fix failing testcases (#80902)
Commit: 672fb27b267edc5dec4939b0295c8eebcdc57467
https://github.com/llvm/llvm-project/commit/672fb27b267edc5dec4939b0295c8eebcdc57467
Author: Yitzhak Mandelbaum <ymand at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
Log Message:
-----------
[clang][dataflow] Add new `join` API and replace existing `merge` implementations. (#80361)
This patch adds a new interface for the join operation, now properly
called `join`. Originally, the framework offered a single `merge`
operation, which could serve either as a join or a widening. In
practice, though we found this conflation didn't work for non-trivial
anlyses, and split of the widening operation (`widen`). This change
completes the transition by introducing a proper `join` with strict join
semantics.
In the process, it drops an odd (and often misused) aspect of `merge`
wherein callees could implictly instruct the framework to drop the
current entry by returning `false`. This features was never used
correctly in analyses and doesn't belong in a join operation, so it is
omitted.
---------
Co-authored-by: Dmitri Gribenko <gribozavr at gmail.com>
Co-authored-by: martinboehme <mboehme at google.com>
Commit: 4607f385e005b3792b5669683d2c9b50d83e4e61
https://github.com/llvm/llvm-project/commit/4607f385e005b3792b5669683d2c9b50d83e4e61
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Log Message:
-----------
[RISCV] Use hasStdExtCOrZca instead of FeatureStdExtC to determine NOP size in RISCVAsmPrinter.cpp.
Found while auditing places where we only check C and not Zca.
Commit: 3f1e95a9d4cc1fdb933390247d0bd4391cf93f60
https://github.com/llvm/llvm-project/commit/3f1e95a9d4cc1fdb933390247d0bd4391cf93f60
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeEmitter.cpp
M clang/test/AST/ms-constexpr.cpp
Log Message:
-----------
[clang][Interp] consider "MS constexpr" functions as well
This implements the minimum amout of support for this feature
to get the test/AST/ms-constexpr.cpp test working. More has to
be added to get SemaCXX tests to work.
Commit: cd0d11be7a6de335dcfcf2788a97d915f017e25e
https://github.com/llvm/llvm-project/commit/cd0d11be7a6de335dcfcf2788a97d915f017e25e
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll
M llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/add.ll
M llvm/test/CodeGen/M68k/Arith/bitwise.ll
M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
M llvm/test/CodeGen/M68k/Atomics/load-store.ll
M llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll
M llvm/test/CodeGen/M68k/CConv/c-args.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-args.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
M llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
M llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
M llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
M llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
M llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
M llvm/test/CodeGen/M68k/CodeModel/small-static.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
M llvm/test/CodeGen/M68k/inline-asm.ll
M llvm/test/CodeGen/M68k/link-unlnk.ll
M llvm/test/CodeGen/M68k/reserved-regs.ll
M llvm/test/CodeGen/M68k/varargs.ll
Log Message:
-----------
[M68k] Convert tests to opaque pointers (NFC)
Commit: 423ac3d9ee82ff48da91b35ec80497089bc55b9e
https://github.com/llvm/llvm-project/commit/423ac3d9ee82ff48da91b35ec80497089bc55b9e
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll
M llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll
M llvm/test/CodeGen/CSKY/atomic-load-store.ll
M llvm/test/CodeGen/CSKY/atomic-rmw.ll
M llvm/test/CodeGen/CSKY/call-16bit.ll
M llvm/test/CodeGen/CSKY/call.ll
M llvm/test/CodeGen/CSKY/constantpool.ll
M llvm/test/CodeGen/CSKY/dwarf-eh.ll
M llvm/test/CodeGen/CSKY/fpu/ldst-d.ll
M llvm/test/CodeGen/CSKY/fpu/ldst-f.ll
M llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll
M llvm/test/CodeGen/CSKY/indirectbr.ll
M llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/CSKY/inline-asm.ll
M llvm/test/CodeGen/CSKY/ldst-i.ll
M llvm/test/CodeGen/CSKY/tls-models.ll
Log Message:
-----------
[CSKY] Convert tests to opaque pointers (NFC)
Commit: 1c22d3f55df852985c155742bbe96ab5e86aa6f0
https://github.com/llvm/llvm-project/commit/1c22d3f55df852985c155742bbe96ab5e86aa6f0
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/CodeGen/ARC/addrmode.ll
M llvm/test/CodeGen/ARC/call.ll
M llvm/test/CodeGen/ARC/ldst.ll
Log Message:
-----------
[ARC] Convert tests to opaque pointers (NFC)
Commit: 92b33822e989884d29465d34769b07d78aeb1a84
https://github.com/llvm/llvm-project/commit/92b33822e989884d29465d34769b07d78aeb1a84
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/DebugInfo/MIR/AArch64/clobber-sp.mir
M llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-expr-chain.mir
M llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param-with-offset.mir
M llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-indirect-param.mir
M llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-interpretation.mir
M llvm/test/DebugInfo/MIR/AArch64/dbgcall-site-orr-moves.mir
M llvm/test/DebugInfo/MIR/AArch64/implicit-def-dead-scope.mir
M llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovd.mir
M llvm/test/DebugInfo/MIR/ARM/call-site-info-vmovs.mir
M llvm/test/DebugInfo/MIR/ARM/dbgcall-site-interpretation.mir
M llvm/test/DebugInfo/MIR/ARM/dbgcall-site-propagated-value.mir
M llvm/test/DebugInfo/MIR/ARM/if-coverter-call-site-info.mir
M llvm/test/DebugInfo/MIR/ARM/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/ARM/param-reg-const-mix.mir
M llvm/test/DebugInfo/MIR/ARM/split-superreg-complex.mir
M llvm/test/DebugInfo/MIR/ARM/split-superreg-piece.mir
M llvm/test/DebugInfo/MIR/ARM/split-superreg.mir
M llvm/test/DebugInfo/MIR/Hexagon/dbgcall-site-instr-before-bundled-call.mir
M llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-indir-value.mir
M llvm/test/DebugInfo/MIR/InstrRef/follow-spill-of-live-value.mir
M llvm/test/DebugInfo/MIR/InstrRef/memory-operand-folding-tieddef.mir
M llvm/test/DebugInfo/MIR/InstrRef/out-of-scope-blocks.mir
M llvm/test/DebugInfo/MIR/InstrRef/restore-clobber-with-indirectness.mir
M llvm/test/DebugInfo/MIR/InstrRef/stack-coloring-dbg-phi.mir
M llvm/test/DebugInfo/MIR/InstrRef/win32-chkctk-modifies-esp.mir
M llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir
M llvm/test/DebugInfo/MIR/InstrRef/x86-fp-stackifier-drop-locations.mir
M llvm/test/DebugInfo/MIR/InstrRef/x86-lea-fixup.mir
M llvm/test/DebugInfo/MIR/Mips/dbg-call-site-copy-sub-reg.mir
M llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation-64bit.mir
M llvm/test/DebugInfo/MIR/Mips/dbg-call-site-delay-slot-interpretation.mir
M llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu-64bit.mir
M llvm/test/DebugInfo/MIR/Mips/dbg-call-site-param-addiu.mir
M llvm/test/DebugInfo/MIR/Mips/last-inst-bundled.mir
M llvm/test/DebugInfo/MIR/Mips/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/X86/avoid-single-entry-value-location.mir
M llvm/test/DebugInfo/MIR/X86/backup-entry-values-usage.mir
M llvm/test/DebugInfo/MIR/X86/call-site-gnu-vs-dwarf5-attrs.mir
M llvm/test/DebugInfo/MIR/X86/clobbered-fragments.mir
M llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg-multiple-defs.mir
M llvm/test/DebugInfo/MIR/X86/dbg-call-site-spilled-arg.mir
M llvm/test/DebugInfo/MIR/X86/dbg-stack-value-range.mir
M llvm/test/DebugInfo/MIR/X86/dbgcall-site-interpretation.mir
M llvm/test/DebugInfo/MIR/X86/dbgcall-site-lea-interpretation.mir
M llvm/test/DebugInfo/MIR/X86/dbgcall-site-reference.mir
M llvm/test/DebugInfo/MIR/X86/dbgcall-site-two-fwd-reg-defs.mir
M llvm/test/DebugInfo/MIR/X86/debug-call-site-param.mir
M llvm/test/DebugInfo/MIR/X86/debug-entry-value-operation.mir
M llvm/test/DebugInfo/MIR/X86/debug-loc-0.mir
M llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-movements.mir
M llvm/test/DebugInfo/MIR/X86/dvl-livedebugvars-stackptr.mir
M llvm/test/DebugInfo/MIR/X86/empty-inline.mir
M llvm/test/DebugInfo/MIR/X86/kill-after-spill.mir
M llvm/test/DebugInfo/MIR/X86/ldv_unreachable_blocks.mir
M llvm/test/DebugInfo/MIR/X86/ldv_unreachable_blocks2.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-entry-transfer.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-fragments.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-restore.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values-spill.mir
M llvm/test/DebugInfo/MIR/X86/live-debug-values.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvalues-limit.mir
M llvm/test/DebugInfo/MIR/X86/livedebugvars-crossbb-interval.mir
M llvm/test/DebugInfo/MIR/X86/machine-cse.mir
M llvm/test/DebugInfo/MIR/X86/machinesink-subreg.mir
M llvm/test/DebugInfo/MIR/X86/machinesink.mir
M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-post-regalloc.mir
M llvm/test/DebugInfo/MIR/X86/mlicm-hoist-pre-regalloc.mir
M llvm/test/DebugInfo/MIR/X86/multiple-param-dbg-value-entry.mir
M llvm/test/DebugInfo/MIR/X86/no-cfi-loc.mir
M llvm/test/DebugInfo/MIR/X86/postra-subreg-sink.mir
M llvm/test/DebugInfo/MIR/X86/prolog-epilog-indirection.mir
M llvm/test/DebugInfo/MIR/X86/regcoalescing-clears-dead-dbgvals.mir
M llvm/test/DebugInfo/MIR/X86/remove-redundant-dbg-vals.mir
M llvm/test/DebugInfo/MIR/X86/sink-leaves-undef.mir
Log Message:
-----------
[DebugInfo/MIR] Convert tests to opaque pointers (NFC)
Link: https://discourse.llvm.org/t/enabling-opaque-pointers-by-default/61322
Commit: cc55af777a19b69f466875683655810f5d485386
https://github.com/llvm/llvm-project/commit/cc55af777a19b69f466875683655810f5d485386
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/Sema/struct-cast.c
Log Message:
-----------
[clang][Interp] Only check ComparisonCategoryInfo in C++ (#80131)
Binary operators are also of struct type in C, when assigning. Don't try to get the ComparisonCategoryInfo in that case.
Commit: 3a05e01d1a76984fe1532bd237edbbb7ed9db6ea
https://github.com/llvm/llvm-project/commit/3a05e01d1a76984fe1532bd237edbbb7ed9db6ea
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/DebugInfo/AArch64/asan-stack-vars.mir
M llvm/test/DebugInfo/AArch64/compiler-gen-bbs-livedebugvalues.mir
M llvm/test/DebugInfo/AArch64/fallthrough-branch.ll
M llvm/test/DebugInfo/AArch64/frameindices.ll
M llvm/test/DebugInfo/AArch64/machine-outliner.ll
M llvm/test/DebugInfo/ARM/cfi-eof-prologue.mir
M llvm/test/DebugInfo/ARM/machine-cp-updates-dbg-reg.mir
M llvm/test/DebugInfo/COFF/function-options.ll
M llvm/test/DebugInfo/COFF/global_rust.ll
M llvm/test/DebugInfo/COFF/nrvo.ll
M llvm/test/DebugInfo/COFF/thunk.ll
M llvm/test/DebugInfo/COFF/type-quals.ll
M llvm/test/DebugInfo/COFF/types-basic.ll
M llvm/test/DebugInfo/COFF/types-cvarargs.ll
M llvm/test/DebugInfo/COFF/types-data-members.ll
M llvm/test/DebugInfo/COFF/vftables.ll
M llvm/test/DebugInfo/COFF/virtual-methods.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/dse/dse-after-memcpyopt-merge.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/dse/shorten-offset.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/dse/shorten.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/inline/id.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/inline/inline-stores.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/memset.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/sink-store.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/sink.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/instcombine/storemerge.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/licm/multi-exit.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/loop-deletion/dead-loop.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/memcpyopt/merge-stores.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/mldst-motion/diamond.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/remove-redundant-fwd-scan-linked.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/simplifycfg/empty-block.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/simplifycfg/speculated-store.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/slp-vectorizer/merge-scalars.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/after-inlining.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/alloca-single-slice.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/complex.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag-2.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/frag.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/id.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/memcpy.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/rewrite.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/store.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/unspecified-var-size.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/user-memcpy.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/sroa/vec-2.ll
M llvm/test/DebugInfo/Generic/assignment-tracking/track-assignments.ll
M llvm/test/DebugInfo/Generic/import-inlined-declaration.ll
M llvm/test/DebugInfo/Generic/licm-hoist-debug-loc.ll
M llvm/test/DebugInfo/Generic/licm-hoist-intrinsic-debug-loc.ll
M llvm/test/DebugInfo/Generic/split-dwarf-local-import.ll
M llvm/test/DebugInfo/MSP430/dwarf-basics.ll
M llvm/test/DebugInfo/MSP430/fp-vla-callee-saved.ll
M llvm/test/DebugInfo/X86/DW_AT_calling-convention.ll
M llvm/test/DebugInfo/X86/PR37234.ll
M llvm/test/DebugInfo/X86/containing-type-extension-rust.ll
M llvm/test/DebugInfo/X86/dbg-value-list-selectiondag-salvage.ll
M llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_at_return.mir
M llvm/test/DebugInfo/X86/dbg_entity_calc_ignores_KILL_instruction_still_clobbers.mir
M llvm/test/DebugInfo/X86/debug-info-blocks.ll
M llvm/test/DebugInfo/X86/debug-loc-asan.mir
M llvm/test/DebugInfo/X86/debug-loc-frame.ll
M llvm/test/DebugInfo/X86/debug-loc-offset.mir
M llvm/test/DebugInfo/X86/dw_op_minus.mir
M llvm/test/DebugInfo/X86/empty-and-one-elem-array.ll
M llvm/test/DebugInfo/X86/fragment-offset-order.ll
M llvm/test/DebugInfo/X86/global-sra-struct-part-overlap-segment.ll
M llvm/test/DebugInfo/X86/linkage-name.ll
M llvm/test/DebugInfo/X86/live-debug-values-constprop.mir
M llvm/test/DebugInfo/X86/live-debug-vars-discard-invalid.mir
M llvm/test/DebugInfo/X86/live-debug-vars-dse.mir
M llvm/test/DebugInfo/X86/live-debug-vars-intervals.mir
M llvm/test/DebugInfo/X86/location-range-inlined-xblock.mir
M llvm/test/DebugInfo/X86/location-range.mir
M llvm/test/DebugInfo/X86/pr19307.mir
M llvm/test/DebugInfo/X86/prolog-params.mir
M llvm/test/DebugInfo/X86/single-location-inlined-param.mir
M llvm/test/DebugInfo/X86/single-location-interrupted-scope.mir
M llvm/test/DebugInfo/X86/single-location.mir
M llvm/test/DebugInfo/assignment-tracking/X86/lower-offset-expression.ll
M llvm/test/DebugInfo/assignment-tracking/X86/lower-to-value.ll
M llvm/test/DebugInfo/assignment-tracking/X86/mem-loc-frag-fill-cfg.ll
M llvm/test/DebugInfo/assignment-tracking/X86/mem-loc-frag-fill.ll
M llvm/test/DebugInfo/assignment-tracking/X86/single-memory-location-2.ll
M llvm/test/DebugInfo/assignment-tracking/X86/single-memory-location.ll
Log Message:
-----------
[DebugInfo] Convert tests to opaque pointers (NFC)
Link: https://discourse.llvm.org/t/enabling-opaque-pointers-by-default/61322
Commit: 51a3019e4d096d93820f921af20d7a0bf3fffc48
https://github.com/llvm/llvm-project/commit/51a3019e4d096d93820f921af20d7a0bf3fffc48
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
A clang/test/CXX/drs/dr28xx.cpp
Log Message:
-----------
[Clang][Sema] Implement proposed resolution for CWG2847 (#80899)
Per the approved resolution for CWG2847, [temp.expl.spec] p8 will state:
> An explicit specialization shall not have a trailing _requires-clause_ unless it declares a function template.
We already implement this _partially_ insofar that a diagnostic is issued upon instantiation of `A<int>` in the following example:
```
template<typename>
struct A
{
template<typename>
void f();
template<>
void f<int>() requires true; // error: non-templated function cannot have a requires clause
};
template struct A<int>; // note: in instantiation of template class 'A<int>' requested here
```
This patch adds a bespoke diagnostic for such declarations, and moves the point of diagnosis for non-templated functions with trailing requires-clauses from `CheckFunctionDeclaration` to `ActOnFunctionDeclarator` (there is no point in diagnosing this during instantiation since we already have all the necessary information when parsing the declaration).
Commit: 12aad1a53c7ae70b88e7cb3fa3d04b6a3532f669
https://github.com/llvm/llvm-project/commit/12aad1a53c7ae70b88e7cb3fa3d04b6a3532f669
Author: carlobertolli <carlo.bertolli at amd.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M openmp/libomptarget/src/omptarget.cpp
A openmp/libomptarget/test/mapping/auto_zero_copy_globals.cpp
Log Message:
-----------
[OpenMP] Support for global variables when in auto zero-copy. (#80876)
When building without unified_shared_memory, global variables are
declared in the device binary and allocated upon loading onto GPU
memory. However, when running in zero-copy mode (same as with
unified_shared_memory) D2H and H2D copies for mapped local and global
variables are turned off. This patch turns back on H2D and D2H copies
when they refer to global variables, enabling an application built
without unified_shared_memory to work correctly with global variables
when run under automatic zero-copy.
Co-authored-by: Doru Bercea <doru.bercea at amd.com>
Co-authored-by: Jan-Patrick Lehr <janpatrick.lehr at amd.com>
Commit: 4c9717c3bee3525c2bf0251469191cc65e246a14
https://github.com/llvm/llvm-project/commit/4c9717c3bee3525c2bf0251469191cc65e246a14
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
M mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[mlir][openacc] Add private/reduction in legalize data pass (#80882)
This is a follow up to #80351 and adds private and reduction operands
from acc.loop, acc.parallel and acc.serial operations.
Commit: e96ba2509d5a1a3ba4ebba806828fc62cd2c34de
https://github.com/llvm/llvm-project/commit/e96ba2509d5a1a3ba4ebba806828fc62cd2c34de
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
Log Message:
-----------
[gn build] Port c13e271a3836
Commit: 091fc81d485594d4b751c10518230769c905430c
https://github.com/llvm/llvm-project/commit/091fc81d485594d4b751c10518230769c905430c
Author: Konstantin Varlamov <varconsteq at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M libcxx/include/__config
Log Message:
-----------
[libc++][hardening] Check that `_LIBCPP_HARDENING_MODE_DEFAULT` is defined (#80353)
If the `_LIBCPP_HARDENING_MODE_DEFAULT` macro is not defined,
`_LIBCPP_HARDENING_MODE` will be considered defined but fail the check
for a valid hardening mode, resulting in a slightly less understandable
error (that error is really meant more to prevent users from passing
incorrect values such as `0` or `1` directly rather than catching
configuration issues).
Commit: c8a97c0f30f3da86e892bf68d572068634994a1e
https://github.com/llvm/llvm-project/commit/c8a97c0f30f3da86e892bf68d572068634994a1e
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Use hasStdExtCOrZca instead of hasStdExtC in estimateFunctionSizeInBytes. (#80905)
Commit: 1dd9162b95d29367635f32c7be24779b1ddaa7e5
https://github.com/llvm/llvm-project/commit/1dd9162b95d29367635f32c7be24779b1ddaa7e5
Author: Greg Clayton <gclayton at fb.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lldb/source/Target/TargetList.cpp
M lldb/test/API/python_api/target/TestTargetAPI.py
Log Message:
-----------
[lldb] Fix a crasher when using the public API. (#80508)
A user found a crash when they would do code like:
```
(lldb) script
>>> target = lldb.SBTarget()
>>> lldb.debugger.SetSelectedTarget(target)
```
We were not checking if the target was valid in and it caused a crash..
Commit: 1b5fae9118ab3450f22fb45f686a2cd0d979cbb4
https://github.com/llvm/llvm-project/commit/1b5fae9118ab3450f22fb45f686a2cd0d979cbb4
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/docs/UserGuides.rst
M llvm/docs/WritingAnLLVMNewPMPass.rst
M llvm/docs/WritingAnLLVMPass.rst
Log Message:
-----------
[docs] Try to make it easier to find info about new PM vs legacy PM (#80834)
Seen several beginner questions popping up in discourse about how to
implement and run custom passes. And then it turns out that they are
following the old "Writing an LLVM Pass" guide that describe legacy
passes, and then things are mixed up when they try to run that pass
using opt that nowadays default to the new pass manager.
This is an attempt to make it slightly clearer in the User Guides that
there are two different "Writing an LLVM Pass" pages depending on which
pass manager that should be used. This is done by renaming the legacy
version of "Writing an LLVM Pass" as "Writing an LLVM Pass (legacy PM
version)".
Also reordered the links to put the link to the new pass manager
documentation first.
This patch also moves the warning text that cross references the
description on how to write a pass for legacy/new PM to make sure it
ends up already in the beginning of the descriptions.
Also adding a new warning in the "Running a pass with opt" section of
the legacy PM version of the guide, to inform that those examples are
outdated.
Commit: e976385415da45650952316db63c4ccd370e4030
https://github.com/llvm/llvm-project/commit/e976385415da45650952316db63c4ccd370e4030
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
A llvm/test/Transforms/GlobalOpt/resolve-static-ifunc.ll
Log Message:
-----------
[llvm][GlobalOpt] Optimize statically resolvable IFuncs (#80606)
Commit: 16d890ced68aafae4cc8ba3efc9213bfab84ba54
https://github.com/llvm/llvm-project/commit/16d890ced68aafae4cc8ba3efc9213bfab84ba54
Author: Kojo Acquah <KoolJBlack at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmNeon/ArmNeon.td
M mlir/test/Dialect/ArmNeon/invalid.mlir
M mlir/test/Dialect/ArmNeon/roundtrip.mlir
M mlir/test/Target/LLVMIR/arm-neon.mlir
Log Message:
-----------
[mlir][ArmNeon] Adds Arm Neon SMMLA, UMMLA, and USMMLA Intrinsics (#80511)
This adds the SMMLA, UMMLA, and USMMLA intrinsics to Neon dialect bringing it in line with the SVE dialect.
These ops enable matrix multiply-accumulate instructions with two e 2x8 matrix inputs of respective signage into a 2x2 32-bit integer accumulator. This is equivalent to performing an 8-way dot product per destination element.
Op details:
https://developer.arm.com/architectures/instruction-sets/intrinsics/#f:@navigationhierarchiessimdisa=[Neon]&q=mmla
Commit: 8075f0db16f3291beed65cbcd034b047cc7373bf
https://github.com/llvm/llvm-project/commit/8075f0db16f3291beed65cbcd034b047cc7373bf
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M bolt/lib/Core/BinarySection.cpp
Log Message:
-----------
[BOLT] Use new contents when emitting sections with relocations (#80782)
We can use BinarySection::updateContents() to change section contents.
However, if we also add relocations for new contents, then the original
data (i.e. not updated) is going to be used. Fix that. A follow-up diff
will use the update interface and will include a test case.
Commit: b98db441f01ee8e0cdab8df1ef8a9b0aff2f6e5a
https://github.com/llvm/llvm-project/commit/b98db441f01ee8e0cdab8df1ef8a9b0aff2f6e5a
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M bolt/test/AArch64/ifunc.c
Log Message:
-----------
[BOLT] Make ifunc test not statically-resolvable. NFC
This fixes a breakage caused by e976385415da
Commit: 4d8e849dfbf3ca1301f208a7286b31215d2a94db
https://github.com/llvm/llvm-project/commit/4d8e849dfbf3ca1301f208a7286b31215d2a94db
Author: Alexander Shaposhnikov <6532716+alexander-shaposhnikov at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/abs.ll
Log Message:
-----------
[ConstraintElim] Add facts for llvm.abs >= 0 (#79070)
Add facts for llvm.abs >= 0.
https://alive2.llvm.org/ce/z/GXnMHu
Commit: fbded6663fb04d12f451c18bc8018989d2db3a87
https://github.com/llvm/llvm-project/commit/fbded6663fb04d12f451c18bc8018989d2db3a87
Author: ZijunZhaoCCK <88353225+ZijunZhaoCCK at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
R clang/test/Driver/android-version.cpp
A clang/test/Driver/invalid-version.cpp
Log Message:
-----------
[Driver] Check the environment version except wasm case. (#80783)
Add isWasm() check for here:
https://github.com/llvm/llvm-project/pull/78655#issuecomment-1928075569
Commit: 08457e1f7693bdafe5330cde2bf41290cad4cade
https://github.com/llvm/llvm-project/commit/08457e1f7693bdafe5330cde2bf41290cad4cade
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M libcxx/test/libcxx/containers/sequences/deque/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/list/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/vector.bool/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/vector/abi.compile.pass.cpp
Log Message:
-----------
[libc++] Add tests to pin down the ABI of deque, list and vector (#80191)
This patch adds tests that lock down the ABI of types like deque, list
and vector.
An upcoming patch will replace the usage of __compressed_pair in these
classes
by [[no_unique_address]], so we are adding these tests to pin down their
ABI
before making the change. That way, we can be confident that the patch
making
the actual ABI-sensitive change is safe if it doesn't break these tests.
Commit: 42357df2df4977c80aba77fcab706638a121bde0
https://github.com/llvm/llvm-project/commit/42357df2df4977c80aba77fcab706638a121bde0
Author: PiJoules <6019989+PiJoules at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
A clang/test/AST/fixed-point-zero-init.cpp
Log Message:
-----------
[clang] Add zero-initialization for fixed point types (#80781)
Commit: 2f490583c368627f552c71e340c39f2b55c0526c
https://github.com/llvm/llvm-project/commit/2f490583c368627f552c71e340c39f2b55c0526c
Author: jkorous-apple <32549412+jkorous-apple at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-debug.cpp
Log Message:
-----------
[-Wunsafe-buffer-usage] Fix debug notes for unclaimed DREs (#80787)
Debug notes for unclaimed DeclRefExpr should report any DRE of an unsafe
variable that is not covered by a Fixable (i. e. fixit for the
particular AST pattern isn't implemented for whatever reason). Currently
not all unclaimed DeclRefExpr-s are reported which is a bug. The debug
notes report only those DREs where the referred VarDecl has at least one
other DeclRefExpr which is claimed (covered by a fixit). If there is an
unsafe VarDecl that has exactly one DRE and the DRE isn't claimed then
the debug note about missing fixit won't be emitted. That is because the
debug note is emitted from within a loop over set of successfully
matched FixableGadgets which by-definition is missing those DRE that are
not matched at all.
The new code simply iterates over all unsafe VarDecls and all of their
unclaimed DREs.
Commit: 1b03cbc93989c84ad0b78c27d4427a7eaa5842f1
https://github.com/llvm/llvm-project/commit/1b03cbc93989c84ad0b78c27d4427a7eaa5842f1
Author: Fernando Tagawa <tagawafernando at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/lib/Format/BreakableToken.cpp
M clang/unittests/Format/FormatTestComments.cpp
Log Message:
-----------
[clang-format] Handle doxygen commands starting with \ (#80381)
Fixes llvm/llvm-project#63241
Doxygen commands can start with `@` or `\`.
Commit: 2217837c3377c22bffb6c498a732ce4672b8b535
https://github.com/llvm/llvm-project/commit/2217837c3377c22bffb6c498a732ce4672b8b535
Author: Wanyi <kusmour at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M lldb/bindings/headers.swig
A lldb/bindings/interface/SBStatisticsOptionsDocStrings.i
M lldb/bindings/interfaces.swig
M lldb/include/lldb/API/LLDB.h
M lldb/include/lldb/API/SBDefines.h
A lldb/include/lldb/API/SBStatisticsOptions.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Target/Statistics.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/API/CMakeLists.txt
A lldb/source/API/SBStatisticsOptions.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Commands/CommandObjectStats.cpp
M lldb/source/Commands/Options.td
M lldb/source/Target/Statistics.cpp
M lldb/source/Target/Target.cpp
M lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py
M lldb/test/API/functionalities/stats_api/main.c
Log Message:
-----------
Support statistics dump summary only mode (#80745)
Add a new --summary option to statistics dump command so that it is
much more light weight than the full version.
Introduce a new SBStatisticsOptions API setting the verbosity of statistics dump.
[PR
#80218](https://github.com/llvm/llvm-project/pull/80218#discussion_r1473639878)
Commit: bcd1490496a5bf06ce98470ef622db29a8eebbf7
https://github.com/llvm/llvm-project/commit/bcd1490496a5bf06ce98470ef622db29a8eebbf7
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/API/BUILD.gn
Log Message:
-----------
[gn build] Port 2217837c3377
Commit: 44767278650227b30cf969170dc139197ce4338d
https://github.com/llvm/llvm-project/commit/44767278650227b30cf969170dc139197ce4338d
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/test/Preprocessor/wasm-target-features.c
Log Message:
-----------
[WebAssembly] Add tests for generic CPU config (#80775)
This adds tests for `generic` cpu configuration. We had tests for `mvp`
and `bleeding-edge` configs but not `generic`.
Commit: 897297e8b09ed6076f5dc6883b459b209bb9e29f
https://github.com/llvm/llvm-project/commit/897297e8b09ed6076f5dc6883b459b209bb9e29f
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M clang/test/Driver/wasm-features.c
Log Message:
-----------
[WebAssembly] Fix CPU tests in wasm-features.c (#80900)
The CPU tests in this file are not working as intended. Specifying
`-mcpu=[mvp|generic|bleeding-edge]` in `clang` command line does NOT add
arguments like `-target-feature`, `+feature-name`, ... to `clang-14`
command line. Specifying `-mcpu=[mvp|generic|bleeding-edge]` in `clang`
command line will just add `-target-cpu` `[mvp|generic|bleeding-edge]`
to `clang-14` command line, and individual features are added here
within `clang-14` invocation:
https://github.com/llvm/llvm-project/blob/5b780c8c6c558ec283a9eec485a4f172df0f9fe1/clang/lib/Basic/Targets/WebAssembly.cpp#L150-L163
The reason these CPU tests are passing is because they only have `-NOT`
checks, and we don't emit `-target-feature` arguments for them anyway,
the test passes, but they don't check what they are supposed to check.
This make CPU tests only check `-target-cpu` lines instead of individual
features, which will not be emitted.
Commit: 055ac72ecca4b56826ac02851f8a18f20a8557df
https://github.com/llvm/llvm-project/commit/055ac72ecca4b56826ac02851f8a18f20a8557df
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
Log Message:
-----------
[GISel] Add support for scalable vectors in getLCMType (#80306)
This function can be called from buildCopyToRegs where at least one of
the types is a scalable vector type. This function crashed because it
did not know how to handle scalable vector types.
This patch extends the functionality of getLCMType to handle when at
least one of the types is a scalable vector. getLCMType between a fixed
and scalable vector is not implemented since the docstring of the
function explains that getLCMType is used to build MERGE/UNMERGE
instructions and we will never build a MERGE/UNMERGE between fixed and
scalable vectors.
Commit: 6d268577259071cb1d9cccd89006bae8570f6c51
https://github.com/llvm/llvm-project/commit/6d268577259071cb1d9cccd89006bae8570f6c51
Author: Wanyi <kusmour at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
R lldb/bindings/interface/SBStatisticsOptionsDocStrings.i
A lldb/bindings/interface/SBStatisticsOptionsDocstrings.i
Log Message:
-----------
Fix the Docstring.i filename (#80917)
The typo DocStrings.i broke linux buildbots
Commit: bd1324113e90884a4a83d6232ecf0c623e2e113e
https://github.com/llvm/llvm-project/commit/bd1324113e90884a4a83d6232ecf0c623e2e113e
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/memprof/memprof_allocator.h
M compiler-rt/lib/memprof/memprof_interceptors.cpp
M compiler-rt/lib/memprof/memprof_internal.h
M compiler-rt/lib/memprof/memprof_malloc_linux.cpp
Log Message:
-----------
[MemProf][NFC] Clean up runtime code (#80581)
Commit: c5bf1f4b8f5ba1912f18729f0726c9227f567c9d
https://github.com/llvm/llvm-project/commit/c5bf1f4b8f5ba1912f18729f0726c9227f567c9d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/AArch64/clamped-trip-count.ll
Log Message:
-----------
[test] Autogen a test for ease of update in forthcoming patch
Commit: 1aafe7605b295bdb6e9951f4ca86390d306152d2
https://github.com/llvm/llvm-project/commit/1aafe7605b295bdb6e9951f4ca86390d306152d2
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/test/Transforms/LoopVectorize/RISCV/short-trip-count.ll
Log Message:
-----------
[test] Regen a test for naming changes
Commit: 69a661cbae10495e9556d195fa683c0100ae299c
https://github.com/llvm/llvm-project/commit/69a661cbae10495e9556d195fa683c0100ae299c
Author: Visoiu Mistrih Francis <890283+francisvm at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
A llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
Log Message:
-----------
[RISCV] Remove CalleeSavedInfo for Zcmp/save-restore-libcalls registers (#79535)
Registers that are pushed/popped by Zcmp or libcalls have pre-defined
frame indices that are never allocated in MachineFrameInfo. They're
being used throughout PEI, but the rest of codegen doesn't work that way
and expects each frame index to be a valid index in MFI.
This patch keeps it local to PEI and removes them from the
CalleeSavedInfo list at the end of the pass.
Before this pass, any MIR testing post-PEI is broken and asserts (see
issue #79491).
Commit: cf0773fb14e18e97de3f66b4f21f286ca4f97eae
https://github.com/llvm/llvm-project/commit/cf0773fb14e18e97de3f66b4f21f286ca4f97eae
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/Target/TargetSchedule.td
Log Message:
-----------
[TableGen][NFC] Remove EponymousProcResourceKind (#80812)
We can use `!cast` to cast `NAME` to `ProcResourceKind`.
Commit: c7fa25f0b2398f7037af6e10b18456b69178f7c5
https://github.com/llvm/llvm-project/commit/c7fa25f0b2398f7037af6e10b18456b69178f7c5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/test/MC/RISCV/elf-flags.s
Log Message:
-----------
[RISCV] Set the RVC bit in the ELF EFlags for C or Zca. (#80913)
Commit: 8ea7f1d20ad8ab8c381800eefda948d85c6860cc
https://github.com/llvm/llvm-project/commit/8ea7f1d20ad8ab8c381800eefda948d85c6860cc
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M bolt/lib/Passes/BinaryPasses.cpp
Log Message:
-----------
[BOLT][NFCI] Keep instruction annotations (#80382)
We used to delete most instruction annotations before code emission. It
was done to release memory taken by annotations and to reduce overall
memory consumption. However, since the implementation of annotations has
moved to using existing instruction operands, the memory overhead
associated with them has reduced drastically. I measured that savings
are less than 0.5% on large binaries and processing time is just
slightly reduced if we keep them. Additionally, I plan to use
annotations in pre-emission passes for the Linux kernel rewriter.
Commit: 8ae048507086cc3a2ceb6974506d3048c516a726
https://github.com/llvm/llvm-project/commit/8ae048507086cc3a2ceb6974506d3048c516a726
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/docs/TableGen/BackEnds.rst
M llvm/test/TableGen/generic-tables-instruction.td
M llvm/utils/TableGen/CodeGenTarget.cpp
M llvm/utils/TableGen/CodeGenTarget.h
M llvm/utils/TableGen/SearchableTableEmitter.cpp
Log Message:
-----------
[TableGen] Extend direct lookup to instruction values in generic tables. (#80486)
Currently, for some tables involving a single primary key field which is
integral and densely numbered, a direct lookup is generated rather than
a binary search. This patch extends the direct lookup function
generation to instructions, where the integral value corresponds to the
instruction's enum value.
While this isn't as common as for other tables, it does occur in at
least one downstream backend and one in-tree backend.
Added a unit test and minimally updated the documentation.
Commit: adbf21f12b3069b2554efb39f2e92c6cf6f24940
https://github.com/llvm/llvm-project/commit/adbf21f12b3069b2554efb39f2e92c6cf6f24940
Author: Boian Petkantchin <boian.petkantchin at amd.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
A mlir/include/mlir/Dialect/Func/Extensions/MeshShardingExtensions.h
M mlir/include/mlir/Dialect/Mesh/IR/MeshOps.h
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.h
M mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterface.td
A mlir/include/mlir/Dialect/Mesh/Interfaces/ShardingInterfaceImpl.h
M mlir/include/mlir/Dialect/Mesh/Transforms/Passes.td
M mlir/include/mlir/Dialect/Mesh/Transforms/Spmdization.h
M mlir/lib/Dialect/Func/Extensions/AllExtensions.cpp
M mlir/lib/Dialect/Func/Extensions/CMakeLists.txt
A mlir/lib/Dialect/Func/Extensions/MeshShardingExtensions.cpp
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
M mlir/lib/Dialect/Mesh/Transforms/ShardingPropagation.cpp
M mlir/lib/Dialect/Mesh/Transforms/Spmdization.cpp
M mlir/lib/Dialect/Tosa/IR/ShardingInterfaceImpl.cpp
M mlir/test/Dialect/Mesh/resharding-spmdization.mlir
A mlir/test/Dialect/Mesh/spmdization.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][mesh] Add spmdization pass (#80518)
Add a pass that converts a function that has sharding annotations into
SPMD form.
Commit: b0785cd1cbf97dbd4eb39647ff22771ef0a7cfea
https://github.com/llvm/llvm-project/commit/b0785cd1cbf97dbd4eb39647ff22771ef0a7cfea
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
A llvm/test/CodeGen/ARM/GlobalISel/select-const.mir
Log Message:
-----------
[GlobalISel][ARM] Support missing case for G_CONSTANT (#80555)
Global Instruction Selector could not select the code:
%0:gprb(s32) = G_CONSTANT i32 -1
In DAG selector the similar code is selected to the instruction MVNi
using custom operand `mod_imm_not`. Changing its definition from
`PatLeaf` to `ImmLeaf` and providing counterpart for `imm_not_XFORM`
make the relevant rule available for GlobalISel too.
Commit: 966f78bdf849d1ae4ce205f93f5967df71e95f4c
https://github.com/llvm/llvm-project/commit/966f78bdf849d1ae4ce205f93f5967df71e95f4c
Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/test/Transforms/InstCombine/fdiv.ll
Log Message:
-----------
[InstCombine] Resolve TODO: nnan nsz X / -0.0 -> copysign(inf, X) (#79766)
Commit: 86fa21e93efe6d8079d202bf30e7e8db66cc32a0
https://github.com/llvm/llvm-project/commit/86fa21e93efe6d8079d202bf30e7e8db66cc32a0
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp
Log Message:
-----------
[mlir] Fix -Wunused-function in ShardingInterface.cpp (NFC)
llvm-project/mlir/lib/Dialect/Mesh/Interfaces/ShardingInterface.cpp:522:1:
error: unused function 'isValueCompatibleWithFullReplicationSharding' [-Werror,-Wunused-function]
isValueCompatibleWithFullReplicationSharding(Value value,
^
1 error generated.
Commit: 679d0d70295cab1f3692fc1919299d8c16070863
https://github.com/llvm/llvm-project/commit/679d0d70295cab1f3692fc1919299d8c16070863
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[RISCV][Docs] Fix link to Zjpm spec in RISCVUsage.rst.
Commit: c5e5661591a90094eeb5831de86d701419c74f07
https://github.com/llvm/llvm-project/commit/c5e5661591a90094eeb5831de86d701419c74f07
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/Headers/cpuid.h
Log Message:
-----------
[X86] Add missing MACROs in cpuid.h (#80815)
Relate gcc file:
https://github.com/gcc-mirror/gcc/blob/master/gcc/config/i386/cpuid.h
Commit: 8c84096da195ae38336ba9aa700dc35e567157ba
https://github.com/llvm/llvm-project/commit/8c84096da195ae38336ba9aa700dc35e567157ba
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/Opcodes.td
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp] Fix initializing _Complex values from DeclRefExpr
See the comment I added. When initializing a complex value from a
DeclRefExpr, we need to manually copy both array elements.
This adds some unfortunate code duplication that I'm still pondering
on how to get rid of best.
Commit: 28b82075ff3e58ba9c6959a585d3d0fc5d0325e5
https://github.com/llvm/llvm-project/commit/28b82075ff3e58ba9c6959a585d3d0fc5d0325e5
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp] Support ImplicitValueInitExpr for complex types
Initialize both elements to 0, once again.
Commit: cb7561ac5a8445f5c526c949efd50f45f55bb089
https://github.com/llvm/llvm-project/commit/cb7561ac5a8445f5c526c949efd50f45f55bb089
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Log Message:
-----------
[Sched] Add MacroFusion mutation if fusions are not empty (#72227)
We can get the fusions list by `getMacroFusions` and if it is not
empty, then we will add the MacroFusion mutation automatically.
Commit: ea4f44e85f7ca884d42b9b12bd13bab47c3e5d3c
https://github.com/llvm/llvm-project/commit/ea4f44e85f7ca884d42b9b12bd13bab47c3e5d3c
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Log Message:
-----------
[RISCV] Remove unused variable 'ST' in RISCVTargetMachine.cpp (NFC)
llvm-project/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp:358:27:
error: unused variable 'ST' [-Werror,-Wunused-variable]
const RISCVSubtarget &ST = C->MF->getSubtarget<RISCVSubtarget>();
^
1 error generated.
Commit: 9bda1de0b6096d26e87fed18cb681cc3e5b8319a
https://github.com/llvm/llvm-project/commit/9bda1de0b6096d26e87fed18cb681cc3e5b8319a
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir
Log Message:
-----------
[TwoAddressInstruction] Propagate undef flags for partial defs (#79286)
If part of a register (lowered from REG_SEQUENCE) is undefined then we
should propagate undef flags to uses of those lanes. This is only
performed when live intervals are present as it requires live intervals
to correctly match uses to defs, and the primary goal is to allow
precise computation of subrange intervals.
Commit: e7c0e59bbcf713d09ca7a09cd513399d66a94ca5
https://github.com/llvm/llvm-project/commit/e7c0e59bbcf713d09ca7a09cd513399d66a94ca5
Author: Job Noorman <jnoorman at igalia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Fix crash for relocs in data sections against ABS symbols (#76026)
Fixes #75771
Commit: 93962ea1176b91239496378e7141a44dc95a5efd
https://github.com/llvm/llvm-project/commit/93962ea1176b91239496378e7141a44dc95a5efd
Author: Björn Pettersson <bjorn.a.pettersson at ericsson.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/docs/Passes.rst
Log Message:
-----------
[docs][passes] Update documentation of Analysis and Transform Passes (#80835)
- Added a warning about the pass list being incomplete (and hint about
"opt -print-passes" listing known passes).
- Removed legacy PM example involving "opt -analyze".
- print-function and print-module does not exist with those names in the
new PM. Since the document has been updated to reflect the new PM names
earlier, those names were changed into referring to function(print) and
module(print) instead.
- Resolved some FIXME:s around strip* passes.
Commit: 9a028afdd655f8e378819e4125292d973985f3f4
https://github.com/llvm/llvm-project/commit/9a028afdd655f8e378819e4125292d973985f3f4
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Transform/IR/TransformInterfaces.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Dialect/Transform/IR/TransformInterfaces.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Log Message:
-----------
[mlir][IR][NFC] `Listener::notifyMatchFailure` returns `void` (#80704)
There are two `notifyMatchFailure` methods: one in the rewriter and one
in the listener. The one in the rewriter notifies the listener and
returns "failure" for convenience. The one in the listener should not
return anything; it is just a notification. It can currently be abused
to return "success" from the rewriter function. That would be a
violation of the rewriter API rules.
Also make sure that the listener is always notified about match
failures, not just with `NDEBUG`. The current implementation is
consistent: one `notifyMatchFailure` overload notifies only in debug
mode and another one notifies all the time.
Commit: 2ad6fd6735150e44e2170368968c0006df4d8387
https://github.com/llvm/llvm-project/commit/2ad6fd6735150e44e2170368968c0006df4d8387
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
Log Message:
-----------
[RISCV][NFC] Move SFB pseudos and patterns to RISCVInstrInfoSFB.td (#80945)
To make the structure of TableGen files clear.
Commit: 7d508eb5d38f4bbbab4230a666d9e742e271af61
https://github.com/llvm/llvm-project/commit/7d508eb5d38f4bbbab4230a666d9e742e271af61
Author: Carl Ritson <carl.ritson at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
R llvm/test/CodeGen/AMDGPU/pal-metadata-3.0-callable.ll
Log Message:
-----------
Revert "[AMDGPU] Add pal metadata 3.0 support to callable pal funcs (#67104)"
This reverts commit d6c7253d32e4bdff619c39708170f1c1fa01ff95.
Change causing CTS failures due to incomplete metadata.
Commit: fff86c6111b6d3ed68a8ea57ab5e7d3d716472c6
https://github.com/llvm/llvm-project/commit/fff86c6111b6d3ed68a8ea57ab5e7d3d716472c6
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir
M mlir/test/Dialect/ArmSME/invalid.mlir
M mlir/test/Dialect/ArmSME/outer-product-fusion.mlir
M mlir/test/Dialect/ArmSME/roundtrip.mlir
A mlir/test/Integration/Dialect/Vector/CPU/ArmSME/test-outerproduct-i8i8i32.mlir
Log Message:
-----------
[mlir][ArmSME] Support 4-way widening outer products (#79288)
This patch introduces support for 4-way widening outer products. This
enables the fusion of 4 'arm_sme.outerproduct' operations that are
chained via the accumulator into single widened operations.
Changes:
- Adds the following operations:
- smopa_4way, smops_4way
- umopa_4way, umops_4way
- sumopa_4way, sumops_4way
- sumopa_4way, sumops_4way
- Implements conversions for the above ops to intrinsics in ArmSMEToLLVM.
- Extends 'arm-sme-outer-product' pass.
For a detailed description of these operations see the
'arm_sme.smopa_4way' description.
Commit: 67402fe5e4bf7a706d47bc106113f599a8d59947
https://github.com/llvm/llvm-project/commit/67402fe5e4bf7a706d47bc106113f599a8d59947
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M flang/include/flang/Lower/ConvertCall.h
M flang/include/flang/Optimizer/Builder/MutableBox.h
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Optimizer/Builder/MutableBox.cpp
M flang/test/Lower/HLFIR/function-return-as-expr.f90
Log Message:
-----------
[flang] Do not move finalized function results in lowering (#80683)
Fortran requires finalizing function results when the result type have
final procedures.
Lowering was unconditionally "moving" function results into values
"hlfir.expr". This is not correct when the results are finalized because
it means the function result storage will be used after the hlfir.expr.
Only move function results that are not finalized.
Commit: 1b87ebce924e507cbc27c2e0dc623941d16388c9
https://github.com/llvm/llvm-project/commit/1b87ebce924e507cbc27c2e0dc623941d16388c9
Author: Yi Kong <yikong at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-objcopy.rst
M llvm/include/llvm/ObjCopy/CommonConfig.h
M llvm/lib/ObjCopy/ConfigManager.cpp
M llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
A llvm/test/tools/llvm-objcopy/ELF/prefix-symbols-remove.test
M llvm/tools/llvm-objcopy/ObjcopyOptions.cpp
M llvm/tools/llvm-objcopy/ObjcopyOpts.td
Log Message:
-----------
[llvm-objcopy] Add --remove-symbol-prefix (#79415)
Commit: e1d564ac130fb6ec14d1e237a123373d64249e55
https://github.com/llvm/llvm-project/commit/e1d564ac130fb6ec14d1e237a123373d64249e55
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-exegesis/X86/latency/middle-half.s
Log Message:
-----------
[llvm-exegesis] Allow retries on flaky middle half test
The middle half repetition mode test sometimes fails on the avx512
buildbots due to a negative value being produced. This needs more
investigation, but add a retry count temporarily to alleviate
false-positive errors on the buildbots.
This is being tracked in #80957.
Commit: 0f439f374f9cec73466c5166b9a8764214a74069
https://github.com/llvm/llvm-project/commit/0f439f374f9cec73466c5166b9a8764214a74069
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
A flang/test/HLFIR/as_expr-codegen-polymorphic.fir
M flang/test/HLFIR/bufferize-poly-expr.fir
Log Message:
-----------
[flang] Fix hlfir.as_expr codegen for polymorphic entities (#80824)
https://github.com/llvm/llvm-project/pull/80683 revealed that
hlfir.as_expr was propagating the temporary buffer for polymorphic
values as an allocatable while codegen later expects to be working with
fir.box/fir.class but not fir.ref<box/class> when processing the
operations using the hlfir.as_expr result.
Dereference the temporary allocatable as soon as it is created.
Commit: 88c830a1a5687bec597ca947159e4dd9a3f2ac2d
https://github.com/llvm/llvm-project/commit/88c830a1a5687bec597ca947159e4dd9a3f2ac2d
Author: Thomas Preud'homme <thomas.preudhomme at arm.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp
M mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir
Log Message:
-----------
[TOSA] Fix avgpool2d accum in wider type (#80849)
Truncate result of avgpool when accumulation is done in a wider type
than the result element type, such as when doing a f16 avgpool2d with a
f32 accumulator type.
Commit: f8562e245c0c3ebaa8c75575fac566497a0c9245
https://github.com/llvm/llvm-project/commit/f8562e245c0c3ebaa8c75575fac566497a0c9245
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M flang/lib/Lower/OpenMP.cpp
Log Message:
-----------
[flang][OpenMP][NFC] Further refactoring for `genOpWithBody` & (#80839)
`createBodyOfOp`
This refactors the arguments to the above functions in 2 ways:
- Combines the 2 structs of arguments into one since they were almost
identical.
- Replaces the `args` argument with a callback to a rebion-body
generation function. This is a preparation for delayed privatization as
we will need different callbacks for ws loops and parallel ops with
delayed privatization.
Commit: 365bf43b8b290ab64b5b82879bc9d1dfdd5d6aa9
https://github.com/llvm/llvm-project/commit/365bf43b8b290ab64b5b82879bc9d1dfdd5d6aa9
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/Transforms/LoopStrengthReduce/Power/incomplete-phi.ll
Log Message:
-----------
[LSR] Regenerate test checks (NFC)
Check output IR instead of debug output. The debug output will
change in an upcoming patch in an irrecoverable way.
Commit: e60c4b61f8bab25a137a481e4d2d3dbfa656807b
https://github.com/llvm/llvm-project/commit/e60c4b61f8bab25a137a481e4d2d3dbfa656807b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Log Message:
-----------
[InstCombine] Change order of checks for dominating conditions (NFC)
Check whether the condition is in the expected format before
performing more expensive dominator checks.
Commit: bec7181d5b9d1828129d78d440fd9e02d5cb63e8
https://github.com/llvm/llvm-project/commit/bec7181d5b9d1828129d78d440fd9e02d5cb63e8
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
A llvm/test/Transforms/LoopIdiom/pr80954.ll
Log Message:
-----------
[SCEVExpander] Don't use recursive expansion for ptr IV inc
Similar to the non-ptr case, directly create the getelementptr
instruction. Going through expandAddToGEP() no longer makes sense
with opaque pointers, where generating the necessary instruction
is trivial.
This avoids recursive expansion of (the SCEV of) StepV while the
IR is in an inconsistent state, in particular with an incomplete
IV phi node, which utilities may not be prepared to deal with.
Fixes https://github.com/llvm/llvm-project/issues/80954.
Commit: eeb60e335e4fecb9ce3ed62cf081568cecf1d4ac
https://github.com/llvm/llvm-project/commit/eeb60e335e4fecb9ce3ed62cf081568cecf1d4ac
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU] Remove unused multiclass
Commit: 7760006d8d39e7624601936e2b1b428d850726b8
https://github.com/llvm/llvm-project/commit/7760006d8d39e7624601936e2b1b428d850726b8
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/CMakeLists.txt
A libc/src/stdbit/stdc_trailing_ones_uc.cpp
A libc/src/stdbit/stdc_trailing_ones_uc.h
A libc/src/stdbit/stdc_trailing_ones_ui.cpp
A libc/src/stdbit/stdc_trailing_ones_ui.h
A libc/src/stdbit/stdc_trailing_ones_ul.cpp
A libc/src/stdbit/stdc_trailing_ones_ul.h
A libc/src/stdbit/stdc_trailing_ones_ull.cpp
A libc/src/stdbit/stdc_trailing_ones_ull.h
A libc/src/stdbit/stdc_trailing_ones_us.cpp
A libc/src/stdbit/stdc_trailing_ones_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/CMakeLists.txt
A libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_ui_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_ul_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_ull_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp
Log Message:
-----------
[libc][stdbit] implement stdc_trailing_ones (C23) (#80459)
Commit: 670c2529bb97f53a5b73e1eedb736ac6e070e1d9
https://github.com/llvm/llvm-project/commit/670c2529bb97f53a5b73e1eedb736ac6e070e1d9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] Use DAGCombiner::SimplifyDemandedBits wrappers with default (all) DemandedElts. NFC.
Don't call TLI.SimplifyDemandedVectorElts directly from every SimplifyDemandedBits call, use the more expressive wrappers instead first.
This reduces the number of places we call TLI.SimplifyDemandedVectorElts and CommitTargetLoweringOpt to make it easier to track.
Part of the work to process DAG nodes in topological order.
Commit: c2a91d4a33af49cd77c6d6ec731ae25538f746b8
https://github.com/llvm/llvm-project/commit/c2a91d4a33af49cd77c6d6ec731ae25538f746b8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/combine-movmsk-avx.ll
Log Message:
-----------
[X86] combine-movmsk-avx.ll - add full AVX1/AVX2 VTEST/MOVMSK test coverage
Test all combos of avx1/avx2 and prefer-movmsk-over-vtest
Commit: 89ad31fd9356e2f999eb63fbac88d1338b8b3592
https://github.com/llvm/llvm-project/commit/89ad31fd9356e2f999eb63fbac88d1338b8b3592
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/Assembler/DIDefaultTemplateParam.ll
M llvm/test/Transforms/Attributor/ArgumentPromotion/pr33641_remove_arg_dbgvalue.ll
M llvm/test/Transforms/Scalarizer/dbginfo.ll
Log Message:
-----------
[RemoveDIs][DebugInfo] Perform some pre-turn-on test maintenence (#80885)
As we'll hopefully move away from using intrinsics for debug-info
shortly, this commit stabilizes a few tests to avoid spurious changes in
the process. Briefly, there are differences in output when we don't use
intrinsics that we're going to suppress in case we have to revert, these
are:
* The attributor test gets different attributes for the dbg.value
intrinsic because it's not present during optimisation. This has no
functional effect and there's no need to test for it.
* The Scalarizer test exposes a "debug-info affects codegen" problem,
but fixing it is fiddly (updating 20 IRBuilder object calls). Pin this
test to not change with RemoveDIs, we can relax it later and get the
correct behaviour.
* DIDefaultTemplateParam.ll tests for explicit metadata node numbers
which is generally bad. Add explicit node-number capturing CHECK lines.
Commit: fb581adbdd2264b3ab28394b5e8539d4d2c05fbd
https://github.com/llvm/llvm-project/commit/fb581adbdd2264b3ab28394b5e8539d4d2c05fbd
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/Transforms/SROA/select-gep.ll
Log Message:
-----------
[SROA] Add tests with gep of index select (NFC)
Commit: af6656c375b8aa9c9156575f7c0ac678a57070d5
https://github.com/llvm/llvm-project/commit/af6656c375b8aa9c9156575f7c0ac678a57070d5
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Descriptor.cpp
Log Message:
-----------
[clang][Interp][NFC] Fix moveArrayTy byte offset
We need to account for the InitMapPtr here. This is NFC right now since
no test is affected by it.
Commit: df856e49773d0569741117cfd856818b7644ea85
https://github.com/llvm/llvm-project/commit/df856e49773d0569741117cfd856818b7644ea85
Author: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
Log Message:
-----------
[SLP]Add GEP cost estimation for gathered loads.
When doing estimation for vectorization of gathered loads, need to
estimate the cost of the pointer (vectorization), as it is done for the
actual vectorized loads. Otherwise may be too optimistic about the cost
of the gathered loads.
Reviewers: preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/80867
Commit: 61c7a69fa0c020e92b1b10882d5d2957f3b8da21
https://github.com/llvm/llvm-project/commit/61c7a69fa0c020e92b1b10882d5d2957f3b8da21
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp] Fix sizeof of reference types
Commit: a97ff2d35af0a5c640c20abf4215c08e0e69aa41
https://github.com/llvm/llvm-project/commit/a97ff2d35af0a5c640c20abf4215c08e0e69aa41
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/test/AST/Interp/literals.cpp
Log Message:
-----------
[clang][Interp] Add missing static_assert message
This breaks builders:
https://lab.llvm.org/buildbot/#/builders/139/builds/58960
Commit: d109f94f29e2bc2fc31c8870b1e41759f524fe77
https://github.com/llvm/llvm-project/commit/d109f94f29e2bc2fc31c8870b1e41759f524fe77
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll
M llvm/test/DebugInfo/X86/debug_value_list_selectiondag.ll
M llvm/test/Transforms/IROutliner/legal-debug.ll
M llvm/test/Transforms/InstCombine/cast-mul-select.ll
M llvm/test/Transforms/InstCombine/debuginfo_add.ll
M llvm/test/Transforms/InstCombine/sink-instruction-introduces-unnecessary-poison-value.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] Re-enable some test coverage
We disabled these extra-special RUNlines due to unexpected interactions
between the various things we've been fixing. Re-enable them (they'll run
on the llvm-new-debug-iterators buildbot) as they all now pass.
Commit: f37d81f8a3e1475f30bec63bfc0b703fc9509d7c
https://github.com/llvm/llvm-project/commit/f37d81f8a3e1475f30bec63bfc0b703fc9509d7c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstSimplify/cast-unsigned-icmp-cmp-0.ll
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch] Add a matching helper `m_ElementWiseBitCast`. NFC. (#80764)
This patch introduces a matching helper `m_ElementWiseBitCast`, which is
used for matching element-wise int <-> fp casts.
The motivation of this patch is to avoid duplicating checks in
https://github.com/llvm/llvm-project/pull/80740 and
https://github.com/llvm/llvm-project/pull/80414.
Commit: 6cb66ee5f8827040c5178fc2a479c138f4838eca
https://github.com/llvm/llvm-project/commit/6cb66ee5f8827040c5178fc2a479c138f4838eca
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Metadata.cpp
Log Message:
-----------
[RemoveDIs][DebugInfo] Handle RAUW from dead constants (#80837)
Ensure that when a constant value dies, all ValueAsMetadata uses of that
constant in a DebugValueUser will be replaced with a PoisonValue instead
of a nullptr. This has little visible effect currently, as any nullptr metadata
uses in a DebugValueUser would be converted to an empty MDNode in
the end anyway, but this patch adds an assert that would be triggered by
two existing tests without the functional component of this patch:
llvm/test/Transforms/Inline/delete-function-with-metadata-use.ll
llvm/test/DebugInfo/X86/array2.ll
Commit: accbcb9578959b86cadc901a57ffa4a0c3f23ead
https://github.com/llvm/llvm-project/commit/accbcb9578959b86cadc901a57ffa4a0c3f23ead
Author: Dmitri Gribenko <gribozavr at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-objcopy/ELF/prefix-symbols-remove.test
Log Message:
-----------
[llvm-objcopy][test] Use actual temporary file names in the test for --remove-symbol-prefix
Commit: b0c6fc81fe132f20eed38bd836620dfcb5ac17e9
https://github.com/llvm/llvm-project/commit/b0c6fc81fe132f20eed38bd836620dfcb5ac17e9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeStmtGen.cpp
M clang/test/SemaCXX/cxx20-using-enum.cpp
Log Message:
-----------
[clang][Interp] Ignore UsingEnumDecls
We previously aborted compilation when seeing one of them. Ignore
them instead, they have no effect on the generated bytecode.
Commit: 7ab0a871431375cb966b0653b9f5caaba15cb6d9
https://github.com/llvm/llvm-project/commit/7ab0a871431375cb966b0653b9f5caaba15cb6d9
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/free-inversion.ll
Log Message:
-----------
[InstCombine] Try to freely invert phi nodes (#80804)
This patch tries to invert phi nodes if all incoming values are either
constants or nots.
Commit: 0aacd44a4698da012ee0704815123b28f2a06d0f
https://github.com/llvm/llvm-project/commit/0aacd44a4698da012ee0704815123b28f2a06d0f
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
M llvm/test/Transforms/SpeculativeExecution/PR46267.ll
Log Message:
-----------
[RemoveDIs][DebugInfo] Hoist DPValues in SpeculativeExecution (#80886)
This patch modifies `SpeculativeExecutionPass::considerHoistingFromTo`
to treat DPValues the same way that it treats debug intrinsics, which is
to hoist them iff all of their instruction operands within the FromBlock
are also being hoisted. This is probably not the ideal behaviour, which
would be to not hoist debug info at all in this case, but this patch
simply ensures that DPValue behaviour is consistent with debug intrinsic
behaviour rather than trying to create new functional changes.
Commit: de7beb06e7b3864feec165f84f02e24f6c18870a
https://github.com/llvm/llvm-project/commit/de7beb06e7b3864feec165f84f02e24f6c18870a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
Log Message:
-----------
[DAG] ExpandShiftWithKnownAmountBit - reduce number of repeated getOpcode / getOperand calls. NFC.
Commit: 50d38cf934861205768de9e3cf32827e73764001
https://github.com/llvm/llvm-project/commit/50d38cf934861205768de9e3cf32827e73764001
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants.cpp - update comment to describe all the constant load ops performed by the pass
Commit: 4e58f03f298eb5c74877942c1c68911341c678bd
https://github.com/llvm/llvm-project/commit/4e58f03f298eb5c74877942c1c68911341c678bd
Author: Shourya Goel <114918019+Sh0g0-1758 at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/test/Frontend/verify.c
Log Message:
-----------
[Clang] Fix : More Detailed "No expected directives found" (#78338)
Updated the error message to use the proper prefix when
no expected directives are found by changing the hard coded expected in
the message to a dynamic value in two error messages.
Fixes #58290
Commit: c76b0eb898d1e5edc416b658a6902163d64db1ce
https://github.com/llvm/llvm-project/commit/c76b0eb898d1e5edc416b658a6902163d64db1ce
Author: Stephen Tozer <Stephen.Tozer at Sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
M llvm/test/Transforms/SpeculativeExecution/PR46267.ll
Log Message:
-----------
Revert "[RemoveDIs][DebugInfo] Hoist DPValues in SpeculativeExecution (#80886)"
Reverted due to buildbot failures resulting from failed compile due to a
missing brace error that got into the original commit.
This reverts commit 0aacd44a4698da012ee0704815123b28f2a06d0f.
Commit: 52bf531630d19e115d30b4ca46f1ef03b9a724c6
https://github.com/llvm/llvm-project/commit/52bf531630d19e115d30b4ca46f1ef03b9a724c6
Author: Sirraide <74590115+Sirraide at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
Log Message:
-----------
[Clang][Sema] Fix out-of-bounds access (#80978)
Trying to compile a C-style variadic member function with an explicit
object parameter was crashing in Sema because of an out-of-bounds
access.
This fixes #80971.
Commit: 5c84054223102b00cc0dd343a4023e3c6cba42b2
https://github.com/llvm/llvm-project/commit/5c84054223102b00cc0dd343a4023e3c6cba42b2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/OffloadingDesign.rst
M clang/test/Driver/linker-wrapper-image.c
M clang/test/Driver/linker-wrapper.c
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Object/OffloadBinary.cpp
Log Message:
-----------
[LinkerWrapper] Support relocatable linking for offloading (#80066)
Summary:
The standard GPU compilation process embeds each intermediate object
file into the host file at the `.llvm.offloading` section so it can be
linked later. We also use a special section called something like
`omp_offloading_entries` to store all the globals that need to be
registered by the runtime. The linker-wrapper's job is to link the
embedded device code stored at this section and then emit code to
register the linked image and the kernels and globals in the offloading
entry section.
One downside to RDC linking is that it can become quite big for very
large projects that wish to make use of static linking. This patch
changes the support for relocatable linking via `-r` to support a kind
of "partial" RDC compilation for offloading languages.
This primarily requires manually editing the embedded data in the
output object file for the relocatable link. We need to rename the
output section to make it distinct from the input sections that will be
merged. We then delete the old embedded object code so it won't be
linked further. We then need to rename the old offloading section so
that it is private to the module. A runtime solution could also be done
to defer entries that don't belong to the given GPU executable, but this
is easier. Note that this does not work with COFF linking, only the ELF
method for handling offloading entries, that could be made to work
similarly.
Given this support, the following compilation path should produce two
distinct images for OpenMP offloading.
```
$ clang foo.c -fopenmp --offload-arch=native -c
$ clang foo.c -lomptarget.devicertl --offload-link -r -o merged.o
$ clang main.c merged.o -fopenmp --offload-arch=native
$ ./a.out
```
Or similarly for HIP to effectively perform non-RDC mode compilation for
a subset of files.
```
$ clang -x hip foo.c --offload-arch=native --offload-new-driver -fgpu-rdc -c
$ clang -x hip foo.c -lomptarget.devicertl --offload-link -r -o merged.o
$ clang -x hip main.c merged.o --offload-arch=native --offload-new-driver -fgpu-rdc
$ ./a.out
```
One question is whether or not this should be the default behavior of
`-r` when run through the linker-wrapper or a special option. Standard
`-r` behavior is still possible if used without invoking the
linker-wrapper and it guaranteed to be correct.
Commit: 5d8a7318b2192ce8e396ec420f3f4d8f1a07cc10
https://github.com/llvm/llvm-project/commit/5d8a7318b2192ce8e396ec420f3f4d8f1a07cc10
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/InterpBuiltin.cpp
M clang/test/AST/Interp/builtin-functions.cpp
Log Message:
-----------
[clang][Interp] Support __builtin_eh_return_data_regno
Commit: 66d4fe97d8d46195672117797b663c21cf576f33
https://github.com/llvm/llvm-project/commit/66d4fe97d8d46195672117797b663c21cf576f33
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/X86/free-intrinsics.ll
M llvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll
M llvm/test/Analysis/CostModel/free-intrinsics-no_info.ll
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values.ll
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values.ll.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values.ll.funcsig.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values.ll.funcsig.globals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values.ll.funcsig.noglobals.expected
M llvm/test/tools/UpdateTestChecks/update_test_checks/Inputs/various_ir_values.ll.funcsig.transitiveglobals.expected
M llvm/unittests/Transforms/Utils/DebugifyTest.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Final final test-maintenence patch (#80988)
This should be the final portion of shaping-up the test suite to be
ready for turning on non-intrinsic debug-info:
* Pin CostModel tests that expect to see intrinsics in their -debug
output to not use RemoveDIs. This is a spurious test output difference.
* Add 'tail' to a bunch of intrinsics in UpdateTestChecks. We're
cannonicalising intrinsics to be printed with "tail" in RemoveDI
conversion as dbg.values usually pick that up while being optimised.
This is another spurious output difference.
* The "DebugInfoDrop" pass used in the debugify unit-tests happens to
operate inside the pass manager, thus it sees non-intrinsic debug-info.
Update it to correctly drop it.
Commit: d42f3957cea0a8f45d5f3c11db229e2ea1e6d614
https://github.com/llvm/llvm-project/commit/d42f3957cea0a8f45d5f3c11db229e2ea1e6d614
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/test/AST/Interp/switch.cpp
Log Message:
-----------
[clang][Interp][NFC] Convert test to verify=expected,both style
Commit: 7718ac38a0c23597d7d02f0022eb89afe6d1b35f
https://github.com/llvm/llvm-project/commit/7718ac38a0c23597d7d02f0022eb89afe6d1b35f
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/lib/IR/AffineExpr.cpp
Log Message:
-----------
[MLIR] NFC. Fix remaining clang-tidy warnings in AffineExpr.cpp (#80933)
NFC. Fix remaining clang-tidy warnings in AffineExpr.cpp.
Commit: d4a2c7f95297d1865a457955dcf7b679dabb5e0e
https://github.com/llvm/llvm-project/commit/d4a2c7f95297d1865a457955dcf7b679dabb5e0e
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/records.cpp
M clang/test/SemaCXX/cxx1z-copy-omission.cpp
Log Message:
-----------
[clang][Interp] Fix record initialization from temporary in initlist
Commit: 7a71ac2b00cd6ec06c113f8813f085d5ed346ad9
https://github.com/llvm/llvm-project/commit/7a71ac2b00cd6ec06c113f8813f085d5ed346ad9
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/and-fcmp.ll
A llvm/test/Transforms/InstCombine/canonicalize-fcmp-inf.ll
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstCombine/fold-select-fmul-if-zero.ll
Log Message:
-----------
[InstCombine] Canonicalize fcmp with inf (#80986)
This patch canonicalizes floating-point comparisons with inf:
```
fcmp olt X, +inf -> fcmp one X, +inf
fcmp ole X, +inf -> fcmp ord X, 0
fcmp ogt X, +inf -> false
fcmp oge X, +inf -> fcmp oeq X, +inf
fcmp ult X, +inf -> fcmp une X, +inf
fcmp ule X, +inf -> true
fcmp ugt X, +inf -> fcmp uno X, 0
fcmp uge X, +inf -> fcmp ueq X, +inf
fcmp olt X, -inf -> false
fcmp ole X, -inf -> fcmp oeq X, -inf
fcmp ogt X, -inf -> fcmp one X, -inf
fcmp oge X, -inf -> fcmp ord X, 0
fcmp ult X, -inf -> fcmp uno X, 0
fcmp ule X, -inf -> fcmp ueq X, -inf
fcmp ugt X, -inf -> fcmp une X, -inf
fcmp uge X, -inf -> true
```
Alive2: https://alive2.llvm.org/ce/z/FRqqDg
The motivation of this patch is to fix the regression found in
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/199#discussion_r1480974120.
Commit: aeb58844dd6673417ebd7fb83f3acdf7282397fb
https://github.com/llvm/llvm-project/commit/aeb58844dd6673417ebd7fb83f3acdf7282397fb
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/test/ThinLTO/X86/crash_debuginfo.ll
Log Message:
-----------
[RemoveDIs] Don't convert debug-info in bitcode-loading just now (#80865)
We've been building and testing this no-debug-intrinsic work inside of
the pass manager for a while, so that optimisation passes get exercised
and tested when we turn it on. However, by converting to the
non-intrinsic form in the bitcode loader, we accidentally caused all
parts of LLVM to potentially see non-intrinsic debug-info.
Seeing how we're trying to turn things on incrementally, it was a
mistake to go this far this fast: we can instead just focus on enabling
during optimisations for the moment, then all the other parts of LLVM
later.
Commit: c954986fec97ab22a9658b496731d0c280938a64
https://github.com/llvm/llvm-project/commit/c954986fec97ab22a9658b496731d0c280938a64
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/unittests/CodeGen/GlobalISel/GISelUtilsTest.cpp
Log Message:
-----------
[GISel] Add support for scalable vectors in getGCDType (#80307)
This function can be called from buildCopyToRegs where at least one of
the types is a scalable vector type. This function crashed because it
did not know how to handle scalable vector types.
This patch extends the functionality of getGCDType to handle when at
least one of the types is a scalable vector. getGCDType between a fixed
and scalable vector is not implemented since the docstring of the
function explains that getGCDType is used to build MERGE/UNMERGE
instructions and we will never build a MERGE/UNMERGE between fixed and
scalable vectors.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Commit: 4d12292c2ac5caf93cd325a1516cbeacfc87b2e9
https://github.com/llvm/llvm-project/commit/4d12292c2ac5caf93cd325a1516cbeacfc87b2e9
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU] Clean up and share SOP Real instruction definitions (#80990)
The aim is to share definitions for all architectures that have the same
instruction (ignoring renaming) with the same opcode. Overall this saves
about 60 lines of tablegen.
Commit: 4f381afa09c2e60f48a65b10074f8b862a0b6738
https://github.com/llvm/llvm-project/commit/4f381afa09c2e60f48a65b10074f8b862a0b6738
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/or.ll
Log Message:
-----------
[InstCombine] Add additional multi-use test for and/or replacement (NFC)
Commit: 934ba0d59e650644fe69462935982318b265ad2c
https://github.com/llvm/llvm-project/commit/934ba0d59e650644fe69462935982318b265ad2c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
Log Message:
-----------
[InstCombine] Handle missing cases in `visitFCmpInst`
Fiix buildbot failures.
Commit: 8c37e3e64bb1432f771ec4d191837e6b3be5bf0c
https://github.com/llvm/llvm-project/commit/8c37e3e64bb1432f771ec4d191837e6b3be5bf0c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/test/ExecutionEngine/JITLink/RISCV/ELF_relax_align_rvc.s
M llvm/test/ExecutionEngine/JITLink/RISCV/ELF_relax_call_boundary.s
M llvm/test/ExecutionEngine/JITLink/RISCV/ELF_relax_call_rvc.s
Log Message:
-----------
[RISCV] Only set Zca flag for EF_RISCV_RVC in ELFObjectFileBase::getRISCVFeatures(). (#80928)
This code appears to be a hack to set the features to include compressed
instructions if the ELF EFLAGS flags bit is present, but the ELF
attribute for the ISA string is no present or not accurate.
We can't remove the hack because llvm-mc doesn't create ELF attributes
by default so a lot of tests fail to disassembler properly. Using clang
as the assembler does set the attributes.
This patch changes the hack to only set Zca since that is the minimum
implied by the flag. Setting anything else potentially conflicts with
the ISA string containing Zcmp or Zcmt.
JITLink also needs to be updated to recognize Zca in addition to C.
Commit: 79fec2f8ba8ea0b0b1c2f13fb6355cb395e1d3af
https://github.com/llvm/llvm-project/commit/79fec2f8ba8ea0b0b1c2f13fb6355cb395e1d3af
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/AtomicExpandPass.cpp
Log Message:
-----------
[AtomicExpand][RISCV] Call shouldExpandAtomicRMWInIR before widenPartwordAtomicRMW (#80947)
This gives the target a chance to keep an atomicrmw op that is smaller
than the minimum cmpxchg size. This is needed to support the Zabha
extension for RISC-V which provides i8/i16 atomicrmw operations, but
does not provide an i8/i16 cmpxchg or LR/SC instructions.
This moves the widening until after the target requests
LLSC/CmpXChg/MaskedIntrinsic expansion. Once we widen, we call
shouldExpandAtomicRMWInIR again to give the target another chance to
make a decision about the widened operation.
I considered making the targets return AtomicExpansionKind::Expand or a
new expansion kind for And/Or/Xor, but that required the targets to
special case And/Or/Xor which they weren't currently doing.
Commit: 7212b4ae09abe5ba0f9a6ea608ebb6dbfad48b73
https://github.com/llvm/llvm-project/commit/7212b4ae09abe5ba0f9a6ea608ebb6dbfad48b73
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/IR/AsmWriter.cpp
Log Message:
-----------
[RemoveDIs] Remove unused debug-printing facility for DPMarkers
We originally thought that printing the DPMarker pointer after each
instruction was going to be useful, but it turns out it only serves to
generate spurious test output differences now. As it stands, the cannonical
way to debug RemoveDIs metadata is "dumpDbgValues".
Commit: 7e4ac8541dcc389ca8f0d11614e19ea7bae07af7
https://github.com/llvm/llvm-project/commit/7e4ac8541dcc389ca8f0d11614e19ea7bae07af7
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
Log Message:
-----------
[Flang] Use specific symbol rather than generic symbol as procInterface to declare procedure pointer. (#80738)
Flang crashes when lowering the type of `p1` with the following code.
The problem is when it sets up the `procInterface`, it uses the generic
symbol `int`, not the specific `int`. This PR is to correct that.
```
INTERFACE Int
integer FUNCTION Int(arg)
integer :: arg
END FUNCTION
END INTERFACE
integer :: res
procedure(int), pointer :: p1
p1 => int
res = p1(4)
end
```
Commit: ab92f6274b7c3a4b4445d47017bc481aa919545f
https://github.com/llvm/llvm-project/commit/ab92f6274b7c3a4b4445d47017bc481aa919545f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[workflows] Fix libclc CI tests (#80942)
This was broken by 1a6426067fb33a8a789978f6e229108787a041be.
Commit: 65bf93dd7b4cfe96b549fd8248455ba4869ba27c
https://github.com/llvm/llvm-project/commit/65bf93dd7b4cfe96b549fd8248455ba4869ba27c
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/or-xor.ll
M llvm/test/Transforms/InstCombine/or.ll
Log Message:
-----------
[InstCombine] Clean up bitwise folds without one-use check (#80587)
This patch removes some bitwise folds that fail to check the one-use
constraint on the operands.
See also the comments
https://github.com/llvm/llvm-project/pull/77231#issuecomment-1904090035.
Commit: bb531c9a0068a078c5bbe95298769b235aa1ad75
https://github.com/llvm/llvm-project/commit/bb531c9a0068a078c5bbe95298769b235aa1ad75
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineModuleInfo.h
M llvm/lib/CodeGen/MachineModuleInfo.cpp
M llvm/lib/CodeGen/MachinePassManager.cpp
M llvm/tools/llc/NewPMDriver.cpp
M llvm/unittests/CodeGen/PassManagerTest.cpp
M llvm/unittests/MIR/PassBuilderCallbacksTest.cpp
Log Message:
-----------
[NewPM/Codegen] Move MachineModuleInfo ownership outside of analysis (#80937)
With the legacy pass manager, MachineModuleInfoWrapperPass owned the
MachineModuleInfo used in the codegen pipeline. It can do this since
it's an ImmutablePass that doesn't get invalidated.
However, with the new pass manager, it is legal for the
ModuleAnalysisManager to clear all of its analyses, regardless of if the
analysis does not want to be invalidated. So we must move ownership of
the MachineModuleInfo outside of the analysis (this is similar to
PassInstrumentation). For now, make the PassBuilder user register a
MachineModuleAnalysis that returns a reference to a MachineModuleInfo
that the user owns. Perhaps we can find a better place to own the
MachineModuleInfo to make using the codegen pass manager less cumbersome
in the future.
Commit: 5a83bccb35d6b0e6914b52af6db067aa01dd3efb
https://github.com/llvm/llvm-project/commit/5a83bccb35d6b0e6914b52af6db067aa01dd3efb
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/tls-models.ll
Log Message:
-----------
[X86] Fix lowering TLS under darwin large code model (#80907)
OpFlag and WrapperKind should be chosen consistently with each other in
regards to PIC, otherwise we hit asserts later on.
Broken by c04a05d8.
Fixes #80831.
Commit: eaab6abd79bf1a377bf034e1cf652a93d10b45fb
https://github.com/llvm/llvm-project/commit/eaab6abd79bf1a377bf034e1cf652a93d10b45fb
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
A llvm/test/tools/llc/new-pm/pipeline.mir
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[llc] Respect --print-pipeline-passes when using -passes (#80940)
Commit: c1f7f4df01f48e771e501ea14fbef80a23c0e700
https://github.com/llvm/llvm-project/commit/c1f7f4df01f48e771e501ea14fbef80a23c0e700
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
R libc/src/__support/FPUtil/XFloat.h
Log Message:
-----------
[libc][NFC] Remove dead code (#81005)
Commit: e71a5f54d86be3ddf66d4a4e53d5083ef7f7a118
https://github.com/llvm/llvm-project/commit/e71a5f54d86be3ddf66d4a4e53d5083ef7f7a118
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/Register.h
Log Message:
-----------
[NFC] Typo in Register.h
Commit: 34f61cfa6656acffc1a969a21c934c24ad0073c3
https://github.com/llvm/llvm-project/commit/34f61cfa6656acffc1a969a21c934c24ad0073c3
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/test/Transforms/MergeFunc/mergefunc-preserve-debug-info.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] Instrument MergeFunctions for DPValues (#80974)
The MergeFunctions pass has a "preserve some debug-info" mode that tries
to preserve parameter values. This patch generalises its decision-making
so that it applies to both debug-info stored in intrinsics, and
debug-info stored in DPValue objects. For the most part this involves
using a generic lambda and applying it to each type of object.
(Normally we avoid debug-info affecting the code generated, but this is
hidden behind a command line switch, so won't usually be encountered by
users).
Note that this diff is messy, but that's because I'm hoisting some code
into lambdas. The actual decision making processes here are identical.
Commit: e28ca2dd46c137fd33dd327aed1afb1e66a32908
https://github.com/llvm/llvm-project/commit/e28ca2dd46c137fd33dd327aed1afb1e66a32908
Author: Artem Tyurin <artem.tyurin at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M libc/src/stdio/printf_core/converter.cpp
M libc/src/stdio/printf_core/int_converter.h
M libc/src/stdio/printf_core/parser.h
M libc/test/src/stdio/printf_core/converter_test.cpp
M libc/test/src/stdio/sprintf_test.cpp
Log Message:
-----------
[libc] Support C23 'b' (binary) modifier in printf (#80851)
Reference: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n2612.pdf.
Fixes https://github.com/llvm/llvm-project/issues/80727.
Commit: bcc1635c7f8cf25c05ca9ef1f4995ad3e01ddda4
https://github.com/llvm/llvm-project/commit/bcc1635c7f8cf25c05ca9ef1f4995ad3e01ddda4
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/docs/math/index.rst
Log Message:
-----------
[libc] Enable float128 entrypoints on aarch64 and riscv64. (#80682)
Commit: 9eed89908cc906850ef9c6a97ed7a5642ecd6599
https://github.com/llvm/llvm-project/commit/9eed89908cc906850ef9c6a97ed7a5642ecd6599
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
A llvm/test/ThinLTO/X86/memprof-import-fix.ll
Log Message:
-----------
[MemProf] Handle empty stack context during ThinLTO cloning (#81008)
Fix for assert after PR#78264.
Handle the case where the MIB context is empty after skipping the
callsite context, because the callsite context is actually longer than
the MIB context. Presumably this happened as a result of inlining, but
in theory the metadata should have been replaced with an attribute in
that case. Need to investigate why this is occuring, but for now handle
this gracefully to fix the build regression.
Commit: 7c16cb6b3361ff4217004d0cc43f158dea221620
https://github.com/llvm/llvm-project/commit/7c16cb6b3361ff4217004d0cc43f158dea221620
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir-opt][nfc] Remove dead function decls
This removes 3 dead function decls from mlir-opt:
- registerTestLowerToNVVM - recently removed in #75775 when NVVM was
productized.
- registerTestPreparationPassWithAllowedMemrefResults - removed in
D90778 (f7bc56826616).
- registerTestGenericIRVisitorsInterruptPass - added in D116230
(8067ced144a2) but never existed. Pass is registered by
registerTestGenericIRVisitorsPass.
Commit: b0b0bf6d579f26962ac29592feaacd54ae04b60d
https://github.com/llvm/llvm-project/commit/b0b0bf6d579f26962ac29592feaacd54ae04b60d
Author: YAMAMOTO Takashi <yamamoto at midokura.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
Log Message:
-----------
WebAssemblyTargetMachine.cpp: fix a typo in a message (#80958)
Commit: 347ab99a5c6d096beb7378794c6255dca2a866e6
https://github.com/llvm/llvm-project/commit/347ab99a5c6d096beb7378794c6255dca2a866e6
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/OffloadingDesign.rst
Log Message:
-----------
[Clang][Docs] Fix trailing whitespace warnings
Commit: 7880b2c8586eade00a4aa5ac11007317a61e376c
https://github.com/llvm/llvm-project/commit/7880b2c8586eade00a4aa5ac11007317a61e376c
Author: Max191 <44243577+Max191 at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tensor/Utils/Utils.h
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Transforms.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/Tensor/Utils/Utils.cpp
M mlir/test/Dialect/Linalg/vectorization.mlir
Log Message:
-----------
[mlir] Add direct vectorization lowering for `tensor.pack` ops (#78660)
This PR adds a direct vectorization lowering of `tensor.pack` into
`mask(vector.transfer_read)`->`vector.shape_cast`->`vector.transpose`->`vector.transfer_write`.
Commit: 3115ad8980e7d36adca95b5449db8ebf9bd94bf2
https://github.com/llvm/llvm-project/commit/3115ad8980e7d36adca95b5449db8ebf9bd94bf2
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/idot4u.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
M llvm/test/CodeGen/AMDGPU/load-hi16.ll
M llvm/test/CodeGen/AMDGPU/permute.ll
M llvm/test/CodeGen/AMDGPU/permute_i8.ll
Log Message:
-----------
[AMDGPU] Accept arbitrary sized sources in CalculateByteProvider (#70240)
Reland the original patch with additional commit containing fix for two
issues:
1. Attempting to bitcast using MVTs with no corresponding LLVM type.
getDWordFromOffset now works directly with the original vector to get
the corresponding elements given the DWordOffset.
2. Improper bit tracking in CalculateByteProvider for vector types using
certain ops. Previously, bit tracking for certain ops (e.g.
ISD::TRUNCATE) assumed operands were scalar types, which is not correct
since these ops have different semantics depending on vector / scalar.
CalculateByteProvider / CalculateSrcByte now exit on vector types,
handling which is a TODO.
Commit: b89eb9790a8962ca634965d05491a93c58773faf
https://github.com/llvm/llvm-project/commit/b89eb9790a8962ca634965d05491a93c58773faf
Author: Shourya Goel <114918019+Sh0g0-1758 at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/Sema/SemaOpenMP.cpp
A clang/test/OpenMP/bug69085.c
Log Message:
-----------
[Clang][OpenMP] Fix `!isNull() && "Cannot retrieve a NULL type pointer"' fail. (#81015)
Fixes : #69085 , #69200
**PR SUMMARY**: "Added Null check for negative sized array and a test
for the same"
Commit: 9c75a981554d5de4b909e6493f2c3dda03395aa2
https://github.com/llvm/llvm-project/commit/9c75a981554d5de4b909e6493f2c3dda03395aa2
Author: Ilya Leoshkevich <iii at linux.ibm.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/test/CodeGen/SystemZ/asm-01.ll
Log Message:
-----------
[SystemZ] Implement A, O and R inline assembly format flags (#80685)
Implement the following assembly format flags, which are already
supported by GCC:
'A': On z14 or higher: If operand is a mem print the alignment
hint usable with vl/vst prefixed by a comma.
'O': print only the displacement of a memory reference or address.
'R': print only the base register of a memory reference or address.
Implement 'A' conservatively, since the memory operand alignment
information is not available for INLINEASM at the moment.
Commit: 2ecf608829252d7d5b530a03b87817cd948a3386
https://github.com/llvm/llvm-project/commit/2ecf608829252d7d5b530a03b87817cd948a3386
Author: lonely eagle <2020382038 at qq.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/Transforms/ComposeSubView.cpp
M mlir/test/Transforms/compose-subview.mlir
Log Message:
-----------
[mlir]Fix compose subview (#80551)
I found a bug in `test-compose-subview`,You can see the example I gave.
```
#map = affine_map<() -> ()>
module {
func.func private @fun(%arg0: memref<10x10xf32>, %arg1: memref<5x5xf32>) -> memref<5x5xf32> {
%c0 = arith.constant 0 : index
%c5 = arith.constant 5 : index
%c1 = arith.constant 1 : index
%subview = memref.subview %arg0[0, 0] [5, 5] [1, 1] : memref<10x10xf32> to memref<5x5xf32, strided<[10, 1]>>
%alloc = memref.alloc() : memref<5x5xf32>
scf.for %arg2 = %c0 to %c5 step %c1 {
scf.for %arg3 = %c0 to %c5 step %c1 {
%subview_0 = memref.subview %subview[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32, strided<[10, 1]>> to memref<f32, strided<[], offset: ?>>
%subview_1 = memref.subview %arg1[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32> to memref<f32, strided<[], offset: ?>>
%alloc_2 = memref.alloc() : memref<f32>
linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []} ins(%subview_0, %subview_1 : memref<f32, strided<[], offset: ?>>, memref<f32, strided<[], offset: ?>>) outs(%alloc_2 : memref<f32>) {
^bb0(%in: f32, %in_4: f32, %out: f32):
%0 = arith.addf %in, %in_4 : f32
linalg.yield %0 : f32
}
%subview_3 = memref.subview %alloc[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32> to memref<f32, strided<[], offset: ?>>
memref.copy %alloc_2, %subview_3 : memref<f32> to memref<f32, strided<[], offset: ?>>
}
}
return %alloc : memref<5x5xf32>
}
func.func @test(%arg0: memref<10x10xf32>, %arg1: memref<5x5xf32>) -> memref<5x5xf32> {
%0 = call @fun(%arg0, %arg1) : (memref<10x10xf32>, memref<5x5xf32>) -> memref<5x5xf32>
return %0 : memref<5x5xf32>
}
}
```
When I run `mlir-opt test.mlir ---test-compose-subview`.
```
test.mlir:14:9: error: 'linalg.generic' op expected operand rank (2) to match the result rank of indexing_map #0 (0)
linalg.generic {indexing_maps = [#map, #map, #map], iterator_types = []} ins(%subview_0, %subview_1 : memref<f32, strided<[], offset: ?>>, memref<f32, strided<[], offset: ?>>) outs(%alloc_2 : memref<f32>) {
^
test1.mlir:14:9: note: see current operation:
"linalg.generic"(%4, %5, %6) <{indexing_maps = [affine_map<() -> ()>, affine_map<() -> ()>, affine_map<() -> ()>], iterator_types = [], operandSegmentSizes = array<i32: 2, 1>}> ({
^bb0(%arg4: f32, %arg5: f32, %arg6: f32):
%8 = "arith.addf"(%arg4, %arg5) <{fastmath = #arith.fastmath<none>}> : (f32, f32) -> f32
"linalg.yield"(%8) : (f32) -> ()
}) : (memref<1x1xf32, strided<[10, 1], offset: ?>>, memref<f32, strided<[], offset: ?>>, memref<f32>) -> ()
```
This PR fixes that.In the meantime I've extended this PR to handle cases
where stride is greater than 1.
```
func.func private @Unknown0(%arg0: memref<10x10xf32>, %arg1: memref<5x5xf32>) -> memref<5x5xf32> {
%c0 = arith.constant 0 : index
%c5 = arith.constant 5 : index
%c1 = arith.constant 1 : index
%subview = memref.subview %arg0[0, 0] [5, 5] [2, 2] : memref<10x10xf32> to memref<5x5xf32, strided<[20, 2]>>
%alloc = memref.alloc() : memref<5x5xf32>
scf.for %arg2 = %c0 to %c5 step %c1 {
scf.for %arg3 = %c0 to %c5 step %c1 {
%subview_0 = memref.subview %subview[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32, strided<[20, 2]>> to memref<f32, strided<[], offset: ?>>
%subview_1 = memref.subview %arg1[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32> to memref<f32, strided<[], offset: ?>>
%alloc_2 = memref.alloc() : memref<f32>
linalg.generic {indexing_maps = [affine_map<() -> ()>, affine_map<() -> ()>, affine_map<() -> ()>], iterator_types = []} ins(%subview_0, %subview_1 : memref<f32, strided<[], offset: ?>>, memref<f32, strided<[], offset: ?>>) outs(%alloc_2 : memref<f32>) {
^bb0(%in: f32, %in_4: f32, %out: f32):
%0 = arith.addf %in, %in_4 : f32
linalg.yield %0 : f32
}
%subview_3 = memref.subview %alloc[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32> to memref<f32, strided<[], offset: ?>>
memref.copy %alloc_2, %subview_3 : memref<f32> to memref<f32, strided<[], offset: ?>>
}
}
return %alloc : memref<5x5xf32>
}
$ mlir-opt test.mlir -test-compose-subview
#map = affine_map<()[s0] -> (s0 * 2)>
#map1 = affine_map<() -> ()>
module {
func.func private @Unknown0(%arg0: memref<10x10xf32>, %arg1: memref<5x5xf32>) -> memref<5x5xf32> {
%c0 = arith.constant 0 : index
%c5 = arith.constant 5 : index
%c1 = arith.constant 1 : index
%alloc = memref.alloc() : memref<5x5xf32>
scf.for %arg2 = %c0 to %c5 step %c1 {
scf.for %arg3 = %c0 to %c5 step %c1 {
%0 = affine.apply #map()[%arg2]
%1 = affine.apply #map()[%arg3]
%subview = memref.subview %arg0[%0, %1] [1, 1] [2, 2] : memref<10x10xf32> to memref<f32, strided<[], offset: ?>>
%subview_0 = memref.subview %arg1[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32> to memref<f32, strided<[], offset: ?>>
%alloc_1 = memref.alloc() : memref<f32>
linalg.generic {indexing_maps = [#map1, #map1, #map1], iterator_types = []} ins(%subview, %subview_0 : memref<f32, strided<[], offset: ?>>, memref<f32, strided<[], offset: ?>>) outs(%alloc_1 : memref<f32>) {
^bb0(%in: f32, %in_3: f32, %out: f32):
%2 = arith.addf %in, %in_3 : f32
linalg.yield %2 : f32
}
%subview_2 = memref.subview %alloc[%arg2, %arg3] [1, 1] [1, 1] : memref<5x5xf32> to memref<f32, strided<[], offset: ?>>
memref.copy %alloc_1, %subview_2 : memref<f32> to memref<f32, strided<[], offset: ?>>
}
}
return %alloc : memref<5x5xf32>
}
}
```
Commit: 8b0f47bfa4b6aa1bafa10261444c93aba5a2d31d
https://github.com/llvm/llvm-project/commit/8b0f47bfa4b6aa1bafa10261444c93aba5a2d31d
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M lld/test/wasm/build-id.test
M lld/test/wasm/merge-string-debug.s
M lld/test/wasm/startstop.ll
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/test/tools/llvm-objdump/wasm/executable-without-symbols-debugnames.test
M llvm/test/tools/llvm-objdump/wasm/executable-without-symbols.test
M llvm/test/tools/llvm-objdump/wasm/no-codesec.test
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[Object][Wasm] Use file offset for section addresses in linked wasm files (#80529)
Wasm has no unified virtual memory space as other object formats and
architectures do, so previously WasmObjectFile reported 0 for all
section addresses, and until 428cf71ff used section offsets for function
symbols. Now we use file offsets for function symbols, and this change
switches section addresses to do the same (in linked files). The main
result of this is that objdump now reports VMAs in section listings, and
also uses file offets rather than section offsets when disassembling
linked binaries (matching the behavior of other disassemblers and stack
traces produced by browwsers). To make this work, this PR also updates
objdump's generation of synthetics fallback symbols to match lib/Object
and also correctly plumbs symbol types for regular and dummy symbols
through to the backend to avoid needing special knowledge of address 0.
This also paves the way for generating symbols from name sections rather
than symbol tables or imports (see #76107) by allowing the
disassembler's synthetic fallback symbols match the name-section
generated symbols (in a followup PR).
Commit: caf537ea493a7583bbc369c6a692842819daee74
https://github.com/llvm/llvm-project/commit/caf537ea493a7583bbc369c6a692842819daee74
Author: Stephen Tozer <Stephen.Tozer at Sony.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
M llvm/test/Transforms/SpeculativeExecution/PR46267.ll
Log Message:
-----------
Reapply "[RemoveDIs][DebugInfo] Hoist DPValues in SpeculativeExecution (#80886)"
Reapply the original commit, 0aacd44, which had a missing brace resulting in
an error in compilation.
This reverts commit c76b0eb898d1e5edc416b658a6902163d64db1ce.
Commit: 9f6c00565a82fc375d415804d54da1113f719b17
https://github.com/llvm/llvm-project/commit/9f6c00565a82fc375d415804d54da1113f719b17
Author: Kolya Panchenko <87679760+nikolaypanchenko at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/CMakeLists.txt
A mlir/include/mlir/Dialect/LLVMIR/VCIXDialect.h
A mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td
M mlir/include/mlir/Target/LLVMIR/Dialect/All.h
A mlir/include/mlir/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.h
M mlir/lib/Dialect/LLVMIR/CMakeLists.txt
A mlir/lib/Dialect/LLVMIR/IR/VCIXDialect.cpp
M mlir/lib/Target/LLVMIR/CMakeLists.txt
M mlir/lib/Target/LLVMIR/Dialect/CMakeLists.txt
A mlir/lib/Target/LLVMIR/Dialect/VCIX/CMakeLists.txt
A mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp
A mlir/test/Conversion/MathToVCIX/math-to-vcix.mlir
A mlir/test/Target/LLVMIR/vcix-rv32.mlir
A mlir/test/Target/LLVMIR/vcix-rv64.mlir
M mlir/test/lib/Conversion/CMakeLists.txt
A mlir/test/lib/Conversion/MathToVCIX/CMakeLists.txt
A mlir/test/lib/Conversion/MathToVCIX/TestMathToVCIXConversion.cpp
M mlir/tools/mlir-opt/CMakeLists.txt
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[MLIR][VCIX] Support VCIX intrinsics in LLVMIR dialect (#75875)
The changeset extends LLVMIR intrinsics with VCIX intrinsics.
The VCIX intrinsics allow MLIR users to interact with RISC-V
co-processors that are compatible with `XSfvcp` extension
Source:
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software
Commit: 7a9b0e4acb3b5ee15f8eb138aad937cfa4763fb8
https://github.com/llvm/llvm-project/commit/7a9b0e4acb3b5ee15f8eb138aad937cfa4763fb8
Author: Xing Xue <xingxue at outlook.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M openmp/runtime/src/kmp.h
M openmp/runtime/test/tasking/bug_nested_proxy_task.c
M openmp/runtime/test/tasking/bug_proxy_task_dep_waiting.c
M openmp/runtime/test/tasking/hidden_helper_task/common.h
Log Message:
-----------
[OpenMP][test]Flip bit-fields in 'struct flags' for big-endian in test cases (#79895)
This patch flips bit-fields in `struct flags` for big-endian in test
cases to be consistent with the definition of the structure in libomp
`kmp.h`.
Commit: 369b82218419a0218400e7483255523b8dfd6cf0
https://github.com/llvm/llvm-project/commit/369b82218419a0218400e7483255523b8dfd6cf0
Author: Vijay Kandiah <vkandiah at nvidia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRDialect.h
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Dialect/FIRDialect.cpp
M flang/tools/bbc/bbc.cpp
M flang/tools/fir-opt/fir-opt.cpp
M flang/tools/tco/tco.cpp
Log Message:
-----------
[flang] Introducing a method to dynamically and conditionally register dialect interfaces. (#80881)
This change introduces the `addFIRExtensions` method to dynamically and
conditionally register dialect interfaces. As a use case of
`addFIRExtensions`, this change moves the static registration of
`FIRInlinerInterface` out of the constructor of `FIROpsDialect` to be
dynamically registered while loading the necessary MLIR dialects
required by Flang. This registration of `FIRInlinerInterface` is also
guarded by a boolean `addFIRInlinerInterface` which defaults to true.
---------
Co-authored-by: Vijay Kandiah <vkandiah at nvidia.com>
Commit: c95693c74601521463e12ff358fed6fb9ee736b9
https://github.com/llvm/llvm-project/commit/c95693c74601521463e12ff358fed6fb9ee736b9
Author: Pranav Kant <prka at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[NFC][AMDGPU] Fix unused-variable warning (#81040)
This is only used in assert statement.
Commit: bb3ea6c810ccdffd176589e608bfa79dd25268ff
https://github.com/llvm/llvm-project/commit/bb3ea6c810ccdffd176589e608bfa79dd25268ff
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/IR/ModuleSummaryIndex.h
Log Message:
-----------
[MemProf] Switch to DenseMap for performance (NFC) (#81035)
Some profiling showed that the accesses to this map during bitcode
reading was incurring over 10% of the time in a large thin link. There
is no need for it to be std::map, and I measured around 8.5% time
reduction in the same thin link from switching to DenseMap.
Commit: b1ac052ab07ea091c90c2b7c89445b2bfcfa42ab
https://github.com/llvm/llvm-project/commit/b1ac052ab07ea091c90c2b7c89445b2bfcfa42ab
Author: Arnold Schwaighofer <aschwaighofer at apple.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-infinite-loop-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-start-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-dyn-align.ll
A llvm/test/Transforms/Coroutines/coro-async-mutal-recursive.ll
M llvm/test/Transforms/Coroutines/coro-async-unreachable.ll
M llvm/test/Transforms/Coroutines/coro-async.ll
M llvm/test/Transforms/Coroutines/swift-async-dbg.ll
Log Message:
-----------
[Coro] [async] Disable inlining in async coroutine splitting (#80904)
The call to the inlining utility does not update the call graph. Leading
to assertion failures when calling the call graph utility to update the
call graph.
Instead rely on an inline pass to run after coro splitting and use
alwaysinline annotations.
github.com/apple/swift/issues/68708
Commit: d05bd34a1814f7b60265207b1b805572f79aca6d
https://github.com/llvm/llvm-project/commit/d05bd34a1814f7b60265207b1b805572f79aca6d
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/lib/CodeGen/MachinePassManager.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[NFC][NewPM/Codegen] Remove unused parameter from verifyMachineFunction
The MachineFunctionAnalysisManager forward declaration is messing with upcoming changes.
Commit: 50ffc53e4708f3484939ef82e7b0309600a8e19f
https://github.com/llvm/llvm-project/commit/50ffc53e4708f3484939ef82e7b0309600a8e19f
Author: jimingham <jingham at apple.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
Log Message:
-----------
Don't search for separate debug files for mach-o object files (#81041)
mach-o object files never have separate debug info, and in a big app
there can be quite a large number of object files, so even a few stats
per object file can slow launches considerably.
This patch avoids this search for Mach-o symbol files of object type.
I don't have a way to test this, the only effect is that you didn't do a
bunch of stats that weren't going to do any good anyway.
Commit: 514686acfda66401869f9599954d731619c12c99
https://github.com/llvm/llvm-project/commit/514686acfda66401869f9599954d731619c12c99
Author: Visoiu Mistrih Francis <890283+francisvm at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
M llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp
A llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir
M llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir
Log Message:
-----------
[RISCV] Add correct Uses, Defs, isReturn to Zcmp (#81039)
* they all do stack adjustments, so they all use and def x2.
* popret and popretz also return
* popretz also defines x10
This adds that to the TD file and updates the PushPopOptimizer to
preserve the extra implicit operands added during frame lowering when
converting to popret(z).
Commit: d6c2cbbc6513bd412b34f3bf70e21b5a363b2fd9
https://github.com/llvm/llvm-project/commit/d6c2cbbc6513bd412b34f3bf70e21b5a363b2fd9
Author: Yi Kong <yikong at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/utils/UpdateTestChecks/common.py
Log Message:
-----------
Fix test failure if CLANG_VENDOR contains spaces (#81017)
Commit: ff8c865838b46d0202963b816fbed50aaf96a7f4
https://github.com/llvm/llvm-project/commit/ff8c865838b46d0202963b816fbed50aaf96a7f4
Author: Daniel Hoekwater <hoekwater at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/Driver/fbasic-block-sections.c
Log Message:
-----------
[Driver] Allow -fbasic-block-sections for AArch64 ELF (#80916)
Basic block sections "all" doesn't work on AArch64 since branch
relaxation may create new basic blocks. However, the other basic
block section modes should work out of the box since machine function
splitting already uses the basic block sections pass.
Commit: 43badc0a9644d032fe0176410fabda6ac1fddf19
https://github.com/llvm/llvm-project/commit/43badc0a9644d032fe0176410fabda6ac1fddf19
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineModuleInfo.h
Log Message:
-----------
[NewPM/CodeGen] Move MachineModuleInfo::invalidate() to MachineModuleAnalysis::Result
Missed in #80937 since it's not currently being used.
Commit: 78b9dd6b206a151fe09b56fcb157f38321b84340
https://github.com/llvm/llvm-project/commit/78b9dd6b206a151fe09b56fcb157f38321b84340
Author: quanwanandy <150498259+quanwanandy at users.noreply.github.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel
Log Message:
-----------
Fix Bazel build (#81064)
Commit: 4520b478d2512b0f39764e0464dcb4cb961845b5
https://github.com/llvm/llvm-project/commit/4520b478d2512b0f39764e0464dcb4cb961845b5
Author: YunQiang Su <syq at debian.org>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M libunwind/CMakeLists.txt
Log Message:
-----------
MIPS/libunwind: Use -mfp64 if compiler is FPXX (#68521)
Libunwind supports FP64 and FP32 modes, but not FPXX. The reason is
that, FP64 and FP32 have different way to save/restore FPRs. If
libunwind is built as FPXX, we have no idea which one should we use.
It's not due to the code bug, but rather the nature of FPXX.
FPXX is an ABI which uses only a common subset of FR=1(FP64) and FR=0
(FP32).
So that FPXX binaries can link with both FP64 and FP32 ones, aka.
FPXX + FP32 -> FP32
FPXX + FP64 -> FP64
While for libunwind, we should save/restore all of FPRs. If we use FPXX,
we can only save/restore a common subset of FPRs, instead of superset.
If libunwind is built as FP64, it will interoperatable with FPXX/FP64
APPs, and if it is built as FP32, it will interoperatable with
FP32/FPXX. Currently most of O32 APPs are FPXX or FP64, while few are
FP32.
So if the compiler is FPXX, which is the default value of most
toolchain, let's switch it to FP64.
Co-authored-by: YunQiang Su <yunqiang.su at cipunited.com>
Commit: 0d7f232baf6103529844c8977324bd45b21ad923
https://github.com/llvm/llvm-project/commit/0d7f232baf6103529844c8977324bd45b21ad923
Author: dhruvachak <Dhruva.Chakrabarti at amd.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M openmp/libomptarget/include/OpenMP/OMPT/Interface.h
M openmp/libomptarget/src/LegacyAPI.cpp
M openmp/libomptarget/src/OpenMP/API.cpp
M openmp/libomptarget/src/OpenMP/OMPT/Callback.cpp
M openmp/libomptarget/src/device.cpp
M openmp/libomptarget/src/interface.cpp
M openmp/libomptarget/test/ompt/callbacks.h
A openmp/libomptarget/test/ompt/target_memcpy.c
M openmp/libomptarget/test/ompt/veccopy.c
M openmp/libomptarget/test/ompt/veccopy_data.c
M openmp/libomptarget/test/ompt/veccopy_emi.c
Log Message:
-----------
[libomptarget] [OMPT] Fixed return address computation for OMPT events. (#80498)
Currently, __builtin_return_address is used to generate the return
address when the callback invoker is created. However, this may result
in the return address pointing to an internal runtime function. This is
not what a tool would typically want. A tool would want to know the
corresponding user code from where the runtime entry point is invoked.
This change adds a thread local variable that is assigned the return
address at the OpenMP runtime entry points. An RAII is used to manage
the modifications to the thread local variable. Whenever the return
address is required for OMPT events, it is read from the thread local
variable.
Commit: ece66dbc60971cf43a96f63e05c5a507feae3854
https://github.com/llvm/llvm-project/commit/ece66dbc60971cf43a96f63e05c5a507feae3854
Author: Luke Lau <luke at igalia.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/RISCV/rvv/stepvector.ll
Log Message:
-----------
[SelectionDAG] Add computeKnownBits support for ISD::STEP_VECTOR (#80452)
This handles two cases where we can work out some known-zero bits for
ISD::STEP_VECTOR.
The first case handles when we know the low bits are zero because the
step
amount is a power of two. This is taken from
https://reviews.llvm.org/D128159,
and even though the original patch didn't end up landing this case due
to it
not having any test difference, I've included it here for completeness's
sake.
The second case handles the case when we have an upper bound on
vscale_range.
We can use this to work out the upper bound on the number of elements,
and thus
what the maximum step will be. From the maximum step we then know which
hi bits
are zero.
On its own, computing the known hi bits results in some small
improvements for
RVV with -mrvv-vector-bits=zvl across the llvm-test-suite. However I'm
hoping
to be able to use this later to reduce the LMUL in index calculations
for
vrgather/indexed accesses.
---------
Co-authored-by: Philip Reames <preames at rivosinc.com>
Commit: 2df42fe0efd92a89ae191a598e2727c7b63de80b
https://github.com/llvm/llvm-project/commit/2df42fe0efd92a89ae191a598e2727c7b63de80b
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M lldb/docs/lldb-gdb-remote.txt
M lldb/tools/debugserver/source/RNBRemote.cpp
Log Message:
-----------
[lldb] [NFC] Remove min pkt size for compression setting (#81075)
debugserver will not compress small packets; the overhead of the
compression header makes this useful for larger packets. I default to
384 bytes in debugserver, and added an option for lldb to request a
different cutoff. This option has never been used in lldb in the past
nine years, so I don't think there's any point to keeping it around.
Commit: 7da1dda01eff708decbbb0b4cd52b2b95d89ea2a
https://github.com/llvm/llvm-project/commit/7da1dda01eff708decbbb0b4cd52b2b95d89ea2a
Author: David Green <david.green at arm.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
M llvm/test/CodeGen/AArch64/arm64-fminv.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
Log Message:
-----------
[AArch64][GlobalISel] Update GISel check line and regenerate tests. NFC
Commit: 567d304e5344dfb408f2453390886fc229c09481
https://github.com/llvm/llvm-project/commit/567d304e5344dfb408f2453390886fc229c09481
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
Log Message:
-----------
[TableGen][NFC] Replace hardcoded opcode numbering. (#81065)
This patch uses the recently introduced CodeGenTarget::getInstrIntValue
to replace hardcoded opcode enum value numbering in a few places.
Commit: 5c4a630ab70f98138d6f95d19712bb114d92323d
https://github.com/llvm/llvm-project/commit/5c4a630ab70f98138d6f95d19712bb114d92323d
Author: Alexandre Ganea <aganea at havenstudios.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M lld/ELF/Arch/LoongArch.cpp
Log Message:
-----------
[LLD][ELF] Silence warning when building with latest MSVC
This fixes:
```
[193/3517] Building CXX object
tools\lld\ELF\CMakeFiles\lldELF.dir\Arch\LoongArch.cpp.obj
C:\git\llvm-project\lld\ELF\Arch\LoongArch.cpp(683): warning C4334:
'<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit
shift intended?
```
Commit: d01864eb2f21d56cf432da7d80c505f510533c46
https://github.com/llvm/llvm-project/commit/d01864eb2f21d56cf432da7d80c505f510533c46
Author: Jason Eckhardt <jeckhardt at nvidia.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/utils/TableGen/CodeGenInstruction.h
M llvm/utils/TableGen/CodeGenTarget.cpp
M llvm/utils/TableGen/CodeGenTarget.h
Log Message:
-----------
[TableGen] Remove map CodeGenTarget::InstrToIntMap. (#81079)
This patch removes CodeGenTarget::InstrToIntMap, using instead a new
member CodeGenInstruction::EnumVal to store each enum value. This value
is computed and set by CodeGenTarget::computeInstrsByEnum and queried by
CodeGenTarget::getInstrIntValue.
Commit: 05091aa3ac53a13d08c78882c0c2035e58a1b4c4
https://github.com/llvm/llvm-project/commit/05091aa3ac53a13d08c78882c0c2035e58a1b4c4
Author: Mingming Liu <mingmingl at google.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/ProfileData/InstrProfTest.cpp
Log Message:
-----------
[NFC][InstrProf]Generalize getParsedIRPGOFuncName to getParsedIRPGOName (#81054)
- Function getParsedIRPGOFuncName splits name by delimiter. The `[filename;]mangled-name` format could be generalized for non-function global values (e.g., vtables for type profiling). So rename the
function.
- Use kGlobalIdentifierDelimiter rather than semicolon directly for defragmentation.
Commit: d033799050b7bda70d80a933d5d99b7088a72a95
https://github.com/llvm/llvm-project/commit/d033799050b7bda70d80a933d5d99b7088a72a95
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Add Leave to AlwaysBreakTemplateDeclarations (#80569)
Closes #78067.
Commit: 351f94d981f363909ae6e76ed57cd0a75c3f5688
https://github.com/llvm/llvm-project/commit/351f94d981f363909ae6e76ed57cd0a75c3f5688
Author: Rageking8 <106309953+Rageking8 at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
Log Message:
-----------
[clang][NFC] resolve redundant predicates (#79701)
Fixes #79686
Commit: 8f6e13e6da84510c8321717860fd506e12118514
https://github.com/llvm/llvm-project/commit/8f6e13e6da84510c8321717860fd506e12118514
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-07 (Wed, 07 Feb 2024)
Changed paths:
M clang/test/Format/dump-config-objc-stdin.m
M clang/test/Format/verbose.cpp
M clang/tools/clang-format/ClangFormat.cpp
Log Message:
-----------
[clang-format] Fix a regression in dumping the config (#80628)
Commit d813af73f70f addressed a regression introduced by commit
3791b3fca6ea
but caused `clang-format -dump-config` to "hang".
This patch reverts changes to ClangFormat.cpp by both commits and
reworks the cleanup.
Fixes #80621.
Commit: c8ca98a2a9796797f2eab00cc6516610c133633a
https://github.com/llvm/llvm-project/commit/c8ca98a2a9796797f2eab00cc6516610c133633a
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
Log Message:
-----------
[InstCombine] Handle IsInf/IsZero idioms (#80607)
This patch does the following folds:
```
icmp eq/ne (bitcast X to int), (bitcast +/-inf to int) -> llvm.is.fpclass(X, (~)fcPosInf/fcNegInf)
icmp eq/ne (bitcast X to int), (bitcast +0/-0 to int) -> llvm.is.fpclass(X, (~)fcPosZero/fcNegZero)
```
Alive2: https://alive2.llvm.org/ce/z/JJmEE9
Commit: e17dded8d712fb13c30fd88f7810edaa0ee3e60d
https://github.com/llvm/llvm-project/commit/e17dded8d712fb13c30fd88f7810edaa0ee3e60d
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/test/Transforms/InstCombine/create-class-from-logic-fcmp.ll
M llvm/test/Transforms/InstSimplify/logic-of-fcmps.ll
Log Message:
-----------
[InstSimplify] Generalize `simplifyAndOrOfFCmps` (#81027)
This patch generalizes `simplifyAndOrOfFCmps` to simplify patterns like:
```
define i1 @src(float %x, float %y) {
%or.cond.i = fcmp ord float %x, 0.000000e+00
%cmp.i.i34 = fcmp olt float %x, %y
%cmp.i2.sink.i = and i1 %or.cond.i, %cmp.i.i34
ret i1 %cmp.i2.sink.i
}
define i1 @tgt(float %x, float %y) {
%cmp.i.i34 = fcmp olt float %x, %y
ret i1 %cmp.i.i34
}
```
Alive2: https://alive2.llvm.org/ce/z/9rydcx
This patch and #80986 will fix the regression introduced by #80941.
See also the IR diff
https://github.com/dtcxzyw/llvm-opt-benchmark/pull/199#discussion_r1480974120.
Commit: 9ff3b82948c90c54f2f6ec20798c529cb93fab3b
https://github.com/llvm/llvm-project/commit/9ff3b82948c90c54f2f6ec20798c529cb93fab3b
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/Support/AMDGPUMetadata.h
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
Log Message:
-----------
[AMDGPU] Revert Metadata Version Upgrade (#80995)
Metadata is still 1.2, not 1.3 after V6.
I thought that amdhsa.version mapped to the COV version but it's
separate, and there are no MD changes in V6, hence it doesn't need to be
updated.
Commit: a446c9bf69b4797da329977366ca62e55a429a90
https://github.com/llvm/llvm-project/commit/a446c9bf69b4797da329977366ca62e55a429a90
Author: martinboehme <mboehme at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
Log Message:
-----------
[clang][dataflow] Add support for `CXXRewrittenBinaryOperator`. (#81086)
This occurs in rewritten candidates for binary operators (a C++20
feature).
The patch modifies UncheckedOptionalAccessModelTest to run in C++20 mode
(as
well as C++17 mode, as before) and to use rewritten candidates. The
modified
test fails without the newly added support for
`CXXRewrittenBinaryOperator`.
Commit: a24b0c351a75a87410203dd3777c0d8ee87f65c1
https://github.com/llvm/llvm-project/commit/a24b0c351a75a87410203dd3777c0d8ee87f65c1
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/test/Headers/__clang_hip_cmath.hip
M clang/test/Headers/__clang_hip_math.hip
Log Message:
-----------
clang/AMDGPU: Regenerate test checks in hip header tests
Commit: decbd29f9e9be50756a083cd677f7fea22cd3c91
https://github.com/llvm/llvm-project/commit/decbd29f9e9be50756a083cd677f7fea22cd3c91
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/simplify-demanded-fpclass.ll
Log Message:
-----------
Reapply "InstCombine: Introduce SimplifyDemandedUseFPClass"" (#74056)
This reverts commit ef388334ee5a3584255b9ef5b3fefdb244fa3fd7.
The referenced issue violates the spec for finite-only math only by
using a return value for a constant infinity. If the interpretation
is results and arguments cannot violate nofpclass, then any
std::numeric_limits<T>::infinity() result is invalid under
-ffinite-math-only. Without this interpretation the utility of
nofpclass is slashed.
Commit: 35d6ae8110e082e9a4704416dfbe83d5a3b16ed1
https://github.com/llvm/llvm-project/commit/35d6ae8110e082e9a4704416dfbe83d5a3b16ed1
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/or.ll
Log Message:
-----------
[InstCombine] Handle multi-use in simplifyAndOrWithOpReplaced() (#81006)
Slightly generalize simplifyAndOrWithOpReplaced() by allowing it to
perform simplifications (without creating new instructions) in multi-use
cases. This way we can remove existing patterns without worrying about
multi-use edge cases.
I've opted to change the general way the implementation works to be more
similar to the standard simplifyWithOpReplaced(). We perform the operand
replacement generically, and then try to simplify the result or create a
new instruction if we're allowed to do so.
Commit: 7c0d52ca91d32e693ca245fb82f2402a34212fc3
https://github.com/llvm/llvm-project/commit/7c0d52ca91d32e693ca245fb82f2402a34212fc3
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Analysis/DomConditionCache.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/InstCombine/known-bits.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
Log Message:
-----------
[ValueTracking] Support dominating known bits condition in and/or (#74728)
This extends computeKnownBits() support for dominating conditions to
also handle and/or conditions. We'll look through either and or or
depending on which edge we're considering.
This change is mainly for the sake of completeness, so we don't start
missing optimizations if SimplifyCFG decides to merge some branches.
Commit: 7ec6e7351458924946e9afaadf9788cb233095b9
https://github.com/llvm/llvm-project/commit/7ec6e7351458924946e9afaadf9788cb233095b9
Author: Sven van Haastregt <sven.vanhaastregt at arm.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/SelectionDAG.h
Log Message:
-----------
[DAG] Fix typos in comments; NFC
Commit: dd9511d3e46094ec15282bce6eba163fed2226a4
https://github.com/llvm/llvm-project/commit/dd9511d3e46094ec15282bce6eba163fed2226a4
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/test/AST/Interp/builtin-functions.cpp
Log Message:
-----------
[clang][Interp][NFC] Convert test case to verify=expected,both style
Commit: ef05b4b520ee342db6a3d6c5607f8e8729246316
https://github.com/llvm/llvm-project/commit/ef05b4b520ee342db6a3d6c5607f8e8729246316
Author: David Green <david.green at arm.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] More vscale tests. NFC
This time with i8 geps and scale intrinsics, along with mutiple vscale
intrinsics that can be treated as identical.
Commit: 9ac82f0d3ecf6c13669b0c7940920460c037a292
https://github.com/llvm/llvm-project/commit/9ac82f0d3ecf6c13669b0c7940920460c037a292
Author: Martin Storsjö <martin at martin.st>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M openmp/cmake/OpenMPTesting.cmake
Log Message:
-----------
[OpenMP] [cmake] In standalone mode, make Python3_EXECUTABLE available (#80828)
When running the tests, we try to invoke them as
"${Python3_EXECUTABLE} ${OPENMP_LLVM_LIT_EXECUTABLE}", but when running
"find_package(Python3)" within the function
"find_standalone_test_dependencies", the variable "Python3_EXECUTABLE"
only gets set within the function scope.
Tests have worked regardless of this in many cases, where executing the
python script directly succeeds. But for consistency, and for working in
cases when the python script can't be executed as such, make the
Python3_EXECUTABLE variable available as intended.
Commit: 49ee2ffc65b7660bfe84cd842e083d6c0ee3e991
https://github.com/llvm/llvm-project/commit/49ee2ffc65b7660bfe84cd842e083d6c0ee3e991
Author: Evgeniy <evgeniy.tyurin at intel.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
R llvm/test/CodeGen/X86/GlobalISel/br.ll
R llvm/test/CodeGen/X86/GlobalISel/brcond.ll
R llvm/test/CodeGen/X86/fast-isel-cmp-branch2.ll
R llvm/test/CodeGen/X86/fast-isel-cmp-branch3.ll
A llvm/test/CodeGen/X86/isel-br.ll
A llvm/test/CodeGen/X86/isel-brcond-fcmp.ll
A llvm/test/CodeGen/X86/isel-brcond-icmp.ll
Log Message:
-----------
[X86][GlobalISel] Reorganize br/brcond tests (NFC) (#80204)
Removing duplicating tests under GlobalISel, consolidating to perform
checks with all three selectors.
Commit: b85fe40cb88a6b4f640c2b757bd0d254ff1d032c
https://github.com/llvm/llvm-project/commit/b85fe40cb88a6b4f640c2b757bd0d254ff1d032c
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/test/Analysis/Inputs/std-c-library-functions-POSIX.h
M clang/test/Analysis/std-c-library-functions-POSIX.c
M clang/test/Analysis/std-c-library-functions.c
M clang/test/Analysis/stream-error.c
M clang/test/Analysis/stream-noopen.c
M clang/test/Analysis/stream.c
Log Message:
-----------
[clang][analyzer] Add missing stream related functions to StdLibraryFunctionsChecker. (#76979)
Some stream functions were recently added to `StreamChecker` that were
not modeled by `StdCLibraryFunctionsChecker`. To ensure consistency
these functions are added to the other checker too.
Some of the related tests are re-organized.
Commit: 8f2378d7fcf19ea00fbd3366c2125569ef084f93
https://github.com/llvm/llvm-project/commit/8f2378d7fcf19ea00fbd3366c2125569ef084f93
Author: Simon Camphausen <simon.camphausen at iml.fraunhofer.de>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
Log Message:
-----------
[mlir][EmitC] Add builders for call_opaque op (#80879)
This allows to omit the default valued attributes and therefore write
more compact code.
Commit: 1a42b3804f0ed1c4958c4f17216543a1623e3452
https://github.com/llvm/llvm-project/commit/1a42b3804f0ed1c4958c4f17216543a1623e3452
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Erase ranges of instructions individually (#81007)
The BasicBlock::erase method simply removes a range of instructions from
the instlist by unlinking them. However, now that we're attaching
debug-info directly to instructions, some cleanup is required, so use
eraseFromParent on each instruction instead.
This is less efficient, but rare, and seemingly only WASM EH Prepare
uses this method of BasicBlock. Detected via a memory leak check in
asan.
(asan is always the final boss for whatever I do).
Commit: faa2f9658a0cd276f3415fad2676f8d90df51268
https://github.com/llvm/llvm-project/commit/faa2f9658a0cd276f3415fad2676f8d90df51268
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
A llvm/test/DebugInfo/X86/dont-drop-dbg-assigns-in-isels.ll
Log Message:
-----------
[DebugInfo] Handle dbg.assigns in FastISel (#80734)
There are some rare circumstances where dbg.assign intrinsics can reach
FastISel. They are a more specialised kind of dbg.value intrinsic with
more information about the originating alloca. They only occur during
optimisation, but might reach FastISel through always_inlining an
optimised function into an optnone function.
This is a slight problem as it's not safe (for debug-info accuracy) to
ignore any intrinsics, and for RemoveDIs (the intrinsic-replacement
project) it causes a crash through an unhandled switch case. To get
around this, we can just treat the dbg.assign as a dbg.value (it's an
actual subclass) and use the variable location information from the
dbg.value fields. This loses a small amount of debug-info about stack
locations, but is more accurate than just ignoring the intrinsic.
(This has popped up deep in an LTO build of a large codebase while
testing RemoveDIs, I figured it'd be good to fix it for the
intrinsic-form at the same time, just to demonstrate the correct
behaviour).
Commit: 878234b3202c9fe343cd59c71b50c4c4c5dc1b8c
https://github.com/llvm/llvm-project/commit/878234b3202c9fe343cd59c71b50c4c4c5dc1b8c
Author: David Green <david.green at arm.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] Scalable offset with scalable typesize. (#80818)
This patch adds a simple alias analysis check for accesses that are scalable
with a offset between them that is also trivially scalable (there are no other
constant/variable offsets). We essentially divide each side by vscale and are
left needing to check that the offset >= typesize.
Commit: 455c3966cd7305b40d6941b544a16c22120b4512
https://github.com/llvm/llvm-project/commit/455c3966cd7305b40d6941b544a16c22120b4512
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Log Message:
-----------
[RISCV][test] Add test coverage for RISCVInstrInfo::isCopyInstrImpl
Commit: d7fb94b6daa643a764e9a756bc544f26c248dafd
https://github.com/llvm/llvm-project/commit/d7fb94b6daa643a764e9a756bc544f26c248dafd
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/include/lldb/DataFormatters/TypeSynthetic.h
M lldb/include/lldb/DataFormatters/VectorIterator.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/ValueObjectSyntheticFilter.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Plugins/Language/CPlusPlus/BlockPointer.cpp
M lldb/source/Plugins/Language/CPlusPlus/Coroutines.cpp
M lldb/source/Plugins/Language/CPlusPlus/Coroutines.h
M lldb/source/Plugins/Language/CPlusPlus/GenericBitset.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.h
M lldb/source/Plugins/Language/CPlusPlus/LibCxxAtomic.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxQueue.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxRangesRefView.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxTuple.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcppTuple.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp
M lldb/source/Plugins/Language/ObjC/Cocoa.cpp
M lldb/source/Plugins/Language/ObjC/NSArray.cpp
M lldb/source/Plugins/Language/ObjC/NSDictionary.cpp
M lldb/source/Plugins/Language/ObjC/NSError.cpp
M lldb/source/Plugins/Language/ObjC/NSException.cpp
M lldb/source/Plugins/Language/ObjC/NSIndexPath.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
Log Message:
-----------
[lldb][TypeSynthetic][NFC] Make SyntheticChildrenFrontend::Update() return an enum (#80167)
This patch changes the return value of
`SyntheticChildrenFrontend::Update` to a scoped enum that aims to
describe what the return value means.
Commit: b35c5197629494cb675948fe33d2fdcd75b5aafa
https://github.com/llvm/llvm-project/commit/b35c5197629494cb675948fe33d2fdcd75b5aafa
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
Log Message:
-----------
[DAG] tryToFoldExtendOfConstant - share the same SDLoc argument instead of recreating it over and over again.
Commit: a643ab852a63a14dba86e031247734c5e3d5adb9
https://github.com/llvm/llvm-project/commit/a643ab852a63a14dba86e031247734c5e3d5adb9
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/DebugInfo/Generic/assignment-tracking/codegenprepare/sunk-addr.ll
M llvm/test/Transforms/GlobalOpt/localize-constexpr-debuginfo.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Final omnibus test fixing for RemoveDIs (#81125)
With this, I get a clean test suite running under RemoveDIs, the
non-intrinsic representation of debug-info, including under asan. We've
previously established that we generate identical binaries for some
large projects, so this i just edge-case cleanup. The changes:
* CodeGenPrepare fixups need to apply to dbg.assigns as well as
dbg.values (a dbg.assign is a dbg.value).
* Pin a test for constant-deletion to intrinsic debug-info: this very
rare scenario uses a different kill-location sigil in dbg.value mode to
RemoveDIs mode, which generates spurious test differences.
* Suppress a memory leak in a unit test: the code for dealing with
trailing debug-info in a block is necessarily fiddly, leading to this
leak when testing it. Developer-facing interfaces for moving
instructions around always deal with this behind the scenes.
* SROA, when replacing some vector-loads, needs to insert the
replacement loads ahead of any debug-info records so that their values
remain dominated by a definition. Set the head-bit indicating our
insertion should come before debug-info.
Commit: 7d4733a267cafa2109dc43b151dbae5716f372e4
https://github.com/llvm/llvm-project/commit/7d4733a267cafa2109dc43b151dbae5716f372e4
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerBUILD_VECTOR - share the same SDLoc argument instead of recreating it over and over again.
Commit: 8e707f8444692762b35fde3e94bbcb02686272a5
https://github.com/llvm/llvm-project/commit/8e707f8444692762b35fde3e94bbcb02686272a5
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/test/Lower/target-features-amdgcn.f90
M flang/test/Lower/target-features-x86_64.f90
Log Message:
-----------
[Flang][Lower] NFC: Update target-features/target-cpu tests (#80984)
Previously, some of these lowering tests inadvertently relied on a
default triple not introducing any target features. This caused failures
when compiling on a ppc64le-linux-unknown-gnu system.
This patch updates these lowering tests to always explicitly set the
target triple and check that the -target-cpu and -target-features
compiler options are processed as expected.
Commit: 42902d22d1272c1bc10132b06be2d5251b17f225
https://github.com/llvm/llvm-project/commit/42902d22d1272c1bc10132b06be2d5251b17f225
Author: Zain Jaffal <zain at jjaffal.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
A llvm/test/Transforms/InstCombine/fdiv-sqrt.ll
Log Message:
-----------
[InstCombine] Add tests for x / sqrt(y / z) with fast-math
Commit: e50189b0fdf382e3e0d5fc5e58fe81a78d0de7c8
https://github.com/llvm/llvm-project/commit/e50189b0fdf382e3e0d5fc5e58fe81a78d0de7c8
Author: Zain Jaffal <zain at jjaffal.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/test/Transforms/InstCombine/fdiv-sqrt.ll
Log Message:
-----------
[InstCombine] Add additional tests for fdiv-sqrt
Add more tests where some of the instructions have missing flags.
Commit: 4b72c5e8277f8688f7ce0bc953f9f3ea54420358
https://github.com/llvm/llvm-project/commit/4b72c5e8277f8688f7ce0bc953f9f3ea54420358
Author: whisperity <whisperity at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/test/Sema/conversion-64-32.c
A clang/test/Sema/conversion-implicit-int-includes-64-to-32.c
Log Message:
-----------
[clang][Sema] Subclass `-Wshorten-64-to-32` under `-Wimplicit-int-conversion` (#80814)
Although "implicit int conversions" is supposed to be a superset
containing the more specific "64-to-32" case, previously they were a
disjoint set, only enabled in common in the much larger `-Wconversion`.
Commit: 448fe73428a810eb67617e07c23510033a21de5a
https://github.com/llvm/llvm-project/commit/448fe73428a810eb67617e07c23510033a21de5a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Add X86::getVectorRegisterWidth helper. NFC.
Replaces internal helper used by addConstantComments to allow reuse in a future patch.
Commit: 6ea76c1328e04799981c78b3661a175a2ba47cec
https://github.com/llvm/llvm-project/commit/6ea76c1328e04799981c78b3661a175a2ba47cec
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/CMakeLists.txt
Log Message:
-----------
[NFCI][RemoveDIs] Build LLVM with RemoveDIs iterators
This commit flips a bit to make LLVM build with "debuginfo iterators",
causing BasicBlock::iterator to contain a bit that's used for debug-info
purposes. More about this can be read on Discourse [0], but the runtime
impact of this should be negligable (iterators usually end up being
inlined), and there should be no change to LLVMs behaviour as a result of
this commit.
What this does mean though, is that roughly 400 debug-info tests where
we've added "--try-experimental-debuginfo-iterators" to RUNlines are going
to start operating in RemoveDIs mode. These are already tested on the
new-debug-iterators buildbot [1], and I've even tested with asan, so I'm
not _expecting_ any turbulence.
[0] https://discourse.llvm.org/t/rfc-instruction-api-changes-needed-to-eliminate-debug-intrinsics-from-ir/68939
[1] https://lab.llvm.org/buildbot/#/builders/275
Commit: ec1fcb381d884ca53e2e0dd4075f946c8f002de2
https://github.com/llvm/llvm-project/commit/ec1fcb381d884ca53e2e0dd4075f946c8f002de2
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/tools/bbc/bbc.cpp
Log Message:
-----------
[Flang][bbc] Prevent bbc -emit-fir command invoking OpenMP passes twice (#80927)
Currently when the bbc tool is invoked with the emit-fir command the pass pipeline will be invoked twice for verification causing the previously added OpenMP pass pipeline to be invoked multiple times.
This change seeks to prevent that from occurring by using a seperate pass manager and run command immediately when it is necessary for the OpenMP passes to be executed.
Commit: 72f04fa0734f8559ad515f507a4a3ce3f461f196
https://github.com/llvm/llvm-project/commit/72f04fa0734f8559ad515f507a4a3ce3f461f196
Author: Martin Storsjö <martin at martin.st>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M openmp/cmake/HandleOpenMPOptions.cmake
Log Message:
-----------
[OpenMP] [cmake] Don't use -fno-semantic-interposition on Windows (#81113)
This was added in 4b7beab4187ab0766c3d7b272511d5751431a8da. When the
flag was added implicitly elsewhere, it was added via
llvm/cmake/modules/HandleLLVMOptions.cmake, where it wasn't added on
Windows/Cygwin targets.
This avoids one warning per object file in OpenMP.
Commit: 8697bbe2d4aed109520e83c6beab52196ec5b702
https://github.com/llvm/llvm-project/commit/8697bbe2d4aed109520e83c6beab52196ec5b702
Author: Mariya Podchishchaeva <mariya.podchishchaeva at intel.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/Sema/SemaChecking.cpp
M clang/test/SemaOpenCL/operators.cl
Log Message:
-----------
[clang] Use CPlusPlus language option instead of Bool (#80975)
As it was pointed out in
https://github.com/llvm/llvm-project/pull/80724, we should not be
checking `getLangOpts().Bool` when determining something related to
logical operators, since it only indicates that bool keyword is present,
not which semantic logical operators have. As a side effect a missing
`-Wpointer-bool-conversion` in OpenCL C was restored since like C23,
OpenCL C has bool keyword but logical operators still return int.
Commit: fe8a62c46365f5ef0c15df2265bbf0026d0a4047
https://github.com/llvm/llvm-project/commit/fe8a62c46365f5ef0c15df2265bbf0026d0a4047
Author: Uday Bondhugula <uday at polymagelabs.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Affine/IR/AffineOps.td
M mlir/include/mlir/Dialect/Utils/StructuredOpsUtils.h
M mlir/include/mlir/IR/AffineMap.h
M mlir/lib/Conversion/TosaToLinalg/TosaToLinalg.cpp
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/Split.cpp
M mlir/lib/Dialect/Linalg/Utils/Utils.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferSplitRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/AffineMap.cpp
M mlir/lib/IR/BuiltinTypes.cpp
A mlir/unittests/IR/AffineMapTest.cpp
M mlir/unittests/IR/CMakeLists.txt
Log Message:
-----------
[MLIR] Fix crash in AffineMap::replace for zero result maps (#80930)
Fix obvious bug in AffineMap::replace for the case of zero result maps.
Extend/complete inferExprsFromList to work with empty expression lists.
Commit: d63c8bee58b5d4dad9f1c550a342e782e0038f28
https://github.com/llvm/llvm-project/commit/d63c8bee58b5d4dad9f1c550a342e782e0038f28
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/AST/ExprConstant.cpp
Log Message:
-----------
[clang][ExprConst] Remove unnecessary cast
FD is a FunctionDecl, so no need to cast a FunctionDecl to a
CXXMethodDecl just to assign it to a FunctionDecl.
Commit: 3ad63593dac390e320808f3de0e1906c5fa45c8a
https://github.com/llvm/llvm-project/commit/3ad63593dac390e320808f3de0e1906c5fa45c8a
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/IR/PatternMatch.h
M llvm/unittests/IR/PatternMatch.cpp
Log Message:
-----------
[PatternMatch] Add m_PtrAdd() matcher (NFC)
This matches a getelementptr i8 instruction or constant expression,
with a given pointer operand and index.
Commit: d9e92765c5f9b0fa7adafa769dd13d37b6bca038
https://github.com/llvm/llvm-project/commit/d9e92765c5f9b0fa7adafa769dd13d37b6bca038
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/IR/ConstantRange.cpp
A llvm/test/Transforms/SCCP/pr79696.ll
M llvm/unittests/IR/ConstantRangeTest.cpp
Log Message:
-----------
[ConstantRange] Improve ConstantRange::binaryXor (#80146)
`ConstantRange::binaryXor` gives poor results as it currently depends on
`KnownBits::operator^`.
Since `sub A, B` is canonicalized into `xor A, B` if `B` is the subset
of `A`, this patch reverts the transform in `ConstantRange::binaryXor`,
which will give better results.
Alive2: https://alive2.llvm.org/ce/z/bmTMV9
Fixes #79696.
Commit: 06774d6bbf32aff45b67d8c3753524ec36bf8869
https://github.com/llvm/llvm-project/commit/06774d6bbf32aff45b67d8c3753524ec36bf8869
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/records.cpp
Log Message:
-----------
[clang][Interp] Handle CXXInheritedCtorInitExprs
We need to forward all arguments of the current function and
call the ctor function.
Commit: c4b0dfcc99da7506bff6b57d563e5cbce9caf4cd
https://github.com/llvm/llvm-project/commit/c4b0dfcc99da7506bff6b57d563e5cbce9caf4cd
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
Log Message:
-----------
[Clang] Fix a non-effective assertion (#81083)
`PTy` here is literally `FTy->getParamType(i)`, which makes this
assertion not
work as expected.
Commit: fb6ef4233968ffefb616d1c779a5483ef1f140d3
https://github.com/llvm/llvm-project/commit/fb6ef4233968ffefb616d1c779a5483ef1f140d3
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/test/AST/Interp/records.cpp
Log Message:
-----------
[clang][Interp][NFC] Convert records test to verify=expected,both style
Commit: 10cd0e7a8bdcd80c0b017f8d0b6b71dd61973b54
https://github.com/llvm/llvm-project/commit/10cd0e7a8bdcd80c0b017f8d0b6b71dd61973b54
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/docs/FortranLLVMTestSuite.md
Log Message:
-----------
[flang][docs] Update flang documentation regarding the test suite (#80755)
Remove redundant reference to flang not being able to generate code. Add
a reference to the gfortran tests that are part of the LLVM Test Suite.
Commit: cd183428a9af6d7dda2018a88aeb495f268716b5
https://github.com/llvm/llvm-project/commit/cd183428a9af6d7dda2018a88aeb495f268716b5
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeEmitter.cpp
M clang/test/AST/Interp/lambda.cpp
Log Message:
-----------
[clang][Interp] Fix handling of generic lambdas
When compiling their static invoker, we need to get the
right specialization.
Commit: 3e33b6f5de6905c98395a77b41d474b87ef9e677
https://github.com/llvm/llvm-project/commit/3e33b6f5de6905c98395a77b41d474b87ef9e677
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M libcxx/include/ostream
M libcxx/include/scoped_allocator
M libcxx/include/shared_mutex
M libcxx/include/string
M libcxx/include/valarray
M libcxx/include/vector
Log Message:
-----------
[libc++][NFC] Reformat a few files that had gotten mis-formatted
Those appear to be oversights when committing patches
in the last few months.
Commit: 5452cbc4a6bfb905fedeacaa6f27895e249da1e5
https://github.com/llvm/llvm-project/commit/5452cbc4a6bfb905fedeacaa6f27895e249da1e5
Author: ostannard <oliver.stannard at arm.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
M llvm/test/CodeGen/AArch64/kcfi-bti.ll
Log Message:
-----------
[AArch64] Indirect tail-calls cannot use x16 with pac-ret+pc (#81020)
When using -mbranch-protection=pac-ret+pc, x16 is used in the function
epilogue to hold the address of the signing instruction. This is used by
a HINT instruction which can only use x16, so we can't change this. This
means that we can't use it to hold the function pointer for an indirect
tail-call.
There is existing code to force indirect tail-calls to use x16 or x17
when BTI is enabled, so there are now 4 combinations:
bti pac-ret+pc Valid function pointer registers
off off Any non callee-saved register
on off x16 or x17
off on Any non callee-saved register except x16
on on x17
Commit: 0802596df3d1ffd15f6b828a0f5c1e5b687a730f
https://github.com/llvm/llvm-project/commit/0802596df3d1ffd15f6b828a0f5c1e5b687a730f
Author: Daniel Chen <cdchen at ca.ibm.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
Log Message:
-----------
[Flang] Update the fix of PR 80738 to cover generic interface inside modules (#81087)
The following test cases crashes. The problem is that the fix for PR
https://github.com/llvm/llvm-project/pull/80738 is not quite complete.
It should `GetUltimate()` of the `interface_` before check if it is
generic.
```
MODULE M
CONTAINS
FUNCTION Int(Arg)
INTEGER :: Int, Arg
Int = Arg
END FUNCTION
FUNCTION Int8(Arg)
INTEGER(8) :: Int8, Arg
Int8 = 8_8
END FUNCTION
END MODULE
MODULE M1
USE M
INTERFACE Int8
MODULE PROCEDURE Int
MODULE PROCEDURE Int8
END INTERFACE
END MODULE
PROGRAM PtrAssignGen
USE M
USE M1
IMPLICIT NONE
INTERFACE Int
MODULE PROCEDURE Int
MODULE PROCEDURE Int8
END INTERFACE
PROCEDURE(Int8), POINTER :: PtrInt8
PtrInt8 => Int8
IF ( PtrInt8(100_8) .NE. 8_8 ) ERROR STOP 12
END
```
Commit: dc5da4851de5d29dd040d85a8387e2e5b4b12b7b
https://github.com/llvm/llvm-project/commit/dc5da4851de5d29dd040d85a8387e2e5b4b12b7b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
A llvm/test/Transforms/InstCombine/dependent-ivs.ll
Log Message:
-----------
[InstCombine] Add tests for #77108 (NFC)
Commit: fffcc5ca83ad2700a3586c1b849a36c6081e2023
https://github.com/llvm/llvm-project/commit/fffcc5ca83ad2700a3586c1b849a36c6081e2023
Author: Francesco Petrogalli <francesco.petrogalli at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/lib/CodeGen/ValueTypes.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
Log Message:
-----------
[CodeGen] Add ValueType v3i8 (NFCI). (#80826)
Commit: b14731fe93d0db9a59984783051880795ae0992d
https://github.com/llvm/llvm-project/commit/b14731fe93d0db9a59984783051880795ae0992d
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/Parse/ParseOpenACC.cpp
Log Message:
-----------
[OpenACC][NFC] Fix parse result from 'set'
Apparently 'set' was being parsed as 'shutdown'. There isn't really any
way of detecting this without getting into a Sema implementation,
however fixing this now as I noticed it.
Commit: 067d2779fcfc62dd429177f350b8cefe49b65b51
https://github.com/llvm/llvm-project/commit/067d2779fcfc62dd429177f350b8cefe49b65b51
Author: ian Bearman <ianb at microsoft.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/lib/Dialect/Arith/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/test/lib/Dialect/Bufferization/TestTensorCopyInsertion.cpp
Log Message:
-----------
[MLIR] Setting MemorySpace During Bufferization (#78484)
Collection of changes with the goal of being able to convert `encoding`
to `memorySpace` during bufferization
- new API for encoder to allow implementation to select destination
memory space
- update existing bufferization implementations to support the new
interface
Commit: 92eaf036bf22ecc276146cd073208e6a867af8d4
https://github.com/llvm/llvm-project/commit/92eaf036bf22ecc276146cd073208e6a867af8d4
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/include/llvm/ADT/ilist_iterator.h
M llvm/tools/llc/llc.cpp
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/llvm-lto/llvm-lto.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
M llvm/tools/llvm-reduce/llvm-reduce.cpp
M llvm/tools/opt/optdriver.cpp
M llvm/unittests/ADT/IListIteratorBitsTest.cpp
M llvm/unittests/IR/BasicBlockDbgInfoTest.cpp
Log Message:
-----------
[NFC][RemoveDIs] Remove conditional compilation for RemoveDIs (#81149)
A colleague observes that switching the default value of
LLVM_EXPERIMENTAL_DEBUGINFO_ITERATORS to "On" hasn't flipped the value
in their CMakeCache.txt. This probably means that everyone with an
existing build tree is going to not have support built in, meaning
everyone in LLVM would need to clean+rebuild their worktree when we flip
the switch on... which doesn't sound good.
So instead, just delete the flag and everything it does, making everyone
build and run ~400 lit tests in RemoveDIs mode. None of the buildbots
have had trouble with this, so it Should Be Fine (TM).
(Sending for review as this is changing various comments, and touches
several different areas -- I don't want to get too punchy).
Commit: 7d19dc50de2c81ead6af750bcddd139ac99a48b5
https://github.com/llvm/llvm-project/commit/7d19dc50de2c81ead6af750bcddd139ac99a48b5
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
A llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp16_from_vop1.s
A llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop3_dpp8_from_vop1.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp16_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop3_dpp8_from_vop1.txt
Log Message:
-----------
[AMDGPU][True16] Support VOP3 source DPP operands. (#80892)
Commit: b846613837d83989d99d33f4b90db7bad019aa8c
https://github.com/llvm/llvm-project/commit/b846613837d83989d99d33f4b90db7bad019aa8c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants - add destination register width to rebuildSplatCst/rebuildZeroUpperCst/rebuildExtCst callbacks
As found on #81136 - we aren't correctly handling for cases where the constant pool entry is wider than the destination register width, causing incorrect scaling of the truncated constant for load-extension cases.
This first patch just pulls out the destination register width argument, its still currently driven by the constant pool entry but that will be addressed in a followup.
Commit: eb85c8edf576d27254fa37bf9ed72ec0867756f7
https://github.com/llvm/llvm-project/commit/eb85c8edf576d27254fa37bf9ed72ec0867756f7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
A llvm/test/CodeGen/X86/pr81136.ll
Log Message:
-----------
[X86] Add test case for #81136
Commit: f407be32fe8084fe02c4f16842548d21afdb447f
https://github.com/llvm/llvm-project/commit/f407be32fe8084fe02c4f16842548d21afdb447f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants - rename FixupEntry::BitWidth to FixupEntry::MemBitWidth NFC.
Make it clearer that this refers to the width of the constant element stored in memory - which won't match the register element width after a sext/zextload
Commit: 5aeabf2df92b92c71b5dbdb9ae82a37431aa2ee4
https://github.com/llvm/llvm-project/commit/5aeabf2df92b92c71b5dbdb9ae82a37431aa2ee4
Author: stephenpeckham <118857872+stephenpeckham at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/ObjectYAML/XCOFFYAML.h
M llvm/lib/ObjectYAML/XCOFFEmitter.cpp
M llvm/lib/ObjectYAML/XCOFFYAML.cpp
M llvm/test/tools/obj2yaml/XCOFF/aix.yaml
M llvm/test/tools/obj2yaml/XCOFF/aux-symbols.yaml
A llvm/test/tools/yaml2obj/XCOFF/aux-aligntype.yaml
M llvm/test/tools/yaml2obj/XCOFF/aux-symbols.yaml
M llvm/tools/obj2yaml/xcoff2yaml.cpp
Log Message:
-----------
[XCOFF][obj2yaml] Support SymbolAlignmentAndType as 2 separate fields in YAML. (#76828)
XCOFF encodes a symbol type and alignment in a single 8-bit field. It is
easier to read and write YAML files if the fields can be specified
separately. This PR causes obj2yaml to write the fields separately and
allows yaml2obj to read either the single combined field or the separate
fields.
Commit: 58e8147d1690485ed0a6fcb59c7b6ea4b8cd2936
https://github.com/llvm/llvm-project/commit/58e8147d1690485ed0a6fcb59c7b6ea4b8cd2936
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
Log Message:
-----------
[flang][openacc] Use original input for base address with optional (#80931)
In #80317 the data op generation was updated to use correctly the #0
result from the hlfir.delcare op. In case of optional that are not
descriptor, it is preferable to use the original input for the varPtr
value of the OpenACC data op.
This patch also make sure that the descriptor value of optional is only
accessed when present.
Commit: 66d462d0a1ba1e510fff479baff8f21ecb924b1f
https://github.com/llvm/llvm-project/commit/66d462d0a1ba1e510fff479baff8f21ecb924b1f
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/include/module.modulemap
Log Message:
-----------
Add missing textual header to module map
Commit: 750981f1a2c6069cded709b75cc87d7abd05277a
https://github.com/llvm/llvm-project/commit/750981f1a2c6069cded709b75cc87d7abd05277a
Author: Adrian Prantl <aprantl at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/test/API/macosx/universal/Makefile
Log Message:
-----------
Fix a truly strange triple in testcase
Commit: bdde5f9bea75e897bcc31a95b9c3376988c211cc
https://github.com/llvm/llvm-project/commit/bdde5f9bea75e897bcc31a95b9c3376988c211cc
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Turn on non-instrinsic debug-info by default
This patch causes all variable-location debug-info to be converted into
non-intrinsic records as they passes through the optimisation /
instrumentation passes. There's a brief introduction here [0] and a more
detailed thread on what this means on discourse at [1].
If this commit is breaking your downstream tests, please see comment 12 in
[1], which documents the kind of variation in tests we'd expect to see from
this change and what to do about it.
[0] https://llvm.org/docs/RemoveDIsDebugInfo.html
[1] https://discourse.llvm.org/t/rfc-instruction-api-changes-needed-to-eliminate-debug-intrinsics-from-ir/68939
Commit: f219cda7bd43696792ca4668ca5a9fbf55a9f09f
https://github.com/llvm/llvm-project/commit/f219cda7bd43696792ca4668ca5a9fbf55a9f09f
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py
Log Message:
-----------
[lldb] Fix printf formatting of std::time_t seconds (#81078)
This formatter
https://github.com/llvm/llvm-project/pull/78609
was originally passing the signed seconds (which can refer to times in
the past) with an unsigned printf formatter, and had tests that expected
to see negative values from the printf which always failed on macOS. I'm
not clear how they ever passed on any platform.
Fix the printf to print seconds as a signed value, and re-enable the
tests.
Commit: af97edff70b0d9cb89729dc0d8af1d1ea101686e
https://github.com/llvm/llvm-project/commit/af97edff70b0d9cb89729dc0d8af1d1ea101686e
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/include/lldb/DataFormatters/FormatManager.h
M lldb/source/Core/FormatEntity.cpp
M lldb/source/DataFormatters/FormatManager.cpp
M lldb/source/Interpreter/OptionArgParser.cpp
Log Message:
-----------
[lldb] Refactor GetFormatFromCString to always check for partial matches (NFC) (#81018)
Refactors logic in `ParseInternal` that was previously calling
`GetFormatFromCString` twice, once with `partial_match_ok` set to false,
and the second time set to true.
With this change, lldb formats (ie `%@`, `%S`, etc) are checked first.
If a format is not one of those, then `GetFormatFromCString` is called
once, and now always checks for partial matches.
Commit: bef25ae297d6d246bf0fa8667c8b08f9d5e8dae7
https://github.com/llvm/llvm-project/commit/bef25ae297d6d246bf0fa8667c8b08f9d5e8dae7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/test/CodeGen/X86/pr81136.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - use explicit register bitwidth for the loaded vector instead of using constant pool bitwidth
Fixes #81136 - we might be loading from a constant pool entry wider than the destination register bitwidth, affecting the vextload scale calculation.
ConvertToBroadcastAVX512 doesn't yet set an explicit bitwidth (it will default to the constant pool bitwidth) due to difficulties in looking up the original register width through the fold tables, but as we only use rebuildSplatCst this shouldn't cause any miscompilations, although it might prevent folding to broadcast if only the lower bits match a splatable pattern.
Commit: c8d431e0ed6ab6276bf45d1c36466faad8e4e4d1
https://github.com/llvm/llvm-project/commit/c8d431e0ed6ab6276bf45d1c36466faad8e4e4d1
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
Log Message:
-----------
[riscv] Add test coverage in advance of a upcoming fix
This is a reduced test case for a fix for the issue identified in
https://github.com/llvm/llvm-project/issues/80910.
Commit: 16d1a6486c25769d264a6ddb70a48bbb1c23c077
https://github.com/llvm/llvm-project/commit/16d1a6486c25769d264a6ddb70a48bbb1c23c077
Author: Cooper Partin <coopp at microsoft.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGExprScalar.cpp
A clang/test/CodeGenHLSL/shift-mask.hlsl
Log Message:
-----------
[DirectX] Fix HLSL bitshifts to leverage the OpenCL pipeline for bitshifting (#81030)
Fixes #55106
In HLSL bit shifts are defined to shift by shift size % type size. This
contains the following changes:
HLSL codegen bit shifts will be emitted as x << (y & (sizeof(x) - 1) and
bitshift masking leverages the OpenCL pipeline for this.
Tests were also added to validate this behavior.
Before this change the following was being emitted:
; Function Attrs: noinline nounwind optnone
define noundef i32 @"?shl32@@YAHHH at Z"(i32 noundef %V, i32 noundef %S) #0
{
entry:
%S.addr = alloca i32, align 4
%V.addr = alloca i32, align 4
store i32 %S, ptr %S.addr, align 4
store i32 %V, ptr %V.addr, align 4
%0 = load i32, ptr %V.addr, align 4
%1 = load i32, ptr %S.addr, align 4
%shl = shl i32 %0, %1
ret i32 %shl
}
After this change:
; Function Attrs: noinline nounwind optnone
define noundef i32 @"?shl32@@YAHHH at Z"(i32 noundef %V, i32 noundef %S) #0
{
entry:
%S.addr = alloca i32, align 4
%V.addr = alloca i32, align 4
store i32 %S, ptr %S.addr, align 4
store i32 %V, ptr %V.addr, align 4
%0 = load i32, ptr %V.addr, align 4
%1 = load i32, ptr %S.addr, align 4
%shl.mask = and i32 %1, 31
%shl = shl i32 %0, %shl.mask
ret i32 %shl
}
---------
Co-authored-by: Cooper Partin <coopp at ntdev.microsoft.com>
Commit: 758fd59d018fe01262dd246e3e1e3d4389cb82e4
https://github.com/llvm/llvm-project/commit/758fd59d018fe01262dd246e3e1e3d4389cb82e4
Author: S. Bharadwaj Yadavalli <Bharadwaj.Yadavalli at microsoft.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILMetadata.cpp
M llvm/utils/TableGen/DXILEmitter.cpp
Log Message:
-----------
[DirectX][NFC] Change usage pattern *Dxil* to *DXIL* for uniformity (#80778)
Match DXIL TableGen class names with structure names in DXIL Emitter.
Delete unnecessary Name field.
Commit: abc4f74df7ab3b324b7bf9d171e8a22a92d7dda5
https://github.com/llvm/llvm-project/commit/abc4f74df7ab3b324b7bf9d171e8a22a92d7dda5
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/include/flang/Lower/ConvertVariable.h
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/Dialect/FIRAttr.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
A flang/test/Lower/CUDA/cuda-data-attribute.cuf
M flang/unittests/Optimizer/FortranVariableTest.cpp
Log Message:
-----------
[flang][cuda] Lower attribute for local variable (#81076)
This is a first simple patch to introduce a new FIR attribute to carry
the CUDA variable attribute information to hlfir.declare and fir.declare
operations. It currently lowers this information for local variables.
The texture attribute is omitted since it is rejected by semantic and
will not make its way to MLIR.
This new attribute is added as optional attribute to the hlfir.declare
and fir.declare operations.
Commit: 17f0680f69f44d340fd0205f7763b2830357c0d5
https://github.com/llvm/llvm-project/commit/17f0680f69f44d340fd0205f7763b2830357c0d5
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/test/AST/ast-print-method-decl.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p23.cpp
M clang/test/OpenMP/for_loop_auto.cpp
Log Message:
-----------
[Clang][Sema] Abbreviated function templates do not append invented parameters to empty template parameter lists (#80864)
According to [dcl.fct] p23:
> An abbreviated function template can have a _template-head_. The
invented _template-parameters_ are appended to the
_template-parameter-list_ after the explicitly declared
_template-parameters_.
`template<>` is not a _template-head_ -- a _template-head_ must have at
least one _template-parameter_. This patch corrects our current behavior
of appending the invented template parameters to the innermost template
parameter list, regardless of whether it is empty. Example:
```
template<typename T>
struct A
{
void f(auto);
};
template<>
void A<int>::f(auto); // ok
template<>
template<> // warning: extraneous template parameter list in template specialization
void A<int>::f(auto);
```
Commit: 35fae044c5faf8ddb9be7b47bb7573e839f77472
https://github.com/llvm/llvm-project/commit/35fae044c5faf8ddb9be7b47bb7573e839f77472
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
Log Message:
-----------
[mlir][sparse] using non-static field to avoid data races. (#81165)
Commit: da95d926f6fce4ed9707c77908ad96624268f134
https://github.com/llvm/llvm-project/commit/da95d926f6fce4ed9707c77908ad96624268f134
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang-tools-extra/clang-move/Move.cpp
M clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
M clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.h
M clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.cpp
M clang-tools-extra/clang-tidy/llvm/IncludeOrderCheck.cpp
M clang-tools-extra/clang-tidy/llvmlibc/RestrictSystemLibcHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/HeaderIncludeCycleCheck.cpp
M clang-tools-extra/clang-tidy/modernize/DeprecatedHeadersCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MacroToEnumCheck.cpp
M clang-tools-extra/clang-tidy/portability/RestrictSystemIncludesCheck.cpp
M clang-tools-extra/clang-tidy/portability/RestrictSystemIncludesCheck.h
M clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp
M clang-tools-extra/clang-tidy/utils/IncludeInserter.cpp
M clang-tools-extra/clangd/Headers.cpp
M clang-tools-extra/clangd/ParsedAST.cpp
M clang-tools-extra/clangd/index/IndexAction.cpp
M clang-tools-extra/clangd/unittests/ReplayPeambleTests.cpp
M clang-tools-extra/include-cleaner/lib/Record.cpp
M clang-tools-extra/modularize/CoverageChecker.cpp
M clang-tools-extra/modularize/PreprocessorTracker.cpp
M clang-tools-extra/pp-trace/PPCallbacksTracker.cpp
M clang-tools-extra/pp-trace/PPCallbacksTracker.h
M clang-tools-extra/test/pp-trace/pp-trace-include.cpp
M clang/include/clang/Lex/PPCallbacks.h
M clang/include/clang/Lex/PreprocessingRecord.h
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/lib/CodeGen/MacroPPCallbacks.cpp
M clang/lib/CodeGen/MacroPPCallbacks.h
M clang/lib/Frontend/DependencyFile.cpp
M clang/lib/Frontend/DependencyGraph.cpp
M clang/lib/Frontend/ModuleDependencyCollector.cpp
M clang/lib/Frontend/PrecompiledPreamble.cpp
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/PreprocessingRecord.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/tools/libclang/Indexing.cpp
M clang/unittests/Lex/PPCallbacksTest.cpp
Log Message:
-----------
[clang][lex] Always pass suggested module to `InclusionDirective()` callback (#81061)
This patch provides more information to the
`PPCallbacks::InclusionDirective()` hook. We now always pass the
suggested module, regardless of whether it was actually imported or not.
The extra `bool ModuleImported` parameter then denotes whether the
header `#include` will be automatically translated into import the the
module.
The main change is in `clang/lib/Lex/PPDirectives.cpp`, where we take
care to not modify `SuggestedModule` after it's been populated by
`LookupHeaderIncludeOrImport()`. We now exclusively use the `SM`
(`ModuleToImport`) variable instead, which has been equivalent to
`SuggestedModule` until now. This allows us to use the original
non-modified `SuggestedModule` for the callback itself.
(This patch turns out to be necessary for
https://github.com/apple/llvm-project/pull/8011).
Commit: 13c14ad42c65e154dc079332dd5dd58e8925d26c
https://github.com/llvm/llvm-project/commit/13c14ad42c65e154dc079332dd5dd58e8925d26c
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/IR/BasicBlock.cpp
Log Message:
-----------
Revert "[DebugInfo][RemoveDIs] Turn on non-instrinsic debug-info by default"
This reverts commit bdde5f9bea75e897bcc31a95b9c3376988c211cc.
Two situations that are tripping a few buildbots:
https://lab.llvm.org/buildbot/#/builders/205/builds/25126
Here, polly is currently presenting a DebugLoc attached to a debugging
intrinsic as a "true" source location in a user report, something that's
unreliable.
https://lab.llvm.org/buildbot/#/builders/184/builds/10242
These HWAsan failures are probably (97% confidence) because in
StackInfoBuilder::visit we're not observing DPValues attached to lifetime
intrinsics because they're delt with higher up the function.
But it's late-o'clock here, so revert for now.
Commit: 544f610d5310e1c1e7dd7a081d5a2a2607225740
https://github.com/llvm/llvm-project/commit/544f610d5310e1c1e7dd7a081d5a2a2607225740
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M libcxx/include/vector
Log Message:
-----------
[libc++] Use __is_pointer_in_range inside vector::insert (#80624)
Commit: d272d944de9f0cb274752f77e97d4ceab2401ec5
https://github.com/llvm/llvm-project/commit/d272d944de9f0cb274752f77e97d4ceab2401ec5
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M libcxx/include/limits
Log Message:
-----------
[libc++][NFC] Simplify the implementation of `numeric_limits` (#80425)
The cv specializations for `numeric_limits` inherited privately for some
reason. We can simplify the implementation by inheriting publicly and
removing the members that just replicate the values from the base class.
Commit: 1b5f6916199ce09244cdb52c6911f2028e6ca95a
https://github.com/llvm/llvm-project/commit/1b5f6916199ce09244cdb52c6911f2028e6ca95a
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M libcxx/include/__compare/strong_order.h
M libcxx/include/__compare/weak_order.h
M libcxx/include/compare
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Avoid including <cmath> in <compare> (#80418)
This reduces the time to include `<compare>` from 84ms to 36ms.
Commit: b92e0a31dab5917f31b4672430004add34b5e775
https://github.com/llvm/llvm-project/commit/b92e0a31dab5917f31b4672430004add34b5e775
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
Log Message:
-----------
[flang][cuda] Fix warning in switch
Commit: c0ff10814fb056369cd2bbf0e672498b4cc9c1d4
https://github.com/llvm/llvm-project/commit/c0ff10814fb056369cd2bbf0e672498b4cc9c1d4
Author: Nicolai Hähnle <nicolai.haehnle at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/docs/CMake.rst
M llvm/docs/GettingStarted.rst
Log Message:
-----------
docs/GettingStarted: document linker-related cmake options (#80932)
Both LLVM_LINK_LLVM_DYLIB and LLVM_PARALLEL_LINK_JOBS help with some
common gotchas. It seems worth documenting them here explicitly.
Based on a review comment, also "refactor" the documentation to avoid duplication.
Commit: 687304a018d36c4b0def4618a98fee6975172453
https://github.com/llvm/llvm-project/commit/687304a018d36c4b0def4618a98fee6975172453
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/Lex/PPDirectives.cpp
Log Message:
-----------
[clang][lex] Fix build failure after da95d926
Commit: ab4a793e8bc78f50f9f104c9c732e2dd91bf70a2
https://github.com/llvm/llvm-project/commit/ab4a793e8bc78f50f9f104c9c732e2dd91bf70a2
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/Core/Debugger.h
Log Message:
-----------
[lldb][debugger][NFC] Add broadcast bit for category-based progress events. (#81169)
This commit adds a new broadcast bit to the debugger. When in use, it
will be listened to for progress events that will be delivered and kept
track of by category as opposed to the current behaviour of coming in
one by one.
Commit: a1ed821b49d9a189c3a0a11228c0de517020feca
https://github.com/llvm/llvm-project/commit/a1ed821b49d9a189c3a0a11228c0de517020feca
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
Log Message:
-----------
[TableGen] Simplify prepSkipToLineEnd for preprocessing
The MemoryBuffer is created using `RequiresNullTerminator`, so we can
safely skip the `CurPtr != CurBuf.end()` check. The redundant check
causes a cppcheck report. In addition, elsewhere, including `*CurPtr ==
'#'` below, makes the null terminator assumption as well.
Close #81120
Commit: a56fa161ab2617fa3aab3f91285fc757b6a8e09b
https://github.com/llvm/llvm-project/commit/a56fa161ab2617fa3aab3f91285fc757b6a8e09b
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang-tools-extra/test/clang-tidy/infrastructure/diagnostic.cpp
Log Message:
-----------
[clang-tidy] Fix failing test after #80864 (#81171)
The following test case in
`clang-tools-extra/test/clang-tidy/infrastructure/diagnostic.cpp` is
failing:
```
#ifdef PR64602 // Should not crash
template <class T = void>
struct S
{
auto foo(auto);
};
template <>
auto S<>::foo(auto)
{
return 1;
}
// CHECK8: error: template parameter list matching the non-templated nested type 'S<>' should be empty ('template<>') [clang-diagnostic-error]
#endif
```
#80864 fixes a bug where we would (incorrectly) append invented template
parameters to empty template parameter lists, which causes this test to
fail.
Commit: 3d71e4166de81bc3b86d127d9ac6607bda2b2755
https://github.com/llvm/llvm-project/commit/3d71e4166de81bc3b86d127d9ac6607bda2b2755
Author: Jeremy Kun <2467754+j2kun at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/docs/Diagnostics.md
Log Message:
-----------
[docs]: Add a note about using custom types with diagnostics (#73818)
Commit: 74fc16aaaa227b84e22706d2c5e376287f560b9e
https://github.com/llvm/llvm-project/commit/74fc16aaaa227b84e22706d2c5e376287f560b9e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/ModuleList.cpp
M lldb/source/Host/common/Host.cpp
M lldb/source/Symbol/SymbolLocator.cpp
Log Message:
-----------
[lldb] Expand background symbol download (#80890)
LLDB has a setting (symbols.enable-background-lookup) that calls
dsymForUUID on a background thread for images as they appear in the
current backtrace. Originally, the laziness of only looking up symbols
for images in the backtrace only existed to bring the number of
dsymForUUID calls down to a manageable number.
Users have requesting the same functionality but blocking. This gives
them the same user experience as enabling dsymForUUID globally, but
without the massive upfront cost of having to download all the images,
the majority of which they'll likely not need.
This patch renames the setting to have a more generic name
(symbols.auto-download) and changes its values from a boolean to an
enum. Users can now specify "off", "background" and "foreground". The
default remains "off" although I'll probably change that in the near
future.
Commit: 88e52511ca71165f1ff3d7c42229aeacb2c16db3
https://github.com/llvm/llvm-project/commit/88e52511ca71165f1ff3d7c42229aeacb2c16db3
Author: alex-t <alex-t at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
Log Message:
-----------
[AMDGPU] Compiler should synthesize private buffer resource descriptor from flat_scratch_init (#79586)
This change implements synthesizing the private buffer resource
descriptor in the kernel prolog instead of using the preloaded kernel
argument.
Commit: d0f72f88606b78447fb7b61214651854c787c26f
https://github.com/llvm/llvm-project/commit/d0f72f88606b78447fb7b61214651854c787c26f
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-buildvec-of-binop.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
M llvm/test/CodeGen/RISCV/urem-seteq-illegal-types.ll
Log Message:
-----------
[RISCV] Consider truncate semantics in performBUILD_VECTORCombine (#81168)
Fixes https://github.com/llvm/llvm-project/issues/80910.
Per the documentation in ISDOpcodes.h, for BUILD_VECTOR "The types of
the operands must match the vector element type, except that integer
types are allowed to be larger than the element type, in which case the
operands are implicitly truncated."
This transform was assuming that the scalar operand type matched the
result type. This resulted in essentially performing a truncate before a
binop, instead of after. As demonstrated by the test case changes, this
is often not legal.
Commit: 35c4f025f9d4c398eff0c8e49a47a5c7067939ba
https://github.com/llvm/llvm-project/commit/35c4f025f9d4c398eff0c8e49a47a5c7067939ba
Author: Jacob Lambert <jacob.lambert at amd.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
Log Message:
-----------
[NFC][clang][Driver] Specify options for <arg> with -save-temps=<arg> (#80921)
Commit: 3b57b647a9bb821137f91dfbc2172a9947f620cc
https://github.com/llvm/llvm-project/commit/3b57b647a9bb821137f91dfbc2172a9947f620cc
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/SPIR.h
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/lib/IR/Function.cpp
M llvm/lib/TargetParser/Triple.cpp
Log Message:
-----------
[HLSL][SPIR-V] Add create.handle intrinsic (#81038)
Add a SPIR-V target-specific intrinsic for creating handles, which is
used for lowering HLSL resources types like RWBuffer.
`llvm/lib/TargetParser/Triple.cpp`: SPIR-V intrinsics use "spv" as the
target prefix, not "spirv". As far as I can tell, this is the first one
that is used via the `CGBuiltin` codepath, which relies on
`getArchTypePrefix`, so I've corrected it here.
`clang/lib/Basic/Targets/SPIR.h`: When records are laid out in the
lowering from AST to IR, they were incorrectly offset because these
Pointer attributes were defaulting to 32.
Related to #81036
Commit: e5924d64991abb4da111317ff5e8d9147265354a
https://github.com/llvm/llvm-project/commit/e5924d64991abb4da111317ff5e8d9147265354a
Author: Yinying Li <107574043+yinying-lisa-li at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/include/mlir-c/Dialect/SparseTensor.h
M mlir/include/mlir/Dialect/SparseTensor/IR/Enums.h
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td
M mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h
M mlir/include/mlir/Dialect/SparseTensor/Utils/Merger.h
M mlir/include/mlir/ExecutionEngine/SparseTensor/Storage.h
M mlir/lib/Bindings/Python/DialectSparseTensor.cpp
M mlir/lib/CAPI/Dialect/SparseTensor.cpp
M mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.cpp
M mlir/lib/Dialect/SparseTensor/IR/Detail/LvlTypeParser.h
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseGPUCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorCodegen.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Utils/Merger.cpp
M mlir/lib/ExecutionEngine/SparseTensor/Storage.cpp
M mlir/test/CAPI/sparse_tensor.c
M mlir/test/Dialect/SparseTensor/GPU/gpu_matmul24_lib.mlir
M mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir
M mlir/test/Dialect/SparseTensor/sparse_fill_zero.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block_matmul.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_ds.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sm80-lt/sparse-matmul-2-4-lib.mlir
M mlir/test/Integration/Dialect/SparseTensor/GPU/CUDA/sm80-lt/sparse-matmul-2-4-prune.mlir
M mlir/test/python/dialects/sparse_tensor/dialect.py
Log Message:
-----------
[mlir][sparse] Implement parsing n out of m (#79935)
1. Add parsing methods for block[n, m].
2. Encode n and m with the newly extended 64-bit LevelType enum.
3. Update 2:4 methods names/comments to n:m.
Commit: d1fdb416299c0efa5979ed989f7c1f39973dcb73
https://github.com/llvm/llvm-project/commit/d1fdb416299c0efa5979ed989f7c1f39973dcb73
Author: John Demme <john.demme at microsoft.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/lib/Bindings/Python/IRCore.cpp
M mlir/lib/Bindings/Python/IRModule.h
M mlir/python/mlir/_mlir_libs/_mlir/ir.pyi
M mlir/test/python/ir/module.py
Log Message:
-----------
[MLIR][Python] Add method for getting the live operation objects (#78663)
Currently, a method exists to get the count of the operation objects
which are still alive. This helps for sanity checking, but isn't
terribly useful for debugging. This new method returns the actual
operation objects which are still alive.
This allows Python code like the following:
```
gc.collect()
live_ops = ir.Context.current._get_live_operation_objects()
for op in live_ops:
print(f"Warning: {op} is still live. Referrers:")
for referrer in gc.get_referrers(op)[0]:
print(f" {referrer}")
```
Commit: 705fcd4e0addee6e9e13541dbcbc81cec9748a83
https://github.com/llvm/llvm-project/commit/705fcd4e0addee6e9e13541dbcbc81cec9748a83
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/ModuleList.cpp
M lldb/source/Host/common/Host.cpp
M lldb/source/Symbol/SymbolLocator.cpp
Log Message:
-----------
Revert "[lldb] Expand background symbol lookup" (#81182)
Reverts llvm/llvm-project#80890
Commit: b8545e1ece271df16185d446503474c105d6398a
https://github.com/llvm/llvm-project/commit/b8545e1ece271df16185d446503474c105d6398a
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
Log Message:
-----------
[RISCV] Consider all subvector extracts within a single VREG cheap (#81032)
This adjusts the isSubVectorExtractCheap callback to consider any
extract which fits entirely within the first VLEN bits of the src vector
(and uses a 5 bit immediate for the slide) as cheap. These can be done
via a single m1 vslide1down.vi instruction.
This allows our generic DAG combine logic to kick in and recognize a few
more cases where shuffle source is longer than the dest, but that using
a wider shuffle is still profitable. (Or as shown in the test diff, we
can split the wider source and do two narrower shuffles.)
Commit: 5f4b40c90a51248b097de7b5bc89c6976d4c3298
https://github.com/llvm/llvm-project/commit/5f4b40c90a51248b097de7b5bc89c6976d4c3298
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/ModuleList.cpp
M lldb/source/Symbol/SymbolLocator.cpp
Log Message:
-----------
[lldb] Expand background symbol download (#80890)
LLDB has a setting (symbols.enable-background-lookup) that calls
dsymForUUID on a background thread for images as they appear in the
current backtrace. Originally, the laziness of only looking up symbols
for images in the backtrace only existed to bring the number of
dsymForUUID calls down to a manageable number.
Users have requesting the same functionality but blocking. This gives
them the same user experience as enabling dsymForUUID globally, but
without the massive upfront cost of having to download all the images,
the majority of which they'll likely not need.
This patch renames the setting to have a more generic name
(symbols.auto-download) and changes its values from a boolean to an
enum. Users can now specify "off", "background" and "foreground". The
default remains "off" although I'll probably change that in the near
future.
Commit: 3f9d8d892e2de2ac2542cb8e88ae5317f3282244
https://github.com/llvm/llvm-project/commit/3f9d8d892e2de2ac2542cb8e88ae5317f3282244
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/test/tools/llvm-cov/mcdc-const.test
M llvm/test/tools/llvm-cov/mcdc-general.test
Log Message:
-----------
[Coverage] MCDCRecordProcessor: Find `ExecVectors` directly (#80816)
Deprecate `TestVectors`, since no one uses it.
This affects the output order of ExecVectors.
The current impl emits sorted by binary value of ExecVector. This impl
emits along the traversal of `buildTestVector()`.
Commit: 581857278961b41bc1676499f92167b97a5e4c58
https://github.com/llvm/llvm-project/commit/581857278961b41bc1676499f92167b97a5e4c58
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/Object/wasm-linked-namesec-with-linkingsec.yaml
A llvm/test/Object/wasm-linked-symbol-table.yaml
A llvm/test/tools/llvm-objdump/wasm/linked-symbol-table-namesec.yaml
R llvm/test/tools/llvm-objdump/wasm/linked-symbol-table.yaml
Log Message:
-----------
[Object][Wasm] Generate symbol info from name section names (#81063)
Currently symbol info is generated from a linking section or from export
names. This PR generates symbols in a WasmObjectFile from the name
section as well, which allows tools like objdump and nm to show useful
information for more linked binaries. There are some limitations:
most notably that we don't assume any particular ABI, so we don't get
detailed information about data symbols if the segments are merged
(which is the default).
Covers most of the desired functionality from #76107
Commit: cdde0d9602217eb0bc091b4de16197e6aa5bb132
https://github.com/llvm/llvm-project/commit/cdde0d9602217eb0bc091b4de16197e6aa5bb132
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
Log Message:
-----------
[clang][Interp][NFC] Make a local variable const
Commit: 7c9c4983b1d493c2fdea76f99591f9ab49877306
https://github.com/llvm/llvm-project/commit/7c9c4983b1d493c2fdea76f99591f9ab49877306
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h
Log Message:
-----------
[DWARFLinkerParallel] Fix member initialization order (#81179)
DWARFLinkerImpl::DWARFLinkerImpl initializes
DebugStrStrings/DebugLineStrStrings/CommonSections using GlobalData
but GlobalData is initialized after the three members.
Move GlobalData before.
Fix #81110
Commit: f78c9b88b7a1a54cf67037f9088a3e48779b1e44
https://github.com/llvm/llvm-project/commit/f78c9b88b7a1a54cf67037f9088a3e48779b1e44
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
Log Message:
-----------
[RISCV] Use MCPhysReg for AllPopRegs. NFC
MCPhysReg is 2 bytes, while Register is 4 bytes.
Commit: 4b54b474aa0ffb355faa63cc2d8f95fd321c887f
https://github.com/llvm/llvm-project/commit/4b54b474aa0ffb355faa63cc2d8f95fd321c887f
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
Log Message:
-----------
[NVPTX][NFC] cleanup dead vars, use MAKE_CASE (#81161)
Cleanup some dead variables. In addition, switch to a `MAKE_CASE` macro,
similar to other targets, to reduce boilerplate.
Commit: 0572dabb71147fdc156d90a3ecd036d1652c2006
https://github.com/llvm/llvm-project/commit/0572dabb71147fdc156d90a3ecd036d1652c2006
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/include/llvm/IR/BUILD.gn
Log Message:
-----------
[gn build] Add IntrinsicsSPIRV.h generator
This was missing in the gn build for some reason, causing build errors like http://45.33.8.238/linux/130337/step_4.txt after 3b57b647.
Commit: a6f42adf9ba03d69e8bf2eaf5af2e7f8f6294b37
https://github.com/llvm/llvm-project/commit/a6f42adf9ba03d69e8bf2eaf5af2e7f8f6294b37
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[Bazel] Update for SPIRV
Commit: 7fe97f042036407a124bf1646a3f1124ddac3de5
https://github.com/llvm/llvm-project/commit/7fe97f042036407a124bf1646a3f1124ddac3de5
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT] Always run CheckLargeFunctions in non-relocation mode (#80922)
We run CheckLargeFunctions pass in non-relocation mode to prevent the
emission of functions that later could not be written to the output due
to their large size. The main reason behind the pass is to prevent the
emission of metadata for such functions since this metadata becomes
incorrect if the function is left unmodified.
Currently, the pass is enabled in non-relocation mode only when debug
info output is also enabled. As we emit increasingly more kinds of
metadata, e.g. for the Linux kernel, it becomes more challenging to
track metadata that needs to be fixed. Hence, I'm enabling the pass to
always run in non-relocation mode.
Commit: 7b5a9bb8f0f58b188655252f74b0941512e44389
https://github.com/llvm/llvm-project/commit/7b5a9bb8f0f58b188655252f74b0941512e44389
Author: Davide Italiano <davidino at fb.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[github/CODEOWNERS] Add Alexander as BOLT reviewer.
Commit: 3c42e10afdc518f6d8be5620289ef0da0bf03c5f
https://github.com/llvm/llvm-project/commit/3c42e10afdc518f6d8be5620289ef0da0bf03c5f
Author: Reid Kleckner <rnk at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/AST/Expr.cpp
M clang/test/SemaCXX/compound-literal.cpp
M clang/unittests/AST/ASTExprTest.cpp
Log Message:
-----------
Consider aggregate bases when checking if an InitListExpr is constant (#80519)
This code was correct as written prior to C++17, which allowed bases to
appear in the initializer list.
This was observable by creating non-constant aggregate initialization at
file scope in a compound literal, but since that behavior will change
soon if we implement support for dynamic initialization, I also added a
unit test for `isConstantInitializer`.
This fixes at least one part of issue #80510 .
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 06c89bd59ca2279f76a41e851b7b2df634a6191e
https://github.com/llvm/llvm-project/commit/06c89bd59ca2279f76a41e851b7b2df634a6191e
Author: Luke Lau <luke at igalia.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
Log Message:
-----------
[RISCV] Check type is legal before combining mgather to vlse intrinsic (#81107)
Otherwise we will crash since target intrinsics don't have their types
legalized. Let the mgather get legalized first, then do the combine on
the legal type.
Fixes #81088
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Commit: f7201505a6ec7a0f904d2f09cece5c770058a991
https://github.com/llvm/llvm-project/commit/f7201505a6ec7a0f904d2f09cece5c770058a991
Author: Jerry Wu <cheyuw at google.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h
M mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SCF/Transforms/WrapInZeroTripCheck.cpp
A mlir/test/Dialect/SCF/wrap-while-loop-in-zero-trip-check.mlir
M mlir/test/lib/Dialect/SCF/CMakeLists.txt
A mlir/test/lib/Dialect/SCF/TestSCFWrapInZeroTripCheck.cpp
M mlir/tools/mlir-opt/mlir-opt.cpp
Log Message:
-----------
[mlir] Add transformation to wrap scf::while in zero-trip-check (#81050)
Add `scf::wrapWhileLoopInZeroTripCheck` to wrap scf while loop in
zero-trip-check.
Commit: 8c106a15156857d23ba9e61c55b49b1e2b6c1583
https://github.com/llvm/llvm-project/commit/8c106a15156857d23ba9e61c55b49b1e2b6c1583
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/test/Fir/fir-ops.fir
Log Message:
-----------
[flang] Fix attribute printing for fir.global op (#81197)
The custom printer for `fir.global` was eluding all the attributes
present on the op when printing the attribute dictionary. So any
attribute that is not part of the pretty printing was therefore
discarded.
This patch fix the printer and also make use of the getters for the
attribute names when they are hardcoded.
Commit: 9affa177b526459beddafad30474d2e3186376e4
https://github.com/llvm/llvm-project/commit/9affa177b526459beddafad30474d2e3186376e4
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/test/CodeGen/NVPTX/alias.ll
Log Message:
-----------
[NVPTX] Add support for calling aliases (#81170)
The current implementation of aliases tries to remove all the aliases in
the module to prevent the generic version of `AsmPrinter` from emitting
them incorrectly. Unfortunately, if the aliases are used this will fail.
Instead let's override the function to print aliases directly.
In addition, the declarations of the alias functions must occur before
the uses. To fix this we emit alias declarations as part of
`emitDeclarations` and only emit the `.alias` directives at the end
(where we can assume the aliasee has also already been declared).
Commit: 9211e67da36782db44a46ccb9ac06734ccf2570f
https://github.com/llvm/llvm-project/commit/9211e67da36782db44a46ccb9ac06734ccf2570f
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Target/NVPTX/NVVMReflect.cpp
A llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
Log Message:
-----------
[NVVMReflect] Force dead branch elimination in NVVMReflect (#81189)
Summary:
The `__nvvm_reflect` function is used to guard invalid code that varies
between architectures. One problem with this feature is that if it is
used without optimizations, it will leave invalid code in the module
that will then make it to the backend. The `__nvvm_reflect` pass is
already mandatory, so it should do some trivial branch removal to ensure
that constants are handled correctly. This dead branch elimination only
works in the trivial case of a compare on a branch and does not touch
any conditionals that were not realted to the `__nvvm_reflect` call in
order to preserve `O0` semantics as much as possible. This should allow
the following to work on NVPTX targets
```c
int foo() {
if (__nvvm_reflect("__CUDA_ARCH") >= 700)
asm("valid;\n");
}
```
Commit: 42230e213e11a0cf9cdbdcd49225eb0d325ef007
https://github.com/llvm/llvm-project/commit/42230e213e11a0cf9cdbdcd49225eb0d325ef007
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/test/Driver/linker-wrapper.c
M llvm/lib/Object/OffloadBinary.cpp
Log Message:
-----------
[LinkerWrapper] Allow 'all' as a generic bundled architecture (#81193)
Summary:
Currently, the linker wrapper sorts input files into different link
jobs according to their architectures. Here we assume each architecture
is a unique and incompatible link job unless they are specifically
marked compatible. This patch simply adds an `all` target to represent
an architecture that should be linked against every single other
architecture.
This will be useful for modelling generic IR such as the ROCm device
libraries or the NVPTX libdevice.
Commit: c429f48b56714f9366eee8490061bd008635cbc0
https://github.com/llvm/llvm-project/commit/c429f48b56714f9366eee8490061bd008635cbc0
Author: Sam Clegg <sbc at chromium.org>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Object/WasmObjectFile.cpp
A llvm/test/Object/wasm-bad-relocation.yaml
Log Message:
-----------
[Object][WebAssembly] Improve error on invalid relocation (#81203)
See https://github.com/emscripten-core/emscripten/issues/21140
Commit: 0800a36053943beabe1c3f98fe4ecccbc192a2a7
https://github.com/llvm/llvm-project/commit/0800a36053943beabe1c3f98fe4ecccbc192a2a7
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Target/NVPTX/NVVMReflect.cpp
R llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
Log Message:
-----------
Revert "[NVVMReflect] Force dead branch elimination in NVVMReflect (#81189)"
This reverts commit 9211e67da36782db44a46ccb9ac06734ccf2570f.
Summary:
This seemed to crash one one of the CUDA math tests. Revert until it can
be fixed.
Commit: 2572f45c7d6c081ba9b4fa344e928182f8df7773
https://github.com/llvm/llvm-project/commit/2572f45c7d6c081ba9b4fa344e928182f8df7773
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/lib/Optimizer/Dialect/CMakeLists.txt
Log Message:
-----------
[flang] Fix missing generated header
Fix buildbot failing because of missing HLFIRTypes.h.inc
Commit: 93471466be65cf78330782d461a821ffb82e070a
https://github.com/llvm/llvm-project/commit/93471466be65cf78330782d461a821ffb82e070a
Author: David Blaikie <dblaikie at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/docs/CodeReview.rst
M llvm/docs/GitHub.rst
Log Message:
-----------
Document use of `skip-precommit-approval` label for non-review pull requests (#81053)
Derived from this discussion:
https://discourse.llvm.org/t/prs-without-approvals-muddy-the-waters/76656
Commit: 1d4fc381d3da4317cc2cfa59b2d59d53decddf71
https://github.com/llvm/llvm-project/commit/1d4fc381d3da4317cc2cfa59b2d59d53decddf71
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
A llvm/test/tools/llvm-dwarfdump/X86/verify_empty_debug_line_sequence.yaml
Log Message:
-----------
[DWARFVerifier] Fix verification of empty line tables (#81162)
A line table whose sole entry is an end sequence should not have the
entry's file index verified, as that value corresponds to the initial
value of the state machine, not to a real file index. In DWARF 5, this
is particularly problematic as it uses 0-based indexing, and the state
machine specifies a starting index of 1; in other words, you'd need to
have _two_ files before such index became legal "by default".
A previous attempt to fix this problem was done [1], but it was too
specific in its condition, and did not capture all possible cases where
this issue can happen.
[1]: https://github.com/llvm/llvm-project/pull/77004
Commit: 1389260805ec2ffb74a4fb311e7327c64d9b8f54
https://github.com/llvm/llvm-project/commit/1389260805ec2ffb74a4fb311e7327c64d9b8f54
Author: Lang Hames <lhames at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
Log Message:
-----------
[JITLink][MachO][arm64] Fix error-check order.
The error check should be performed after the iterator increment, not before
it. Thanks to @dcb314 for catching this!
Fixes github.com/apple/swift/issues/81119
Commit: fbf43b0121006e371fbf50ad8642e4c62405e5cc
https://github.com/llvm/llvm-project/commit/fbf43b0121006e371fbf50ad8642e4c62405e5cc
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M libc/include/math.h.def
M libc/spec/spec.td
M libc/spec/stdc.td
M libc/utils/HdrGen/PublicAPICommand.cpp
Log Message:
-----------
[libc] Only declare float128 math functions in the generated math.h if float128 type is supported. (#81010)
Commit: 4759890f859277cd798648a9a333573cd088d98a
https://github.com/llvm/llvm-project/commit/4759890f859277cd798648a9a333573cd088d98a
Author: Alexey Z <alexey.zhikhar at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/test/Dialect/Tensor/canonicalize.mlir
Log Message:
-----------
[mlir][tensor] Fix bug in insert_slice canonical. with tensor encoding (#81045)
Previously, `InsertSliceOpSourceCastInserter` was incorrectly applied to
a case when tensor types have an encoding attribute attached to them.
The type `newSrcType` was missing that attribute from the old `srcType`,
which made the expression `srcType == newSrcType` false, since
`tensor<2x2xf32, "foo">` is not equal to `tensor<2x2xf32>`. That lead to
an endless back and forth between `InsertSliceOpSourceCastInserter` that
would introduce a cast and `InsertSliceOpCastFolder` that would remove
it right after.
Commit: 6e1f438528b6e1ece2f6ef331905c352ccc2fcfd
https://github.com/llvm/llvm-project/commit/6e1f438528b6e1ece2f6ef331905c352ccc2fcfd
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lld/test/ELF/segments.s
Log Message:
-----------
[ELF] Improve --ro-rosegment/--omagic/--nmagic tests
Notably, test that --ro-rosegment with a linker script may unnecessarily
make a read-only PT_LOAD executable.
Commit: f60826917aff102450a470dee85208fd578685c4
https://github.com/llvm/llvm-project/commit/f60826917aff102450a470dee85208fd578685c4
Author: Abdurrahman Akkas <abdurrahmanakkas at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M mlir/lib/IR/AsmPrinter.cpp
Log Message:
-----------
[MLIR] Fix a small formatting issue in AsmPrinter.cpp (#81214)
Introduced in 76ce4736721a6e9030210bda6df0ad8a8f478a19
Commit: ffabcbcf8f9fc7ef5fd29e2a711f95aba0ef7808
https://github.com/llvm/llvm-project/commit/ffabcbcf8f9fc7ef5fd29e2a711f95aba0ef7808
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/docs/NVPTXUsage.rst
M llvm/lib/Target/NVPTX/NVVMReflect.cpp
A llvm/test/CodeGen/NVPTX/nvvm-reflect-arch-O0.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-arch.ll
Log Message:
-----------
[NVVMReflect][Reland] Force dead branch elimination in NVVMReflect (#81189)
Summary:
The `__nvvm_reflect` function is used to guard invalid code that varies
between architectures. One problem with this feature is that if it is
used without optimizations, it will leave invalid code in the module
that will then make it to the backend. The `__nvvm_reflect` pass is
already mandatory, so it should do some trivial branch removal to ensure
that constants are handled correctly. This dead branch elimination only
works in the trivial case of a compare on a branch and does not touch
any conditionals that were not realted to the `__nvvm_reflect` call in
order to preserve `O0` semantics as much as possible. This should allow
the following to work on NVPTX targets
```c
int foo() {
if (__nvvm_reflect("__CUDA_ARCH") >= 700)
asm("valid;\n");
}
```
Relanding after fixing a bug.
Commit: c560ce464ae486e86e3d2d9684df3f714317f502
https://github.com/llvm/llvm-project/commit/c560ce464ae486e86e3d2d9684df3f714317f502
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Support/Utils.h
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/test/Lower/CUDA/cuda-data-attribute.cuf
Log Message:
-----------
[flang][cuda] Lower attribute for dummy argument (#81212)
Lower CUDA attribute for simple dummy argument. This is done in a
similar way than `TARGET`, `OPTIONAL` and so on.
This patch also move the `Fortran::common::CUDADataAttr` to
`fir::CUDAAttributeAttr` mapping to
`flang/include/flang/Optimizer/Support/Utils.h` so that it can be reused
where needed.
Commit: 8e297c779635d7f22626c1a9dd1cb9dc86ea6540
https://github.com/llvm/llvm-project/commit/8e297c779635d7f22626c1a9dd1cb9dc86ea6540
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M lld/test/ELF/segments.s
Log Message:
-----------
[ELF] Improve --ro-rosegment tests
Commit: ac0577177f053ba7e7016e1b7e44cf5932d00b03
https://github.com/llvm/llvm-project/commit/ac0577177f053ba7e7016e1b7e44cf5932d00b03
Author: Abinaya Saravanan <quic_asaravan at quicinc.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
Log Message:
-----------
[HEXAGON] Add basic block limit for RDF optimizations (#81071)
Skip RDF optimizations if a function contains a number of basic blocks
that is more than a limit
---------
Co-authored-by: Yashas Andaluri <quic_yandalur at quicinc.com>
Commit: db88f3015867ca569ae78a30f20a944c8e1b8afc
https://github.com/llvm/llvm-project/commit/db88f3015867ca569ae78a30f20a944c8e1b8afc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
Log Message:
-----------
[RISCV] Add test for saving s10 with cm.push. NFC
If cm.push saves s10, it must also save s11 due to an encoding
limitation. We handle this in the code, but had no test for it.
Commit: 763139afc19ddf2e0f0265dc828ce8e5fbe92530
https://github.com/llvm/llvm-project/commit/763139afc19ddf2e0f0265dc828ce8e5fbe92530
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M clang/include/clang/Format/Format.h
M clang/lib/Format/FormatToken.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
Log Message:
-----------
[clang-format] Update FormatToken::isSimpleTypeSpecifier() (#80241)
Now with a8279a8bc541, we can make the update.
Commit: b2cd50dbe78c0f0328fe208ab8c4d6005d9272dd
https://github.com/llvm/llvm-project/commit/b2cd50dbe78c0f0328fe208ab8c4d6005d9272dd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
Log Message:
-----------
[RISCV] Use replace XLenVT with i64 in some isel patterns that are only used for RV64. NFC
Commit: 95b14da678f4670283240ef4cf60f3a39bed97b4
https://github.com/llvm/llvm-project/commit/95b14da678f4670283240ef4cf60f3a39bed97b4
Author: Quentin Dian <dianqk at dianqk.net>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
A llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll
Log Message:
-----------
[RegisterCoalescer] Clear instructions not recorded in `ErasedInstrs` but erased (#79820)
Fixes #79718. Fixes #71178.
The same instructions may exist in an iteration. We cannot immediately
delete instructions in `ErasedInstrs`.
Commit: abc39f9aa750634973fe8ba5519d6bbdd70567c4
https://github.com/llvm/llvm-project/commit/abc39f9aa750634973fe8ba5519d6bbdd70567c4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
Log Message:
-----------
[RISCV] Add casts to isel patterns that produce more than 1 instruction.
We need explicitly cast to XLenVT to avoid tablegen picking i32.
If the SelectionDAG scheduler is used it can't find a register
class for i32 if i32 isn't a legal type.
Fixes #81192, but I might have missed some patterns.
Commit: 0079136f7d2454ef2889061bb214741163ba232d
https://github.com/llvm/llvm-project/commit/0079136f7d2454ef2889061bb214741163ba232d
Author: David Green <david.green at arm.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] Fix Scale check in vscale aliasing. (#81174)
This is a fix for #80818, as pointed out in #81144 it should be checking
the abs of Scale. The added test changes from NoAlias to MayAlias.
Commit: 8316bf34ac21117f35bc8e6fafa2b3e7da75e1d5
https://github.com/llvm/llvm-project/commit/8316bf34ac21117f35bc8e6fafa2b3e7da75e1d5
Author: DianQK <dianqk at dianqk.net>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
R llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
R llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll
Log Message:
-----------
Revert "[RegisterCoalescer] Clear instructions not recorded in `ErasedInstrs` but erased (#79820)"
This reverts commit 95b14da678f4670283240ef4cf60f3a39bed97b4.
Commit: ccb46e8365787c446236df20c068d101c637346a
https://github.com/llvm/llvm-project/commit/ccb46e8365787c446236df20c068d101c637346a
Author: DianQK <dianqk at dianqk.net>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/RegisterCoalescer.cpp
A llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
A llvm/test/CodeGen/X86/PR71178-register-coalescer-crash.ll
Log Message:
-----------
Reapply "[RegisterCoalescer] Clear instructions not recorded in `ErasedInstrs` but erased (#79820)"
This reverts commit 8316bf34ac21117f35bc8e6fafa2b3e7da75e1d5.
Commit: b477d39bf6811ac12a1e7e98f308cf4c9a8de26f
https://github.com/llvm/llvm-project/commit/b477d39bf6811ac12a1e7e98f308cf4c9a8de26f
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M flang/include/flang/Evaluate/characteristics.h
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Semantics/runtime-type-info.cpp
A flang/test/Semantics/typeinfo09.f90
Log Message:
-----------
[flang] Align runtime info and lowering regarding passing ABIs (#81166)
Runtime derived type info contains information to tell the runtime if
some argument in a user defined assignment must be passed with a
descriptor or not. This information was not properly build, it would
tell the runtime that TARGET argument must be passed via descriptor,
which is incorrect.
Share the logic between lowering and runtime info generation to
determine if an argument must be passed by descriptor or not.
Commit: bc6955f18ced3ca89d49bc28eeb58cd6d367e136
https://github.com/llvm/llvm-project/commit/bc6955f18ced3ca89d49bc28eeb58cd6d367e136
Author: Diana Picus <Diana-Magda.Picus at amd.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/crash-stack-address-O0.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch-init.gfx.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-cs-chain-preserve-cc.ll
M llvm/test/CodeGen/AMDGPU/amdgpu.private-memory.ll
M llvm/test/CodeGen/AMDGPU/array-ptr-calc-i32.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs-packed.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/captured-frame-index.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cf-loop-on-constant.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes.ll
M llvm/test/CodeGen/AMDGPU/chain-hi-to-lo.ll
M llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
M llvm/test/CodeGen/AMDGPU/commute-compares.ll
M llvm/test/CodeGen/AMDGPU/control-flow-fastregalloc.ll
M llvm/test/CodeGen/AMDGPU/extload-private.ll
M llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-init.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/frame-index-elimination-tied-operand.mir
M llvm/test/CodeGen/AMDGPU/frame-index-elimination.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
M llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
M llvm/test/CodeGen/AMDGPU/kernarg-stack-alignment.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.readfirstlane.ll
M llvm/test/CodeGen/AMDGPU/load-global-i16.ll
M llvm/test/CodeGen/AMDGPU/load-global-i32.ll
M llvm/test/CodeGen/AMDGPU/memory_clause.ll
M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/partial-regcopy-and-spill-missed-at-regalloc.ll
M llvm/test/CodeGen/AMDGPU/partial-sgpr-to-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain-preserve.mir
M llvm/test/CodeGen/AMDGPU/pei-amdgpu-cs-chain.mir
M llvm/test/CodeGen/AMDGPU/regalloc-introduces-copy-sgpr-to-agpr.mir
M llvm/test/CodeGen/AMDGPU/scratch-simple.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-no-vgprs.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill.mir
M llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-offset-calculation.ll
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-special-sgpr.mir
M llvm/test/CodeGen/AMDGPU/stack-realign-kernel.ll
M llvm/test/CodeGen/AMDGPU/stack-size-overflow.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll
M llvm/test/CodeGen/AMDGPU/vgpr-spill-placement-issue61083.ll
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/DebugInfo/AMDGPU/variable-locations.ll
Log Message:
-----------
[AMDGPU] Don't fix the scavenge slot at offset 0 (#79136)
At the moment, the emergency spill slot is a fixed object for entry
functions and chain functions, and a regular stack object otherwise.
This patch adopts the latter behaviour for entry/chain functions too. It
seems this was always the intention [1] and it will also save us a bit
of stack space in cases where the first stack object has a large
alignment.
[1]
https://github.com/llvm/llvm-project/commit/34c8b835b16fb3879f1b9770e91df21883356bb6
Commit: 0d9decc6694c188e2f7fa17d140ba9bd7cc98b6b
https://github.com/llvm/llvm-project/commit/0d9decc6694c188e2f7fa17d140ba9bd7cc98b6b
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeStmtGen.cpp
M clang/test/AST/Interp/records.cpp
Log Message:
-----------
[clang][Interp] Handle invalid CXXCtorInitializer expressions
Their type might be a null type, in which case we need to abort here.
Commit: 173e674ba55eb93e8af43f2eece7feffe9954b34
https://github.com/llvm/llvm-project/commit/173e674ba55eb93e8af43f2eece7feffe9954b34
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/unittests/Format/QualifierFixerTest.cpp
Log Message:
-----------
[clang-format] Fix an out-of-bounds bug uncovered by 763139afc19d
Commit: b9079baaddfed5e604fbfaa1d81a7a1c38e78c26
https://github.com/llvm/llvm-project/commit/b9079baaddfed5e604fbfaa1d81a7a1c38e78c26
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/AsmWriterEmitter.cpp
M llvm/utils/TableGen/AsmWriterInst.cpp
M llvm/utils/TableGen/AsmWriterInst.h
M llvm/utils/TableGen/CTagsEmitter.cpp
M llvm/utils/TableGen/CallingConvEmitter.cpp
M llvm/utils/TableGen/CodeEmitterGen.cpp
M llvm/utils/TableGen/CodeGenDAGPatterns.cpp
M llvm/utils/TableGen/CodeGenDAGPatterns.h
M llvm/utils/TableGen/CodeGenHwModes.cpp
M llvm/utils/TableGen/CodeGenHwModes.h
M llvm/utils/TableGen/CodeGenInstruction.cpp
M llvm/utils/TableGen/CodeGenInstruction.h
M llvm/utils/TableGen/CodeGenIntrinsics.h
M llvm/utils/TableGen/CodeGenMapTable.cpp
M llvm/utils/TableGen/CodeGenRegisters.cpp
M llvm/utils/TableGen/CodeGenRegisters.h
M llvm/utils/TableGen/CodeGenSchedule.cpp
M llvm/utils/TableGen/CodeGenSchedule.h
M llvm/utils/TableGen/CodeGenTarget.cpp
M llvm/utils/TableGen/CodeGenTarget.h
M llvm/utils/TableGen/DAGISelEmitter.cpp
M llvm/utils/TableGen/DAGISelMatcher.cpp
M llvm/utils/TableGen/DAGISelMatcher.h
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
M llvm/utils/TableGen/DAGISelMatcherGen.cpp
M llvm/utils/TableGen/DAGISelMatcherOpt.cpp
M llvm/utils/TableGen/DFAEmitter.cpp
M llvm/utils/TableGen/DFAPacketizerEmitter.cpp
M llvm/utils/TableGen/DXILEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M llvm/utils/TableGen/DisassemblerEmitter.cpp
M llvm/utils/TableGen/FastISelEmitter.cpp
M llvm/utils/TableGen/InfoByHwMode.cpp
M llvm/utils/TableGen/InfoByHwMode.h
M llvm/utils/TableGen/InstrDocsEmitter.cpp
M llvm/utils/TableGen/InstrInfoEmitter.cpp
M llvm/utils/TableGen/IntrinsicEmitter.cpp
M llvm/utils/TableGen/OptParserEmitter.cpp
M llvm/utils/TableGen/PredicateExpander.cpp
M llvm/utils/TableGen/PseudoLoweringEmitter.cpp
M llvm/utils/TableGen/RegisterBankEmitter.cpp
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/TableGen/SDNodeProperties.h
M llvm/utils/TableGen/SearchableTableEmitter.cpp
M llvm/utils/TableGen/SequenceToOffsetTable.h
M llvm/utils/TableGen/SubtargetEmitter.cpp
M llvm/utils/TableGen/SubtargetFeatureInfo.cpp
M llvm/utils/TableGen/SubtargetFeatureInfo.h
M llvm/utils/TableGen/TableGenBackends.h
M llvm/utils/TableGen/Types.cpp
M llvm/utils/TableGen/Types.h
M llvm/utils/TableGen/WebAssemblyDisassemblerEmitter.cpp
M llvm/utils/TableGen/X86CompressEVEXTablesEmitter.cpp
M llvm/utils/TableGen/X86DisassemblerShared.h
M llvm/utils/TableGen/X86DisassemblerTables.cpp
M llvm/utils/TableGen/X86DisassemblerTables.h
M llvm/utils/TableGen/X86ModRMFilters.cpp
M llvm/utils/TableGen/X86ModRMFilters.h
M llvm/utils/TableGen/X86RecognizableInstr.cpp
M llvm/utils/TableGen/X86RecognizableInstr.h
Log Message:
-----------
[NFC] clang-format utils/TableGen (#80973)
```
find llvm/utils/TableGen -iname "*.h" -o -iname "*.cpp" | xargs clang-format-16 -i
```
Split from #80847
Commit: 2f8e37d20114ecb223caaa5a72e8b7c13daf9f34
https://github.com/llvm/llvm-project/commit/2f8e37d20114ecb223caaa5a72e8b7c13daf9f34
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/select-gep.ll
Log Message:
-----------
[SROA] Unfold gep of index select (#80983)
SROA currently supports converting a gep of select into select of gep if
the select is in the pointer operand. This patch expands support to
selects in an index operand.
This is intended to address the regression reported in
https://github.com/llvm/llvm-project/pull/68882#issuecomment-1924909922.
Commit: 38b54c72ca83fd56830b13d2a8d7749887b77922
https://github.com/llvm/llvm-project/commit/38b54c72ca83fd56830b13d2a8d7749887b77922
Author: Jean Perier <jperier at nvidia.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M flang/lib/Evaluate/characteristics.cpp
Log Message:
-----------
[flang] fix shared library builds after #81166
Fix https://lab.llvm.org/buildbot/#/builders/268/builds/7826
IsDerivedTypeWithLengthParameter cannot be used here, it would make
libFortranEvaluate dependent on linFortranSemantics.
Replace by loop through parameter values.
Commit: f6610578653fd47535a18284c688d725943ee8c3
https://github.com/llvm/llvm-project/commit/f6610578653fd47535a18284c688d725943ee8c3
Author: Jan Patrick Lehr <JanPatrick.Lehr at amd.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/call-outgoing-stack-args.ll
M llvm/test/CodeGen/AMDGPU/abi-attribute-hints-undefined-behavior.ll
M llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll
M llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
M llvm/test/CodeGen/AMDGPU/call-argument-types.ll
M llvm/test/CodeGen/AMDGPU/call-reqd-group-size.ll
M llvm/test/CodeGen/AMDGPU/call-waitcnt.ll
M llvm/test/CodeGen/AMDGPU/callee-special-input-vgprs.ll
M llvm/test/CodeGen/AMDGPU/cc-update.ll
M llvm/test/CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/kernel-vgpr-spill-mubuf-with-voffset.ll
M llvm/test/CodeGen/AMDGPU/lds-frame-extern.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.kernel.id.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-hybrid.ll
M llvm/test/CodeGen/AMDGPU/lower-module-lds-via-table.ll
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/need-fp-from-vgpr-spills.ll
M llvm/test/CodeGen/AMDGPU/simple-indirect-call.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/vgpr_constant_to_sgpr.ll
Log Message:
-----------
Revert "[AMDGPU] Compiler should synthesize private buffer resource descriptor from flat_scratch_init" (#81234)
Reverts llvm/llvm-project#79586
This broke the AMDGPU OpenMP Offload buildbot.
The typical error message was that the GPU attempted to read beyong the
largest legal address.
Error message:
AMDGPU fatal error 1: Received error in queue 0x7f8363f22000:
HSA_STATUS_ERROR_MEMORY_APERTURE_VIOLATION: The agent attempted to
access memory beyond the largest legal address.
Commit: d72e8c259637991c8d0be642a5ab2bfeb19b1c6e
https://github.com/llvm/llvm-project/commit/d72e8c259637991c8d0be642a5ab2bfeb19b1c6e
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M .git-blame-ignore-revs
Log Message:
-----------
[NFC] Add b9079ba to git-blame-ignore-revs (#81233)
Commit: df2513c80bbd444ce97d28961bd5c20ffd7d3c44
https://github.com/llvm/llvm-project/commit/df2513c80bbd444ce97d28961bd5c20ffd7d3c44
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/SemaCXX/conditional-expr.cpp
Log Message:
-----------
[clang][Interp] Fix three-way comparison detection
Instead of using !T && CPlusPlus, just check the BinaryOperator's
opcode. Turns out we also hit this code path for some assignments
of structs in C++.
Commit: 79e43eb3e20484bdb6f32eecc336742dd721fcc9
https://github.com/llvm/llvm-project/commit/79e43eb3e20484bdb6f32eecc336742dd721fcc9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
M clang/test/AST/Interp/arrays.cpp
M clang/test/SemaCXX/self-comparison.cpp
Log Message:
-----------
[clang][Interp] Protect ArrayDecay ops against dummy pointers
Commit: 9e73656af524a2c592978aec91de67316c5ce69f
https://github.com/llvm/llvm-project/commit/9e73656af524a2c592978aec91de67316c5ce69f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/SemaCXX/expression-traits.cpp
Log Message:
-----------
[clang][Interp] Support ExpressionTraitExprs
Just push a constant bool value.
Commit: 5609bd83c3bd39a7522b05b32decc9e3c8ad08ae
https://github.com/llvm/llvm-project/commit/5609bd83c3bd39a7522b05b32decc9e3c8ad08ae
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/include/clang/Format/Format.h
M clang/lib/Format/FormatToken.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
Log Message:
-----------
Revert "[clang-format] Update FormatToken::isSimpleTypeSpecifier() (#80241)"
This reverts commit 763139afc19ddf2e0f0265dc828ce8e5fbe92530.
It seems that LangOpts is not initialized before use.
Commit: 245d7727d51548c3d5d867b69b1f9b1efff2502e
https://github.com/llvm/llvm-project/commit/245d7727d51548c3d5d867b69b1f9b1efff2502e
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/unittests/Format/QualifierFixerTest.cpp
Log Message:
-----------
Revert "[clang-format] Fix an out-of-bounds bug uncovered by 763139afc19d"
This reverts commit 173e674ba55eb93e8af43f2eece7feffe9954b34.
Actually, NotTokens[5] in QualifierFixerTest.cpp is not out of bounds.
Commit: c227eca73970c65d9663e6d65abe3f9daef2a25f
https://github.com/llvm/llvm-project/commit/c227eca73970c65d9663e6d65abe3f9daef2a25f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/test/AST/Interp/arrays.cpp
Log Message:
-----------
[clang][Interp][NFC] Convert test case to verify=expected,both style
Commit: 02362b1ad1c07a01714b195d769400dd40dbfd04
https://github.com/llvm/llvm-project/commit/02362b1ad1c07a01714b195d769400dd40dbfd04
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/unittests/Format/QualifierFixerTest.cpp
Log Message:
-----------
[clang-format] Check token size in QualifierFixerTest.cpp
Commit: ac3bd2bd530127786741bd9f164d66a3c3f40961
https://github.com/llvm/llvm-project/commit/ac3bd2bd530127786741bd9f164d66a3c3f40961
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
R llvm/include/llvm/Transforms/Scalar/LoopReroll.h
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/CMakeLists.txt
R llvm/lib/Transforms/Scalar/LoopRerollPass.cpp
R llvm/test/Transforms/LoopReroll/basic.ll
R llvm/test/Transforms/LoopReroll/basic32iters.ll
R llvm/test/Transforms/LoopReroll/complex_reroll.ll
R llvm/test/Transforms/LoopReroll/external_use.ll
R llvm/test/Transforms/LoopReroll/extra_instr.ll
R llvm/test/Transforms/LoopReroll/indvar_with_ext.ll
R llvm/test/Transforms/LoopReroll/negative.ll
R llvm/test/Transforms/LoopReroll/nonconst_lb.ll
R llvm/test/Transforms/LoopReroll/ptrindvar.ll
R llvm/test/Transforms/LoopReroll/reduction.ll
R llvm/test/Transforms/LoopReroll/reroll_with_dbg.ll
Log Message:
-----------
[LoopReroll] Remove unused and unmaintained pass (#80972)
Remove the LoopReroll pass, which is both unused (in any default
pipeline) and unmaintained, with numerous open correctness issues
(https://github.com/llvm/llvm-project/issues?q=is%3Aissue+is%3Aopen+loop-reroll).
The removal is in line with
https://discourse.llvm.org/t/rfc-disallow-unmaintained-unused-passes/75151.
There is also a defunct `-freroll-loops` option in clang, which I'll
remove separately.
Migrated from https://reviews.llvm.org/D150684.
Commit: 75798f21ca7626419ed341cf723ba51889e85500
https://github.com/llvm/llvm-project/commit/75798f21ca7626419ed341cf723ba51889e85500
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Transforms/Scalar/BUILD.gn
Log Message:
-----------
[gn build] Port ac3bd2bd5301
Commit: 1198c3aaff63d4ce63b760b4effc14babc0bdd8a
https://github.com/llvm/llvm-project/commit/1198c3aaff63d4ce63b760b4effc14babc0bdd8a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] PromoteMaskArithmetic - use ISD::isBitwiseLogicOp wrapper. NFC.
Commit: 713fe6dfd4803fba41f2102479580bed058ca0b3
https://github.com/llvm/llvm-project/commit/713fe6dfd4803fba41f2102479580bed058ca0b3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] PromoteMaskArithmetic - consistently use SDValue instead of underlying SDNode. NFC.
Commit: 3902f9b6e2d925d50f9a4861d78e5aba07b6ef11
https://github.com/llvm/llvm-project/commit/3902f9b6e2d925d50f9a4861d78e5aba07b6ef11
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] PromoteMaskArithmetic - explicitly attempt to constant fold zext(c) instead of relying on getNode()
Don't rely on isBuildVectorOfConstantSDNodes/getNode to constant fold, this could also help in cases where the constant is behind a bitcast.
Noticed while investigating #80668
Commit: 2cb61a1d117e2c20e3372bc23bf12b919feaaca2
https://github.com/llvm/llvm-project/commit/2cb61a1d117e2c20e3372bc23bf12b919feaaca2
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/Sema/ms_predefined_expr.cpp
Log Message:
-----------
[clang][Interp] Fix initializing PredefinedExprs
Commit: 316373abcc2abde414d4b9601f4752b6939a2133
https://github.com/llvm/llvm-project/commit/316373abcc2abde414d4b9601f4752b6939a2133
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
Log Message:
-----------
[llvm][AArch64] Refactor expansion of CALL_BTI and CALL_RVMARKER (#80419)
After a lot of churn in expandCALL_BTI, it ended up doing the exact same
thing that expandCALL_RVMARKER does. This change factors out the common
code to make that clear.
Commit: b5a273a1cfe6f509f8d2541e04d9186438f33348
https://github.com/llvm/llvm-project/commit/b5a273a1cfe6f509f8d2541e04d9186438f33348
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M polly/lib/Analysis/ScopDetectionDiagnostic.cpp
M polly/lib/Support/ScopLocation.cpp
M polly/test/ScopDetectionDiagnostics/ReportLoopBound-01.ll
M polly/test/ScopDetectionDiagnostics/loop_has_multiple_exits.ll
Log Message:
-----------
[Polly][DebugInfo] Use getStableDebugLoc to avoid intrinsic-dependent behaviour (#81246)
Polly currently uses `getDebugLoc` in a few places to produce diagnostic
output; this is correct when interacting with specific instructions, but
may be incorrect when dealing with instruction ranges if debug
intrinsics are included. As a general rule, the debug locations attached
to debug intrinsics may be misleading compared to the surrounding
instructions, and are not generally used for anything other than
determining variable scope info; the recommended approach is therefore
to use `getStableDebugLoc` instead, which skips over debug intrinsics.
This is necessary to fix test failures that occur when enabling
non-instruction debug info, which removes debug intrinsics from basic
blocks and thus alters the diagnostic output of Polly (despite causing
no functional change).
Commit: 614fab49b0b47c6463fb4d9d788790345bfdb6ce
https://github.com/llvm/llvm-project/commit/614fab49b0b47c6463fb4d9d788790345bfdb6ce
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] PromoteMaskArithmetic - share the same SDLoc argument instead of recreating it over and over again.
Commit: 047f8321f14a53caad7b564f7f654a470fdca8a9
https://github.com/llvm/llvm-project/commit/047f8321f14a53caad7b564f7f654a470fdca8a9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] ctpop-mask.ll - add 32-bit with SSE2 test coverage
32-bit targets will try to use SSE2 <2 x i64> CTPOP expansion for i64 CTPOP
Commit: 9ba265636f3310b5b5b39767715e1843a06ea603
https://github.com/llvm/llvm-project/commit/9ba265636f3310b5b5b39767715e1843a06ea603
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] ReplaceNodeResults - shrink i64 CTPOP to (shifted) CTPOP i32 if 32 or less active bits to avoid SSE2 codegen
32-bit targets perform i64 CTPOP as a v2i64 CTPOP - if we can perform this as a i32 CTPOP by shifting the source bits, then do so to avoid the gpr<->xmm
This also triggers on non-SSE2 capable targets, as can be seen with the minor codegen diffs in ctpop_shifted_mask16
Commit: eb9cd800b3c8c787f75c00e7d9de3ae6a2e5f876
https://github.com/llvm/llvm-project/commit/eb9cd800b3c8c787f75c00e7d9de3ae6a2e5f876
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsBase.td
M clang/utils/TableGen/ClangBuiltinsEmitter.cpp
Log Message:
-----------
[Clang][TableGen] Add Features to TargetBuiltin
RISCV target will use this parameter, so we need a way to specify
it.
Reviewers: AaronBallman, philnik777
Reviewed By: AaronBallman
Pull Request: https://github.com/llvm/llvm-project/pull/80279
Commit: 345efe0df644ecbc131f7ad120744d5e8191ee6e
https://github.com/llvm/llvm-project/commit/345efe0df644ecbc131f7ad120744d5e8191ee6e
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-09 (Fri, 09 Feb 2024)
Changed paths:
M .git-blame-ignore-revs
M .github/CODEOWNERS
M .github/workflows/build-ci-container.yml
R .github/workflows/containers/github-action-ci/Dockerfile
A .github/workflows/containers/github-action-ci/bootstrap.patch
A .github/workflows/containers/github-action-ci/stage1.Dockerfile
A .github/workflows/containers/github-action-ci/stage2.Dockerfile
A .github/workflows/containers/github-action-ci/storage.conf
A .github/workflows/email-check.yaml
M .github/workflows/libclc-tests.yml
M .github/workflows/lldb-tests.yml
M .github/workflows/llvm-project-tests.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/spirv-tests.yml
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Core/BinarySection.cpp
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Profile/StaleProfileMatching.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/test/AArch64/ifunc.c
M bolt/test/X86/linux-orc.s
A bolt/test/X86/phdr-out-of-order.test
M clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp
M clang-tools-extra/clang-move/Move.cpp
M clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.cpp
M clang-tools-extra/clang-tidy/ExpandModularHeadersPPCallbacks.h
M clang-tools-extra/clang-tidy/add_new_check.py
M clang-tools-extra/clang-tidy/altera/KernelNameRestrictionCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.h
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.h
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.cpp
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.h
M clang-tools-extra/clang-tidy/llvm/HeaderGuardCheck.h
M clang-tools-extra/clang-tidy/llvm/IncludeOrderCheck.cpp
M clang-tools-extra/clang-tidy/llvmlibc/RestrictSystemLibcHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.h
M clang-tools-extra/clang-tidy/misc/HeaderIncludeCycleCheck.cpp
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.h
M clang-tools-extra/clang-tidy/modernize/DeprecatedHeadersCheck.cpp
M clang-tools-extra/clang-tidy/modernize/MacroToEnumCheck.cpp
M clang-tools-extra/clang-tidy/portability/RestrictSystemIncludesCheck.cpp
M clang-tools-extra/clang-tidy/portability/RestrictSystemIncludesCheck.h
M clang-tools-extra/clang-tidy/readability/CMakeLists.txt
M clang-tools-extra/clang-tidy/readability/DuplicateIncludeCheck.cpp
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp
A clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp
A clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h
M clang-tools-extra/clang-tidy/utils/HeaderGuard.cpp
M clang-tools-extra/clang-tidy/utils/HeaderGuard.h
M clang-tools-extra/clang-tidy/utils/IncludeInserter.cpp
M clang-tools-extra/clangd/Headers.cpp
M clang-tools-extra/clangd/ParsedAST.cpp
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/index/IndexAction.cpp
M clang-tools-extra/clangd/unittests/ReplayPeambleTests.cpp
M clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/suspicious-include.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/prefer-member-initializer.rst
M clang-tools-extra/docs/clang-tidy/checks/google/build-namespaces.rst
M clang-tools-extra/docs/clang-tidy/checks/google/global-names-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/list.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/header-guard.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/definitions-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unused-using-decls.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-anonymous-namespace.rst
A clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst
M clang-tools-extra/include-cleaner/lib/Record.cpp
M clang-tools-extra/modularize/CoverageChecker.cpp
M clang-tools-extra/modularize/PreprocessorTracker.cpp
M clang-tools-extra/pp-trace/PPCallbacksTracker.cpp
M clang-tools-extra/pp-trace/PPCallbacksTracker.h
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.yaml
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.yaml
A clang-tools-extra/test/clang-apply-replacements/format-header.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-char.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init.cpp
A clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp
M clang-tools-extra/test/clang-tidy/infrastructure/diagnostic.cpp
M clang-tools-extra/test/pp-trace/pp-trace-include.cpp
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/ClangLinkerWrapper.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/OffloadingDesign.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang-c/Index.h
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/AST/Type.h
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticCommonKinds.td
M clang/include/clang/Basic/DiagnosticDocs.td
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticFrontendKinds.td
M clang/include/clang/Basic/DiagnosticGroups.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/Specifiers.h
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/arm_neon.td
M clang/include/clang/Basic/arm_sme.td
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Lex/PPCallbacks.h
M clang/include/clang/Lex/PreprocessingRecord.h
M clang/include/clang/Lex/Preprocessor.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/include/clang/Sema/Lookup.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/include/clang/Tooling/DependencyScanning/ModuleDepCollector.h
M clang/include/clang/Tooling/Inclusions/IncludeStyle.h
M clang/include/module.modulemap
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/DeclPrinter.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/ExprConstant.cpp
M clang/lib/AST/Interp/ByteCodeEmitter.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/Interp/ByteCodeStmtGen.cpp
M clang/lib/AST/Interp/Descriptor.cpp
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/InterpBuiltin.cpp
M clang/lib/AST/Interp/Opcodes.td
M clang/lib/AST/Interp/Pointer.h
M clang/lib/AST/Interp/PrimType.h
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/Transfer.cpp
M clang/lib/Analysis/ReachableCode.cpp
M clang/lib/Analysis/UnsafeBufferUsage.cpp
M clang/lib/Basic/Sarif.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/SPIR.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGDebugInfo.cpp
M clang/lib/CodeGen/CGExprScalar.cpp
M clang/lib/CodeGen/CGGPUBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/MacroPPCallbacks.cpp
M clang/lib/CodeGen/MacroPPCallbacks.h
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Format/BreakableToken.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/DependencyFile.cpp
M clang/lib/Frontend/DependencyGraph.cpp
M clang/lib/Frontend/ModuleDependencyCollector.cpp
M clang/lib/Frontend/PrecompiledPreamble.cpp
M clang/lib/Frontend/PrintPreprocessedOutput.cpp
M clang/lib/Frontend/Rewrite/InclusionRewriter.cpp
M clang/lib/Frontend/TextDiagnostic.cpp
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/FrontendTool/ExecuteCompilerInvocation.cpp
M clang/lib/Headers/cpuid.h
M clang/lib/Lex/PPDirectives.cpp
M clang/lib/Lex/PPExpressions.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Lex/PreprocessingRecord.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaRISCVVectorLookup.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
M clang/lib/StaticAnalyzer/Checkers/BuiltinFunctionChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
M clang/lib/Tooling/DependencyScanning/ModuleDepCollector.cpp
M clang/lib/Tooling/Inclusions/HeaderIncludes.cpp
M clang/lib/Tooling/Inclusions/IncludeStyle.cpp
M clang/test/AST/Interp/arrays.cpp
A clang/test/AST/Interp/atomic.c
A clang/test/AST/Interp/atomic.cpp
M clang/test/AST/Interp/builtin-functions.cpp
M clang/test/AST/Interp/builtins.cpp
M clang/test/AST/Interp/c.c
M clang/test/AST/Interp/complex.cpp
M clang/test/AST/Interp/cxx20.cpp
M clang/test/AST/Interp/cxx98.cpp
M clang/test/AST/Interp/lambda.cpp
M clang/test/AST/Interp/literals.cpp
M clang/test/AST/Interp/records.cpp
M clang/test/AST/Interp/switch.cpp
A clang/test/AST/ast-dump-pack-indexing-crash.cpp
M clang/test/AST/ast-print-method-decl.cpp
A clang/test/AST/fixed-point-zero-init.cpp
M clang/test/AST/ms-constexpr.cpp
A clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp
M clang/test/Analysis/Inputs/std-c-library-functions-POSIX.h
M clang/test/Analysis/builtin-functions.cpp
A clang/test/Analysis/html_diagnostics/counter.c
M clang/test/Analysis/out-of-bounds-diagnostics.c
A clang/test/Analysis/out-of-bounds-notes.c
M clang/test/Analysis/std-c-library-functions-POSIX.c
M clang/test/Analysis/std-c-library-functions.c
M clang/test/Analysis/stream-error.c
M clang/test/Analysis/stream-noopen.c
M clang/test/Analysis/stream.c
M clang/test/CXX/class.derived/class.member.lookup/p11.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.fct/p23.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.meaning.general/p3.cpp
M clang/test/CXX/drs/dr23xx.cpp
A clang/test/CXX/drs/dr28xx.cpp
M clang/test/CXX/drs/dr7xx.cpp
M clang/test/CXX/temp/p3.cpp
M clang/test/CXX/temp/temp.decls/temp.class/temp.mem.func/p1.cpp
A clang/test/CXX/temp/temp.names/p5.cpp
M clang/test/CXX/temp/temp.spec/part.spec.cpp
M clang/test/CodeGen/RISCV/riscv-inline-asm.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
M clang/test/CodeGen/aarch64-inline-asm.c
M clang/test/CodeGen/aarch64-neon-intrinsics.c
M clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c
M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c
M clang/test/CodeGen/aarch64-targetattr.c
M clang/test/CodeGen/debug-info-cc.c
M clang/test/CodeGen/fp128_complex.c
M clang/test/CodeGen/preserve-call-conv.c
M clang/test/CodeGen/target-builtin-noerror.c
A clang/test/CodeGen/ubsan-shift-bitint.c
M clang/test/CodeGenCUDA/amdgpu-code-object-version-linking.cu
M clang/test/CodeGenCUDA/amdgpu-code-object-version.cu
M clang/test/CodeGenCUDA/amdgpu-workgroup-size.cu
A clang/test/CodeGenCUDA/printf-builtin.cu
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenCXX/dynamic-cast-dead.cpp
M clang/test/CodeGenCXX/dynamic-cast.cpp
A clang/test/CodeGenHIP/printf-builtin.hip
M clang/test/CodeGenHLSL/builtins/RWBuffer-constructor.hlsl
A clang/test/CodeGenHLSL/shift-mask.hlsl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn.cl
M clang/test/CoverageMapping/if.cpp
A clang/test/Driver/Inputs/rocm/amdgcn/bitcode/oclc_abi_version_600.bc
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
R clang/test/Driver/android-version.cpp
A clang/test/Driver/basic-block-address-map.c
M clang/test/Driver/fbasic-block-sections.c
M clang/test/Driver/hip-code-object-version.hip
M clang/test/Driver/hip-device-libs.hip
M clang/test/Driver/hip-options.hip
A clang/test/Driver/invalid-version.cpp
M clang/test/Driver/linker-wrapper-image.c
M clang/test/Driver/linker-wrapper.c
M clang/test/Driver/mips-features.c
M clang/test/Driver/rocm-detect.hip
A clang/test/Driver/sparc64-codemodel.c
M clang/test/Driver/wasm-features.c
M clang/test/Format/clang-format-ignore.cpp
M clang/test/Format/dump-config-objc-stdin.m
M clang/test/Format/verbose.cpp
M clang/test/Frontend/fixed_point_bit_widths.c
M clang/test/Frontend/fixed_point_errors.cpp
M clang/test/Frontend/verify.c
M clang/test/Headers/__clang_hip_cmath.hip
M clang/test/Headers/__clang_hip_math.hip
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
M clang/test/Misc/warning-flags.c
M clang/test/Modules/aarch64-sme-keywords.cppm
A clang/test/OpenMP/bug69085.c
M clang/test/OpenMP/declare_simd_messages.cpp
M clang/test/OpenMP/for_loop_auto.cpp
M clang/test/Preprocessor/aarch64-target-features.c
A clang/test/Preprocessor/has_builtin_cpuid.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Preprocessor/wasm-target-features.c
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/aarch64-sme-func-attrs.c
M clang/test/Sema/atomic-expr.c
M clang/test/Sema/attr-aligned.c
M clang/test/Sema/auto-type.c
M clang/test/Sema/conversion-64-32.c
A clang/test/Sema/conversion-implicit-int-includes-64-to-32.c
M clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c
M clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c
M clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c
M clang/test/Sema/inline-asm-validate-aarch64.c
M clang/test/Sema/inline-asm-validate-riscv.c
M clang/test/Sema/ms_predefined_expr.cpp
M clang/test/Sema/no_callconv.cpp
M clang/test/Sema/objc-bool-constant-conversion.m
A clang/test/Sema/preserve-none-call-conv.c
M clang/test/Sema/rvv-required-features-invalid.c
M clang/test/Sema/struct-cast.c
M clang/test/Sema/warn-cast-qual.c
M clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp
M clang/test/Sema/warn-infinity-nan-disabled-win.cpp
M clang/test/Sema/warn-int-in-bool-context.c
M clang/test/SemaCXX/compound-literal.cpp
M clang/test/SemaCXX/conditional-expr.cpp
A clang/test/SemaCXX/coroutine-unreachable-warning.cpp
M clang/test/SemaCXX/cxx11-default-member-initializers.cpp
M clang/test/SemaCXX/cxx1z-copy-omission.cpp
M clang/test/SemaCXX/cxx20-using-enum.cpp
M clang/test/SemaCXX/cxx2b-deducing-this.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
M clang/test/SemaCXX/datasizeof.cpp
M clang/test/SemaCXX/decomposition-openmp.cpp
M clang/test/SemaCXX/expression-traits.cpp
M clang/test/SemaCXX/function-type-qual.cpp
A clang/test/SemaCXX/libstdcxx_is_nothrow_convertible_hack.cpp
M clang/test/SemaCXX/pr72025.cpp
M clang/test/SemaCXX/self-comparison.cpp
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaCXX/warn-unsafe-buffer-usage-debug.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave64.cl
M clang/test/SemaOpenCL/operators.cl
M clang/test/SemaTemplate/class-template-spec.cpp
M clang/test/SemaTemplate/concepts-out-of-line-def.cpp
M clang/test/SemaTemplate/concepts-recovery-expr.cpp
A clang/test/SemaTemplate/default-parm-init.cpp
M clang/tools/clang-format/ClangFormat.cpp
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
M clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td
M clang/tools/libclang/CXType.cpp
M clang/tools/libclang/Indexing.cpp
M clang/unittests/AST/ASTExprTest.cpp
M clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp
M clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp
M clang/unittests/Analysis/FlowSensitive/UncheckedOptionalAccessModelTest.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/unittests/Format/FormatTestComments.cpp
M clang/unittests/Format/QualifierFixerTest.cpp
M clang/unittests/Format/SortIncludesTest.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M clang/unittests/Lex/PPCallbacksTest.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/perf-training/CMakeLists.txt
M clang/utils/perf-training/perf-helper.py
M compiler-rt/lib/asan/asan_descriptions.cpp
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/builtins/i386/chkstk.S
M compiler-rt/lib/builtins/x86_64/chkstk.S
M compiler-rt/lib/hwasan/hwasan_report.cpp
M compiler-rt/lib/memprof/memprof_allocator.cpp
M compiler-rt/lib/memprof/memprof_allocator.h
M compiler-rt/lib/memprof/memprof_descriptions.cpp
M compiler-rt/lib/memprof/memprof_interceptors.cpp
M compiler-rt/lib/memprof/memprof_internal.h
M compiler-rt/lib/memprof/memprof_malloc_linux.cpp
M compiler-rt/lib/memprof/memprof_mapping.h
M compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
M compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp
M compiler-rt/lib/scudo/standalone/combined.h
M compiler-rt/lib/scudo/standalone/tests/combined_test.cpp
M compiler-rt/lib/scudo/standalone/tests/tsd_test.cpp
M compiler-rt/lib/scudo/standalone/tsd_exclusive.h
M compiler-rt/lib/scudo/standalone/tsd_shared.h
M flang/docs/AliasingAnalysisFIR.md
M flang/docs/FIRArrayOperations.md
M flang/docs/FlangDriver.md
M flang/docs/FortranLLVMTestSuite.md
M flang/docs/HighLevelFIR.md
M flang/docs/OpenACC-descriptor-management.md
A flang/docs/OpenMP-descriptor-management.md
M flang/docs/Overview.md
M flang/docs/ParameterizedDerivedTypes.md
M flang/docs/PolymorphicEntities.md
M flang/docs/ProcedurePointer.md
M flang/docs/conf.py
M flang/docs/fstack-arrays.md
M flang/docs/index.md
M flang/include/flang/Evaluate/characteristics.h
M flang/include/flang/Lower/ConvertCall.h
M flang/include/flang/Lower/ConvertVariable.h
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Builder/HLFIRTools.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Builder/MutableBox.h
A flang/include/flang/Optimizer/CodeGen/CodeGenOpenMP.h
M flang/include/flang/Optimizer/Dialect/FIRAttr.td
M flang/include/flang/Optimizer/Dialect/FIRDialect.h
M flang/include/flang/Optimizer/Dialect/FIROps.td
M flang/include/flang/Optimizer/Dialect/FIROpsSupport.h
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/include/flang/Optimizer/HLFIR/HLFIROps.td
M flang/include/flang/Optimizer/Support/InitFIR.h
M flang/include/flang/Optimizer/Support/Utils.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/CallInterface.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExpr.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Builder/HLFIRTools.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Builder/MutableBox.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
A flang/lib/Optimizer/CodeGen/CodeGenOpenMP.cpp
M flang/lib/Optimizer/Dialect/CMakeLists.txt
M flang/lib/Optimizer/Dialect/FIRAttr.cpp
M flang/lib/Optimizer/Dialect/FIRDialect.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/lib/Optimizer/Transforms/OMPDescriptorMapInfoGen.cpp
M flang/lib/Parser/preprocessor.cpp
M flang/lib/Semantics/resolve-directives.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/lib/Semantics/runtime-type-info.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-8.fir
A flang/test/Driver/aarch64-outline-atomics.f90
M flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
A flang/test/Driver/func-attr-fast-math.f90
M flang/test/Driver/target-cpu-features.f90
A flang/test/Fir/OpenACC/legalize-data.fir
A flang/test/Fir/OpenACC/propagate-attr-folding.fir
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Fir/fir-ops.fir
A flang/test/HLFIR/as_expr-codegen-polymorphic.fir
M flang/test/HLFIR/bufferize-poly-expr.fir
M flang/test/HLFIR/invalid.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
A flang/test/Integration/aarch64-outline-atomics.f90
M flang/test/Lower/AMD/code-object-version.f90
A flang/test/Lower/CUDA/cuda-data-attribute.cuf
M flang/test/Lower/HLFIR/array-ctor-character.f90
M flang/test/Lower/HLFIR/function-return-as-expr.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/procedure-pointer.f90
A flang/test/Lower/Intrinsics/acosd.f90
A flang/test/Lower/Intrinsics/asind.f90
A flang/test/Lower/Intrinsics/atan2d.f90
A flang/test/Lower/Intrinsics/atan2pi.f90
M flang/test/Lower/Intrinsics/atand.f90
A flang/test/Lower/Intrinsics/atanpi.f90
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-loop.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/FIR/array-bounds.f90
M flang/test/Lower/OpenMP/FIR/target.f90
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
A flang/test/Lower/OpenMP/allocatable-array-bounds.f90
A flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
A flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/nullify-polymorphic.f90
M flang/test/Lower/target-features-amdgcn.f90
M flang/test/Lower/target-features-x86_64.f90
M flang/test/Semantics/OpenMP/copyprivate03.f90
A flang/test/Semantics/typeinfo09.f90
A flang/test/Transforms/omp-descriptor-map-info-gen.fir
M flang/tools/bbc/bbc.cpp
M flang/tools/fir-opt/fir-opt.cpp
M flang/tools/tco/tco.cpp
M flang/unittests/Optimizer/FortranVariableTest.cpp
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/cmake/modules/LLVMLibCLibraryRules.cmake
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/index.rst
A libc/docs/libc_search.rst
M libc/docs/math/index.rst
M libc/docs/stdbit.rst
M libc/include/CMakeLists.txt
M libc/include/errno.h.def
M libc/include/inttypes.h.def
M libc/include/llvm-libc-macros/CMakeLists.txt
A libc/include/llvm-libc-macros/inttypes-macros.h
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/float128.h
M libc/include/math.h.def
M libc/spec/posix.td
M libc/spec/spec.td
M libc/spec/stdc.td
M libc/src/__support/CMakeLists.txt
M libc/src/__support/CPP/expected.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
R libc/src/__support/FPUtil/XFloat.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
M libc/src/__support/GPU/amdgpu/utils.h
M libc/src/__support/float_to_string.h
A libc/src/__support/intrusive_list.h
M libc/src/__support/macros/properties/CMakeLists.txt
M libc/src/__support/macros/properties/float.h
M libc/src/errno/CMakeLists.txt
M libc/src/errno/libc_errno.cpp
M libc/src/errno/libc_errno.h
M libc/src/math/CMakeLists.txt
A libc/src/math/ceilf128.h
A libc/src/math/floorf128.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/ceilf128.cpp
A libc/src/math/generic/floorf128.cpp
A libc/src/math/generic/roundf128.cpp
A libc/src/math/generic/truncf128.cpp
M libc/src/math/gpu/vendor/amdgpu/platform.h
A libc/src/math/roundf128.h
A libc/src/math/truncf128.h
M libc/src/search/CMakeLists.txt
A libc/src/search/insque.cpp
A libc/src/search/insque.h
A libc/src/search/remque.cpp
A libc/src/search/remque.h
M libc/src/stdbit/CMakeLists.txt
A libc/src/stdbit/stdc_leading_ones_uc.cpp
A libc/src/stdbit/stdc_leading_ones_uc.h
A libc/src/stdbit/stdc_leading_ones_ui.cpp
A libc/src/stdbit/stdc_leading_ones_ui.h
A libc/src/stdbit/stdc_leading_ones_ul.cpp
A libc/src/stdbit/stdc_leading_ones_ul.h
A libc/src/stdbit/stdc_leading_ones_ull.cpp
A libc/src/stdbit/stdc_leading_ones_ull.h
A libc/src/stdbit/stdc_leading_ones_us.cpp
A libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
A libc/src/stdbit/stdc_trailing_ones_uc.cpp
A libc/src/stdbit/stdc_trailing_ones_uc.h
A libc/src/stdbit/stdc_trailing_ones_ui.cpp
A libc/src/stdbit/stdc_trailing_ones_ui.h
A libc/src/stdbit/stdc_trailing_ones_ul.cpp
A libc/src/stdbit/stdc_trailing_ones_ul.h
A libc/src/stdbit/stdc_trailing_ones_ull.cpp
A libc/src/stdbit/stdc_trailing_ones_ull.h
A libc/src/stdbit/stdc_trailing_ones_us.cpp
A libc/src/stdbit/stdc_trailing_ones_us.h
A libc/src/stdbit/stdc_trailing_zeros_uc.cpp
A libc/src/stdbit/stdc_trailing_zeros_uc.h
A libc/src/stdbit/stdc_trailing_zeros_ui.cpp
A libc/src/stdbit/stdc_trailing_zeros_ui.h
A libc/src/stdbit/stdc_trailing_zeros_ul.cpp
A libc/src/stdbit/stdc_trailing_zeros_ul.h
A libc/src/stdbit/stdc_trailing_zeros_ull.cpp
A libc/src/stdbit/stdc_trailing_zeros_ull.h
A libc/src/stdbit/stdc_trailing_zeros_us.cpp
A libc/src/stdbit/stdc_trailing_zeros_us.h
M libc/src/stdio/printf_core/converter.cpp
M libc/src/stdio/printf_core/int_converter.h
M libc/src/stdio/printf_core/parser.h
M libc/src/sys/epoll/linux/epoll_wait.cpp
M libc/src/unistd/linux/CMakeLists.txt
M libc/src/unistd/linux/pread.cpp
M libc/startup/gpu/CMakeLists.txt
M libc/startup/gpu/amdgpu/CMakeLists.txt
M libc/startup/gpu/nvptx/CMakeLists.txt
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/IntegrationTest/test.h
M libc/test/UnitTest/ErrnoSetterMatcher.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/UnitTest/FuchsiaTest.h
M libc/test/UnitTest/LibcTest.h
M libc/test/include/stdbit_test.cpp
M libc/test/integration/src/pthread/pthread_create_test.cpp
M libc/test/integration/src/pthread/pthread_join_test.cpp
M libc/test/integration/src/unistd/getcwd_test.cpp
M libc/test/integration/startup/linux/tls_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/__support/str_to_double_test.cpp
M libc/test/src/__support/str_to_float_test.cpp
M libc/test/src/__support/str_to_fp_test.h
M libc/test/src/dirent/dirent_test.cpp
M libc/test/src/errno/errno_test.cpp
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/acosf_test.cpp
M libc/test/src/math/acoshf_test.cpp
M libc/test/src/math/asinf_test.cpp
M libc/test/src/math/asinhf_test.cpp
M libc/test/src/math/atanf_test.cpp
M libc/test/src/math/atanhf_test.cpp
M libc/test/src/math/cosf_test.cpp
M libc/test/src/math/coshf_test.cpp
M libc/test/src/math/exp10_test.cpp
M libc/test/src/math/exp10f_test.cpp
M libc/test/src/math/exp2_test.cpp
M libc/test/src/math/exp2f_test.cpp
M libc/test/src/math/exp_test.cpp
M libc/test/src/math/expf_test.cpp
M libc/test/src/math/expm1_test.cpp
M libc/test/src/math/expm1f_test.cpp
M libc/test/src/math/log10_test.cpp
M libc/test/src/math/log1p_test.cpp
M libc/test/src/math/log1pf_test.cpp
M libc/test/src/math/log2_test.cpp
M libc/test/src/math/log2f_test.cpp
M libc/test/src/math/log_test.cpp
M libc/test/src/math/powf_test.cpp
M libc/test/src/math/sincosf_test.cpp
M libc/test/src/math/sinf_test.cpp
M libc/test/src/math/sinhf_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
M libc/test/src/math/smoke/RoundToIntegerTest.h
M libc/test/src/math/smoke/acosf_test.cpp
M libc/test/src/math/smoke/acoshf_test.cpp
M libc/test/src/math/smoke/asinf_test.cpp
M libc/test/src/math/smoke/asinhf_test.cpp
M libc/test/src/math/smoke/atanf_test.cpp
M libc/test/src/math/smoke/atanhf_test.cpp
A libc/test/src/math/smoke/ceilf128_test.cpp
M libc/test/src/math/smoke/cosf_test.cpp
M libc/test/src/math/smoke/coshf_test.cpp
M libc/test/src/math/smoke/exp10f_test.cpp
M libc/test/src/math/smoke/exp2f_test.cpp
M libc/test/src/math/smoke/expf_test.cpp
M libc/test/src/math/smoke/expm1f_test.cpp
A libc/test/src/math/smoke/floorf128_test.cpp
A libc/test/src/math/smoke/roundf128_test.cpp
M libc/test/src/math/smoke/sincosf_test.cpp
M libc/test/src/math/smoke/sinf_test.cpp
M libc/test/src/math/smoke/sinhf_test.cpp
M libc/test/src/math/smoke/tanf_test.cpp
M libc/test/src/math/smoke/tanhf_test.cpp
A libc/test/src/math/smoke/truncf128_test.cpp
M libc/test/src/math/tanf_test.cpp
M libc/test/src/math/tanhf_test.cpp
M libc/test/src/sched/affinity_test.cpp
M libc/test/src/sched/cpu_count_test.cpp
M libc/test/src/sched/get_priority_test.cpp
M libc/test/src/sched/param_and_scheduler_test.cpp
M libc/test/src/sched/sched_rr_get_interval_test.cpp
M libc/test/src/sched/yield_test.cpp
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/insque_test.cpp
M libc/test/src/signal/sigaltstack_test.cpp
M libc/test/src/signal/signal_test.cpp
M libc/test/src/signal/sigprocmask_test.cpp
M libc/test/src/stdbit/CMakeLists.txt
A libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_ui_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_ul_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_ull_test.cpp
A libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp
A libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp
M libc/test/src/stdio/CMakeLists.txt
M libc/test/src/stdio/fgetc_test.cpp
M libc/test/src/stdio/fgetc_unlocked_test.cpp
M libc/test/src/stdio/fgets_test.cpp
M libc/test/src/stdio/fileop_test.cpp
M libc/test/src/stdio/fopencookie_test.cpp
M libc/test/src/stdio/printf_core/converter_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdio/setvbuf_test.cpp
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdio/unlocked_fileop_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/stdlib/atof_test.cpp
M libc/test/src/stdlib/strtod_test.cpp
M libc/test/src/stdlib/strtof_test.cpp
M libc/test/src/stdlib/strtoint32_test.cpp
M libc/test/src/stdlib/strtoint64_test.cpp
M libc/test/src/stdlib/strtold_test.cpp
M libc/test/src/string/strdup_test.cpp
M libc/test/src/sys/mman/linux/madvise_test.cpp
M libc/test/src/sys/mman/linux/mincore_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mmap_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/prctl/linux/prctl_test.cpp
M libc/test/src/sys/random/linux/getrandom_test.cpp
M libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp
M libc/test/src/sys/select/select_ui_test.cpp
M libc/test/src/sys/sendfile/sendfile_test.cpp
M libc/test/src/sys/stat/chmod_test.cpp
M libc/test/src/sys/stat/fchmod_test.cpp
M libc/test/src/sys/stat/fchmodat_test.cpp
M libc/test/src/sys/stat/fstat_test.cpp
M libc/test/src/sys/stat/lstat_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/sys/stat/stat_test.cpp
M libc/test/src/termios/termios_test.cpp
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
M libc/test/src/time/gmtime_test.cpp
M libc/test/src/time/nanosleep_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/syscall_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M libc/utils/HdrGen/PublicAPICommand.cpp
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__bit_reference
M libcxx/include/__compare/strong_order.h
M libcxx/include/__compare/weak_order.h
M libcxx/include/__config
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__locale
A libcxx/include/__locale_dir/locale_base_api.h
A libcxx/include/__locale_dir/locale_base_api/android.h
A libcxx/include/__locale_dir/locale_base_api/fuchsia.h
A libcxx/include/__locale_dir/locale_base_api/ibm.h
A libcxx/include/__locale_dir/locale_base_api/musl.h
A libcxx/include/__locale_dir/locale_base_api/newlib.h
A libcxx/include/__locale_dir/locale_base_api/openbsd.h
A libcxx/include/__locale_dir/locale_base_api/win32.h
M libcxx/include/__memory/allocate_at_least.h
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/temporary_buffer.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
R libcxx/include/__support/android/locale_bionic.h
R libcxx/include/__support/fuchsia/xlocale.h
R libcxx/include/__support/ibm/xlocale.h
R libcxx/include/__support/musl/xlocale.h
R libcxx/include/__support/newlib/xlocale.h
R libcxx/include/__support/openbsd/xlocale.h
R libcxx/include/__support/win32/locale_win32.h
M libcxx/include/__support/xlocale/__posix_l_fallback.h
M libcxx/include/__thread/support/c11.h
M libcxx/include/__type_traits/is_nothrow_convertible.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/compare
R libcxx/include/experimental/__memory
M libcxx/include/libcxx.imp
M libcxx/include/limits
M libcxx/include/memory
M libcxx/include/module.modulemap.in
M libcxx/include/ostream
M libcxx/include/scoped_allocator
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/string
M libcxx/include/valarray
M libcxx/include/vector
M libcxx/include/version
M libcxx/modules/std/memory.inc
M libcxx/src/locale.cpp
M libcxx/test/libcxx/containers/sequences/deque/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/list/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/vector.bool/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/vector/abi.compile.pass.cpp
A libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/get.pass.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
A libcxx/test/std/containers/sequences/vector/vector.modifiers/destory_elements.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/and_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/divide_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/minus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/modulo_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/or_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/plus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_left_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_right_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/times_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/xor_valarray.pass.cpp
A libcxx/test/std/thread/thread.semaphore/lost_wakeup.pass.cpp
M libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.cnstr/allocs.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.signed_integral.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.unsigned_integral.pass.cpp
R libcxx/test/std/utilities/memory/allocator.traits/allocate_at_least.pass.cpp
A libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_at_least.pass.cpp
M libcxx/test/support/count_new.h
M libcxx/utils/generate_feature_test_macro_components.py
M libcxxabi/src/cxa_exception_storage.cpp
M libcxxabi/src/cxa_guard_impl.h
M libcxxabi/src/cxa_thread_atexit.cpp
M libcxxabi/src/fallback_malloc.cpp
M libcxxabi/src/private_typeinfo.cpp
M libcxxabi/test/test_fallback_malloc.pass.cpp
M libunwind/CMakeLists.txt
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Arch/LoongArch.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/InputSection.cpp
M lld/ELF/InputSection.h
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
M lld/ELF/Target.h
M lld/ELF/Writer.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/COFF/def-export-cpp.s
M lld/test/COFF/def-export-stdcall.s
M lld/test/COFF/dllexport.s
M lld/test/ELF/amdgpu-tid.s
M lld/test/ELF/linkerscript/insert-before.test
A lld/test/ELF/loongarch-relax-align.s
A lld/test/ELF/loongarch-relax-emit-relocs.s
A lld/test/ELF/lto/basic-block-address-map.ll
M lld/test/ELF/segments.s
M lld/test/MachO/objc-category-conflicts.s
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
M lld/test/wasm/build-id.test
M lld/test/wasm/merge-string-debug.s
M lld/test/wasm/startstop.ll
M lld/wasm/InputFiles.cpp
M lldb/bindings/headers.swig
A lldb/bindings/interface/SBStatisticsOptionsDocstrings.i
M lldb/bindings/interfaces.swig
M lldb/docs/lldb-gdb-remote.txt
M lldb/docs/use/python-reference.rst
M lldb/include/lldb/API/LLDB.h
M lldb/include/lldb/API/SBCommandInterpreter.h
M lldb/include/lldb/API/SBDebugger.h
M lldb/include/lldb/API/SBDefines.h
M lldb/include/lldb/API/SBProcess.h
A lldb/include/lldb/API/SBStatisticsOptions.h
M lldb/include/lldb/API/SBStructuredData.h
M lldb/include/lldb/API/SBTarget.h
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/include/lldb/Core/Debugger.h
M lldb/include/lldb/Core/ModuleList.h
M lldb/include/lldb/DataFormatters/FormatCache.h
M lldb/include/lldb/DataFormatters/FormatManager.h
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
M lldb/include/lldb/DataFormatters/TypeSynthetic.h
M lldb/include/lldb/DataFormatters/VectorIterator.h
M lldb/include/lldb/Interpreter/CommandInterpreter.h
M lldb/include/lldb/Target/PostMortemProcess.h
M lldb/include/lldb/Target/Process.h
M lldb/include/lldb/Target/ProcessTrace.h
M lldb/include/lldb/Target/Statistics.h
M lldb/include/lldb/Target/Target.h
M lldb/include/lldb/lldb-enumerations.h
M lldb/include/lldb/lldb-forward.h
M lldb/include/lldb/lldb-private-enumerations.h
M lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py
M lldb/source/API/CMakeLists.txt
M lldb/source/API/SBCommandInterpreter.cpp
M lldb/source/API/SBProcess.cpp
A lldb/source/API/SBStatisticsOptions.cpp
M lldb/source/API/SBTarget.cpp
M lldb/source/Breakpoint/WatchpointAlgorithms.cpp
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/source/Commands/CommandObjectCommands.cpp
M lldb/source/Commands/CommandObjectStats.cpp
M lldb/source/Commands/Options.td
M lldb/source/Core/CoreProperties.td
M lldb/source/Core/FormatEntity.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Core/ValueObjectSyntheticFilter.cpp
M lldb/source/DataFormatters/FormatCache.cpp
M lldb/source/DataFormatters/FormatManager.cpp
M lldb/source/DataFormatters/TypeSynthetic.cpp
M lldb/source/DataFormatters/VectorType.cpp
M lldb/source/Interpreter/CommandInterpreter.cpp
M lldb/source/Interpreter/CommandObject.cpp
M lldb/source/Interpreter/OptionArgParser.cpp
M lldb/source/Plugins/Language/CPlusPlus/BlockPointer.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/Language/CPlusPlus/Coroutines.cpp
M lldb/source/Plugins/Language/CPlusPlus/Coroutines.h
M lldb/source/Plugins/Language/CPlusPlus/GenericBitset.cpp
M lldb/source/Plugins/Language/CPlusPlus/GenericOptional.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.h
M lldb/source/Plugins/Language/CPlusPlus/LibCxxAtomic.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxInitializerList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxList.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxQueue.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxRangesRefView.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxSpan.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxTuple.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxUnorderedMap.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVariant.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxxVector.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcpp.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcppTuple.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibStdcppUniquePointer.cpp
M lldb/source/Plugins/Language/ObjC/Cocoa.cpp
M lldb/source/Plugins/Language/ObjC/NSArray.cpp
M lldb/source/Plugins/Language/ObjC/NSDictionary.cpp
M lldb/source/Plugins/Language/ObjC/NSError.cpp
M lldb/source/Plugins/Language/ObjC/NSException.cpp
M lldb/source/Plugins/Language/ObjC/NSIndexPath.cpp
M lldb/source/Plugins/Language/ObjC/NSSet.cpp
M lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp
M lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp
M lldb/source/Plugins/Process/elf-core/ProcessElfCore.h
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h
M lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp
M lldb/source/Plugins/Process/mach-core/ProcessMachCore.h
M lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp
M lldb/source/Plugins/Process/minidump/ProcessMinidump.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp
M lldb/source/Symbol/SymbolLocator.cpp
M lldb/source/Target/ProcessTrace.cpp
M lldb/source/Target/Statistics.cpp
M lldb/source/Target/Target.cpp
M lldb/source/Target/TargetList.cpp
M lldb/source/Utility/ConstString.cpp
M lldb/test/API/commands/statistics/basic/TestStats.py
A lldb/test/API/commands/target/debuginfo/TestDebugInfoSize.py
A lldb/test/API/commands/target/debuginfo/a.out-foo.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out-main.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out.yaml
M lldb/test/API/functionalities/data-formatter/data-formatter-stl/libcxx/chrono/TestDataFormatterLibcxxChrono.py
M lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py
M lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py
M lldb/test/API/functionalities/stats_api/main.c
M lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/test/API/macosx/universal/Makefile
M lldb/test/API/python_api/target/TestTargetAPI.py
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
M lldb/unittests/Core/CMakeLists.txt
M lldb/unittests/Core/DiagnosticEventTest.cpp
A lldb/unittests/Core/ProgressReportTest.cpp
M lldb/unittests/TestingSupport/TestUtilities.cpp
M lldb/unittests/TestingSupport/TestUtilities.h
M llvm/CMakeLists.txt
M llvm/cmake/modules/HandleLLVMOptions.cmake
M llvm/docs/AArch64SME.rst
M llvm/docs/AdvancedBuilds.rst
M llvm/docs/CMake.rst
M llvm/docs/CodeReview.rst
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/docs/CommandGuide/llvm-mca.rst
M llvm/docs/CommandGuide/llvm-objcopy.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/GettingStarted.rst
M llvm/docs/GitHub.rst
M llvm/docs/LangRef.rst
M llvm/docs/NVPTXUsage.rst
M llvm/docs/Passes.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/SecurityTransparencyReports.rst
M llvm/docs/TableGen/BackEnds.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/docs/UserGuides.rst
M llvm/docs/WritingAnLLVMNewPMPass.rst
M llvm/docs/WritingAnLLVMPass.rst
M llvm/include/llvm/ADT/StringMap.h
M llvm/include/llvm/ADT/ilist_iterator.h
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/TypeMetadataUtils.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/AsmParser/LLToken.h
M llvm/include/llvm/BinaryFormat/Dwarf.def
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/BinaryFormat/XCOFF.h
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CommandFlags.h
A llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachineFunction.h
M llvm/include/llvm/CodeGen/MachineModuleInfo.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/include/llvm/CodeGen/Register.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/CodeGen/ValueTypes.td
M llvm/include/llvm/DebugInfo/DIContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h
M llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
A llvm/include/llvm/IR/Analysis.h
M llvm/include/llvm/IR/CallingConv.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/IntrinsicsSPIRV.td
M llvm/include/llvm/IR/ModuleSummaryIndex.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/IR/PatternMatch.h
M llvm/include/llvm/MC/MCAssembler.h
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/ObjCopy/CommonConfig.h
M llvm/include/llvm/Object/COFFImportFile.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/Object/Wasm.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/ObjectYAML/XCOFFYAML.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/InstrProf.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/Support/AMDGPUMetadata.h
M llvm/include/llvm/Support/ScopedPrinter.h
M llvm/include/llvm/Target/GlobalISel/Combine.td
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/Target/TargetSchedule.td
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TextAPI/Utils.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
R llvm/include/llvm/Transforms/Scalar/LoopReroll.h
M llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/DomConditionCache.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/TypeMetadataUtils.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/AsmParser/LLLexer.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/AtomicExpandPass.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/DeadMachineInstructionElim.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachineModuleInfo.cpp
M llvm/lib/CodeGen/MachinePassManager.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/RegisterCoalescer.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
M llvm/lib/CodeGen/ValueTypes.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerImpl.h
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp
M llvm/lib/ExecutionEngine/JITLink/MachO_arm64.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/ConstantRange.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/XCOFFObjectWriter.cpp
M llvm/lib/ObjCopy/ConfigManager.cpp
M llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp
M llvm/lib/Object/COFFImportFile.cpp
M llvm/lib/Object/COFFModuleDefinition.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/OffloadBinary.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/ObjectYAML/XCOFFEmitter.cpp
M llvm/lib/ObjectYAML/XCOFFYAML.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/Support/FormatVariadic.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Support/StringMap.cpp
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp
M llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.td
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMInstrInfo.td
M llvm/lib/Target/ARM/ARMInstructionSelector.cpp
M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/DirectX/DXIL.td
M llvm/lib/Target/DirectX/DXILMetadata.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
M llvm/lib/Target/Hexagon/HexagonRDFOpt.cpp
M llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsAsmPrinter.cpp
M llvm/lib/Target/Mips/MipsAsmPrinter.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.h
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/NVPTX/NVVMReflect.cpp
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFoldMasks.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
A llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td
M llvm/lib/Target/RISCV/RISCVInstrInfoV.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZc.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp
M llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
M llvm/lib/Target/RISCV/RISCVScheduleV.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86CallingConv.td
M llvm/lib/Target/X86/X86FastISel.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86RegisterInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/TextAPI/BinaryReader/DylibReader.cpp
M llvm/lib/TextAPI/Utils.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/Coroutines/CoroSplit.cpp
M llvm/lib/Transforms/IPO/GlobalOpt.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/IPO/MergeFunctions.cpp
M llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Scalar/CMakeLists.txt
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
R llvm/lib/Transforms/Scalar/LoopRerollPass.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp
M llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp
M llvm/lib/Transforms/Utils/CallPromotionUtils.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/Debugify.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/LoopRotationUtils.cpp
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/AliasSet/memloc-vscale.ll
M llvm/test/Analysis/BasicAA/assume-index-positive.ll
M llvm/test/Analysis/BasicAA/index-size.ll
M llvm/test/Analysis/BasicAA/noalias-bugs.ll
M llvm/test/Analysis/BasicAA/vscale.ll
M llvm/test/Analysis/BlockFrequencyInfo/basic.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_pgo.ll
M llvm/test/Analysis/BlockFrequencyInfo/loop_with_invoke.ll
M llvm/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll
M llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
A llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/free-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll
M llvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll
M llvm/test/Analysis/CostModel/free-intrinsics-no_info.ll
M llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
M llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
M llvm/test/Analysis/Dominators/invoke.ll
M llvm/test/Analysis/FunctionPropertiesAnalysis/matmul.ll
M llvm/test/Analysis/IVUsers/deep_recursion_in_scev.ll
M llvm/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll
M llvm/test/Analysis/LazyValueAnalysis/invalidation.ll
M llvm/test/Analysis/LoopAccessAnalysis/forked-pointers.ll
M llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/LoopnestFixedSize.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/loads-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matvecmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/single-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
M llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-complex.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-simple.ll
M llvm/test/Analysis/LoopNestAnalysis/duplicate-successors.ll
M llvm/test/Analysis/LoopNestAnalysis/imperfectnest.ll
M llvm/test/Analysis/LoopNestAnalysis/infinite.ll
M llvm/test/Analysis/LoopNestAnalysis/perfectnest.ll
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/atomics.ll
M llvm/test/Assembler/DIDefaultTemplateParam.ll
M llvm/test/Assembler/incomplete-ir-declarations.ll
M llvm/test/Bitcode/compatibility.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
A llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global-pic.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-xclass-copies.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
M llvm/test/CodeGen/AArch64/PBQP-csr.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
M llvm/test/CodeGen/AArch64/add-i256.ll
M llvm/test/CodeGen/AArch64/addrsig-macho.ll
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/AArch64/arm64-ccmp.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-fminv.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-bad-outline.mir
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
M llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll
M llvm/test/CodeGen/AArch64/arm64-ldp.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-neon-copy.ll
M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
M llvm/test/CodeGen/AArch64/arm64-vaddv.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
M llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
M llvm/test/CodeGen/AArch64/branch-target-enforcement-indirect-calls.ll
A llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/AArch64/compute-call-frame-size-unreachable-pass.ll
A llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
M llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
M llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/divrem.ll
M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/fmov-imm-licm.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
M llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/irg-nomem.mir
M llvm/test/CodeGen/AArch64/kcfi-bti.ll
M llvm/test/CodeGen/AArch64/ldradr.ll
M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
M llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
M llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
M llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
M llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
M llvm/test/CodeGen/AArch64/merge-store.ll
M llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
M llvm/test/CodeGen/AArch64/neon-mov.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
M llvm/test/CodeGen/AArch64/sadd_sat.ll
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M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
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M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll
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M llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
M llvm/test/CodeGen/ARM/debug-info-blocks.ll
M llvm/test/CodeGen/ARM/debug-info-d16-reg.ll
M llvm/test/CodeGen/ARM/debug-info-s16-reg.ll
M llvm/test/CodeGen/ARM/dwarf-eh.ll
M llvm/test/CodeGen/ARM/fp16-args.ll
M llvm/test/CodeGen/ARM/fp16-instructions.ll
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/ARM/ldrcppic.ll
M llvm/test/CodeGen/ARM/llvm.exp10.ll
M llvm/test/CodeGen/ARM/llvm.frexp.ll
M llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
M llvm/test/CodeGen/ARM/misched-copy-arm.ll
M llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/ARM/readonly-aliases.ll
M llvm/test/CodeGen/ARM/shift-combine.ll
M llvm/test/CodeGen/ARM/tail-dup-kill-flags.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
M llvm/test/CodeGen/AVR/ctors.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/elpm.ll
M llvm/test/CodeGen/AVR/features/avr-tiny.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
M llvm/test/CodeGen/AVR/inline-asm/loadstore.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lpmx.ll
M llvm/test/CodeGen/AVR/pr43443-ctor-alias.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-trait-object.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/struct.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
M llvm/test/CodeGen/BPF/BTF/builtin-btf-type-id.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-2.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-struct-3.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-union-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-union-2.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/reloc.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll
M llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll
M llvm/test/CodeGen/CSKY/atomic-load-store.ll
M llvm/test/CodeGen/CSKY/atomic-rmw.ll
M llvm/test/CodeGen/CSKY/call-16bit.ll
M llvm/test/CodeGen/CSKY/call.ll
M llvm/test/CodeGen/CSKY/constantpool.ll
M llvm/test/CodeGen/CSKY/dwarf-eh.ll
M llvm/test/CodeGen/CSKY/fpu/ldst-d.ll
M llvm/test/CodeGen/CSKY/fpu/ldst-f.ll
M llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll
M llvm/test/CodeGen/CSKY/indirectbr.ll
M llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll
M llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll
M llvm/test/CodeGen/CSKY/inline-asm.ll
M llvm/test/CodeGen/CSKY/ldst-i.ll
M llvm/test/CodeGen/CSKY/tls-models.ll
M llvm/test/CodeGen/Generic/DbgValueAggregate.ll
M llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables-x.mir
M llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
M llvm/test/CodeGen/Hexagon/autohvx/fsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfsplat.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
M llvm/test/CodeGen/Hexagon/swp-new-phi.ll
M llvm/test/CodeGen/Hexagon/v5_insns.ll
M llvm/test/CodeGen/Hexagon/v60Vasr.ll
M llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
M llvm/test/CodeGen/Hexagon/vect-regpairs.ll
M llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll
M llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
M llvm/test/CodeGen/Lanai/codemodel.ll
M llvm/test/CodeGen/Lanai/inlineasm-output-template.ll
M llvm/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
M llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
M llvm/test/CodeGen/Lanai/peephole-compare.mir
M llvm/test/CodeGen/Lanai/set_and_hi.ll
M llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
M llvm/test/CodeGen/Lanai/subword.ll
M llvm/test/CodeGen/LoongArch/frame.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
A llvm/test/CodeGen/LoongArch/register-coalescer-crash-pr79718.mir
M llvm/test/CodeGen/LoongArch/tail-calls.ll
M llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll
M llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/add.ll
M llvm/test/CodeGen/M68k/Arith/bitwise.ll
M llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll
M llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll
M llvm/test/CodeGen/M68k/Atomics/load-store.ll
M llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll
M llvm/test/CodeGen/M68k/CConv/c-args.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-args.ll
M llvm/test/CodeGen/M68k/CConv/fastcc-call.ll
M llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll
M llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll
M llvm/test/CodeGen/M68k/CodeModel/medium-static.ll
M llvm/test/CodeGen/M68k/CodeModel/small-pic.ll
M llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll
M llvm/test/CodeGen/M68k/CodeModel/small-static.ll
M llvm/test/CodeGen/M68k/Control/cmp.ll
M llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll
M llvm/test/CodeGen/M68k/inline-asm.ll
M llvm/test/CodeGen/M68k/link-unlnk.ll
M llvm/test/CodeGen/M68k/reserved-regs.ll
M llvm/test/CodeGen/M68k/varargs.ll
M llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/AArch64/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AArch64/machine-metadata.mir
M llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
M llvm/test/CodeGen/MIR/AArch64/swp.mir
M llvm/test/CodeGen/MIR/AArch64/target-flags.mir
M llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-after-pei.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
M llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir
M llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/MIR/Generic/frame-info.mir
M llvm/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir
M llvm/test/CodeGen/MIR/Mips/memory-operands.mir
M llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
M llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
M llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
M llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
M llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
M llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
M llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
M llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
M llvm/test/CodeGen/MIR/X86/global-value-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
M llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
M llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
M llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
M llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
M llvm/test/CodeGen/MIR/X86/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/X86/machine-metadata.mir
M llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
M llvm/test/CodeGen/MIR/X86/metadata-operands.mir
M llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
M llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/null-register-operands.mir
M llvm/test/CodeGen/MIR/X86/pr38773.mir
M llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
M llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
M llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/stack-objects.mir
M llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
M llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unreachable-block-print.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
M llvm/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Rot.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Shift.ll
M llvm/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
M llvm/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
M llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
M llvm/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
M llvm/test/CodeGen/MSP430/2009-12-21-FrameAddr.ll
M llvm/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
M llvm/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
M llvm/test/CodeGen/MSP430/BranchSelector.ll
M llvm/test/CodeGen/MSP430/Inst16mi.ll
M llvm/test/CodeGen/MSP430/Inst16mm.ll
M llvm/test/CodeGen/MSP430/Inst16mr.ll
M llvm/test/CodeGen/MSP430/Inst16rm.ll
M llvm/test/CodeGen/MSP430/Inst8mi.ll
M llvm/test/CodeGen/MSP430/Inst8mm.ll
M llvm/test/CodeGen/MSP430/Inst8mr.ll
M llvm/test/CodeGen/MSP430/Inst8rm.ll
M llvm/test/CodeGen/MSP430/InstII.ll
M llvm/test/CodeGen/MSP430/bit.ll
M llvm/test/CodeGen/MSP430/byval.ll
M llvm/test/CodeGen/MSP430/callee-saved.ll
M llvm/test/CodeGen/MSP430/calls.ll
M llvm/test/CodeGen/MSP430/cc_args.ll
M llvm/test/CodeGen/MSP430/cc_ret.ll
M llvm/test/CodeGen/MSP430/fp.ll
M llvm/test/CodeGen/MSP430/hwmult16.ll
M llvm/test/CodeGen/MSP430/hwmult32.ll
M llvm/test/CodeGen/MSP430/hwmultf5.ll
M llvm/test/CodeGen/MSP430/indirectbr.ll
M llvm/test/CodeGen/MSP430/indirectbr2.ll
M llvm/test/CodeGen/MSP430/inline-asm-absolute-addressing.ll
M llvm/test/CodeGen/MSP430/inline-asm.ll
M llvm/test/CodeGen/MSP430/inlineasm-output-template.ll
M llvm/test/CodeGen/MSP430/interrupt.ll
M llvm/test/CodeGen/MSP430/jumptable.ll
M llvm/test/CodeGen/MSP430/libcalls.ll
M llvm/test/CodeGen/MSP430/memset.ll
M llvm/test/CodeGen/MSP430/misched-msp430.ll
M llvm/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
M llvm/test/CodeGen/MSP430/postinc.ll
M llvm/test/CodeGen/MSP430/promote-i8-mul.ll
M llvm/test/CodeGen/MSP430/spill-to-stack.ll
M llvm/test/CodeGen/MSP430/stacksave_restore.ll
M llvm/test/CodeGen/MSP430/struct-return.ll
M llvm/test/CodeGen/MSP430/struct_layout.ll
M llvm/test/CodeGen/MSP430/transient-stack-alignment.ll
M llvm/test/CodeGen/MSP430/vararg.ll
M llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
M llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
M llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll
M llvm/test/CodeGen/Mips/jump-table-mul.ll
M llvm/test/CodeGen/Mips/mips16_fpret.ll
M llvm/test/CodeGen/Mips/msa/emergency-spill.mir
M llvm/test/CodeGen/Mips/mulull.ll
M llvm/test/CodeGen/Mips/pseudo-jump-fill.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/alias.ll
Log Message:
-----------
[𝘀𝗽𝗿] landed version
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/3e4d516a991f...345efe0df644
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