[all-commits] [llvm/llvm-project] abc39f: [RISCV] Add casts to isel patterns that produce mo...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: abc39f9aa750634973fe8ba5519d6bbdd70567c4
      https://github.com/llvm/llvm-project/commit/abc39f9aa750634973fe8ba5519d6bbdd70567c4
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-08 (Thu, 08 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoD.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoF.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoM.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
    M llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

  Log Message:
  -----------
  [RISCV] Add casts to isel patterns that produce more than 1 instruction.

We need explicitly cast to XLenVT to avoid tablegen picking i32.

If the SelectionDAG scheduler is used it can't find a register
class for i32 if i32 isn't a legal type.

Fixes #81192, but I might have missed some patterns.