[all-commits] [llvm/llvm-project] b8545e: [RISCV] Consider all subvector extracts within a s...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: b8545e1ece271df16185d446503474c105d6398a
      https://github.com/llvm/llvm-project/commit/b8545e1ece271df16185d446503474c105d6398a
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-02-08 (Thu, 08 Feb 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

  Log Message:
  -----------
  [RISCV] Consider all subvector extracts within a single VREG cheap (#81032)

This adjusts the isSubVectorExtractCheap callback to consider any
extract which fits entirely within the first VLEN bits of the src vector
(and uses a 5 bit immediate for the slide) as cheap. These can be done
via a single m1 vslide1down.vi instruction.

This allows our generic DAG combine logic to kick in and recognize a few
more cases where shuffle source is longer than the dest, but that using
a wider shuffle is still profitable. (Or as shown in the test diff, we
can split the wider source and do two narrower shuffles.)