[all-commits] [llvm/llvm-project] b84661: [X86] X86FixupVectorConstants - add destination re...
Simon Pilgrim via All-commits
all-commits at lists.llvm.org
Thu Feb 8 08:35:35 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: b846613837d83989d99d33f4b90db7bad019aa8c
https://github.com/llvm/llvm-project/commit/b846613837d83989d99d33f4b90db7bad019aa8c
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants - add destination register width to rebuildSplatCst/rebuildZeroUpperCst/rebuildExtCst callbacks
As found on #81136 - we aren't correctly handling for cases where the constant pool entry is wider than the destination register width, causing incorrect scaling of the truncated constant for load-extension cases.
This first patch just pulls out the destination register width argument, its still currently driven by the constant pool entry but that will be addressed in a followup.
Commit: eb85c8edf576d27254fa37bf9ed72ec0867756f7
https://github.com/llvm/llvm-project/commit/eb85c8edf576d27254fa37bf9ed72ec0867756f7
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
A llvm/test/CodeGen/X86/pr81136.ll
Log Message:
-----------
[X86] Add test case for #81136
Commit: f407be32fe8084fe02c4f16842548d21afdb447f
https://github.com/llvm/llvm-project/commit/f407be32fe8084fe02c4f16842548d21afdb447f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-08 (Thu, 08 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants - rename FixupEntry::BitWidth to FixupEntry::MemBitWidth NFC.
Make it clearer that this refers to the width of the constant element stored in memory - which won't match the register element width after a sext/zextload
Compare: https://github.com/llvm/llvm-project/compare/7d19dc50de2c...f407be32fe80
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