[all-commits] [llvm/llvm-project] 7c0d52: [ValueTracking] Support dominating known bits cond...

[Nikita Popov via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 7c0d52ca91d32e693ca245fb82f2402a34212fc3
      https://github.com/llvm/llvm-project/commit/7c0d52ca91d32e693ca245fb82f2402a34212fc3
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2024-02-08 (Thu, 08 Feb 2024)

  Changed paths:
    M llvm/lib/Analysis/DomConditionCache.cpp
    M llvm/lib/Analysis/ValueTracking.cpp
    M llvm/test/Transforms/InstCombine/known-bits.ll
    M llvm/test/Transforms/LoopVectorize/induction.ll

  Log Message:
  -----------
  [ValueTracking] Support dominating known bits condition in and/or (#74728)

This extends computeKnownBits() support for dominating conditions to
also handle and/or conditions. We'll look through either and or or
depending on which edge we're considering.

This change is mainly for the sake of completeness, so we don't start
missing optimizations if SimplifyCFG decides to merge some branches.