[all-commits] [llvm/llvm-project] 3d186a: [Clang][AArch64] Fix some target guards and remove...

[Sander de Smalen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 3d186a77cf1aa979014a6443cb423a633c167d9f
      https://github.com/llvm/llvm-project/commit/3d186a77cf1aa979014a6443cb423a633c167d9f
  Author: Sander de Smalen <sander.desmalen at arm.com>
  Date:   2024-02-06 (Tue, 06 Feb 2024)

  Changed paths:
    M clang/include/clang/Basic/arm_sme.td
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c
    M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c
    M clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c

  Log Message:
  -----------
  [Clang][AArch64] Fix some target guards and remove +sve from tests. (#80681)

The TargetGuard fields for 'svldr[_vnum]_za' and 'svstr[_vnum]_za' were
incorrectly set to `+sve` instead of `+sme`. This means that compiling
code that uses these intrinsics requires compiling for both `+sve` as
well as `+sme`.

This PR also fixes the target guards for the `svadd` and `svsub`
builtins that are enabled under `+sme2,+sme-i16i64` and
`+sme2,+sme-f64f64`, as it initially did the following:
```
  let TargetGuard = "+sme2" in {
    let TargetGuard = "+sme-i16i64" in {
      // Builtins defined here will be predicated only by
      // '+sme-i16i64', and not '+sme2,+sme-i16i64'.
    }
  }
```
This PR also removes `-target-feature +sve` from all the SME tests, to
ensure that the SME features are sufficient to build the tests.