[all-commits] [llvm/llvm-project] e296ce: [RISCV][MC] MC layer support for the experimental ...
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Mon Feb 5 13:46:39 PST 2024
Branch: refs/heads/users/alexey-bataev/spr/slpimprove-findreusedorderedscalars-and-graph-rotation
Home: https://github.com/llvm/llvm-project
Commit: e296cedcd686e24fee75756185669f1bb3b47fdd
https://github.com/llvm/llvm-project/commit/e296cedcd686e24fee75756185669f1bb3b47fdd
Author: Brendan Sweeney <brs at eecs.berkeley.edu>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/RISCV/rv32zalasr-invalid.s
A llvm/test/MC/RISCV/rv32zalasr-valid.s
A llvm/test/MC/RISCV/rv64zalasr-invalid.s
A llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
This PR implements experimental support for the RISC-V Atomic
Load-Acquire and Store-Release Extension (Zalasr). It has been approved
to be pursued as a fast track extension
(https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698),
but has not yet been approved by ARC or ratified. See
https://github.com/mehnadnerd/riscv-zalasr for draft spec.
---------
Co-authored-by: brs <turtwig at utexas.edu>
Co-authored-by: Philip Reames <preames at rivosinc.com>
Commit: 20a9fa3e145999d7cb0d311c832ee6c72fc276fb
https://github.com/llvm/llvm-project/commit/20a9fa3e145999d7cb0d311c832ee6c72fc276fb
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
Log Message:
-----------
[mlir][sparse] add sparsification options to pretty print and debug s… (#80205)
…parse loops.
Commit: 41be5412e2da0235811af24b10eb2dacab03f8b5
https://github.com/llvm/llvm-project/commit/41be5412e2da0235811af24b10eb2dacab03f8b5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/MC/RISCV/supervisor-csr-names.s
Log Message:
-----------
[RISCV] Add srmcfg CSR from Ssqosid extension. (#79914)
Based on the spec here
https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1
Ssqosid extension name will be added in a separate patch.
Commit: 10c2d5ff7c6de8096c8f4c4621612970940f6dd3
https://github.com/llvm/llvm-project/commit/10c2d5ff7c6de8096c8f4c4621612970940f6dd3
Author: Jiahan Xie <88367305+jiahanxie353 at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
Log Message:
-----------
[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)
RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.
Commit: f883365cc7600cf1c29b36343f2f8cdbe3394881
https://github.com/llvm/llvm-project/commit/f883365cc7600cf1c29b36343f2f8cdbe3394881
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/include/stdbit_test.cpp
Log Message:
-----------
[libc] fix stdbit include test when not all entrypoints are available (#80323)
The intent of the test is to check that: 1. The type generic macros are
defined. 2. Those macros dispatch to the correct underlying function.
The issue is that when new functionality is added to our stdbit.h without
rolling out the new entrypoint to all targets, this test breaks because our
generated stdbit.h will not contain declarations for the underlying function.
In that case, we should just declare the underlying functions first before
including our generated stdbit.h which just contains declarations. A definition
is a declaration, but redeclarations must match, hence the additions of
noexcept and extern "C".
Commit: 116e801a15569386c452085de783ecb9223050ff
https://github.com/llvm/llvm-project/commit/116e801a15569386c452085de783ecb9223050ff
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/phdr-out-of-order.test
Log Message:
-----------
[BOLT] Adjust section sizes based on file offsets (#80226)
When we adjust section sizes while rewriting a binary, we should be
using section offsets and not addresses to determine if section overlap.
NFC for existing binaries.
Commit: a693ae5306d224228acbbc1366dc90432afce434
https://github.com/llvm/llvm-project/commit/a693ae5306d224228acbbc1366dc90432afce434
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/linux-orc.s
Log Message:
-----------
[BOLT] Enable re-writing of Linux kernel binary (#80228)
Write modified Linux kernel binary to disk. The output is not supposed
to be functional at the moment, but it will allow for future patches to
test the output binary.
Commit: a063df20abeee3513d3577dc41bff7e54159efa5
https://github.com/llvm/llvm-project/commit/a063df20abeee3513d3577dc41bff7e54159efa5
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/CMakeLists.txt
Log Message:
-----------
[OpenMP] Fix typo (NFC) (#80332)
Commit: 6f32d6a4f362ad1c7f6328232a68f44a44fc2d2e
https://github.com/llvm/llvm-project/commit/6f32d6a4f362ad1c7f6328232a68f44a44fc2d2e
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/prefer-member-initializer.rst
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init.cpp
Log Message:
-----------
[clang-tidy] Remove enforcement of rule C.48 from cppcoreguidelines-prefer-member-init (#80330)
This functionality already exists in
cppcoreguidelines-use-default-member-init. It was deprecated from this
check in clang-tidy 17.
This allows us to fully decouple this check from the corresponding
modernize check, which has an unhealthy dependency.
Fixes https://github.com/llvm/llvm-project/issues/62169
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: 7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
https://github.com/llvm/llvm-project/commit/7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc] add bazel support for most of unistd (#80078)
Much of unistd involves modifying files. The tests for these functions
need to use libc_make_test_file_path which didn't exist when they were
first implemented. This patch adds most of unistd to the bazel along
with the corresponding tests. Tests that modify directories had to be
disabled since bazel doesn't seem to handle them properly.
Commit: aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
https://github.com/llvm/llvm-project/commit/aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
Author: Micah Weston <micahsweston at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP][llvm-readobj] Implements llvm-readobj handling for PGOAnalysisMap. (#79520)
Adds raw printing of PGOAnalysisMap in llvm-readobj.
I'm leaving the fixme's for a later patch that will provide a 'pretty'
printing for BBFreq and BrProb (i.e. relative frequencies and
probabilities) that will apply to both llvm-readobj and llvm-objdump.
Commit: 08fccf80949c649e2c4c81bf9149fd77206002c4
https://github.com/llvm/llvm-project/commit/08fccf80949c649e2c4c81bf9149fd77206002c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
Log Message:
-----------
[AArch64][PAC] Expand blend(reg, imm) operation in aarch64-pauth pass (#74729)
In preparation for implementing code generation for more @llvm.ptrauth.* intrinsics, move the expansion of blend(register, small integer) variant of @llvm.ptrauth.blend to the AArch64PointerAuth pass, where most other PAuth-related code generation takes place.
Commit: fe408eb5845737f8d6bf5eeed0aca8651991e687
https://github.com/llvm/llvm-project/commit/fe408eb5845737f8d6bf5eeed0aca8651991e687
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
Log Message:
-----------
[flang][openacc][openmp] Use #0 from hlfir.declare value when generating bound ops (#80317)
`getDataOperandBaseAddr` retrieve the address of a value when we need to
generate bound operations. When switching to HLFIR, we did not really
handle the fact that this value was then pointing to the result of a
hlfir.declare. Because of that the `#1` value was being used. `#0` value
is carrying the correct information about lowerbounds and should be
used. This patch updates the `getDataOperandBaseAddr` function to use
the correct result value from hlfir.declare.
Commit: 243bfed68367263cfc3fb3f396660acf60051fbf
https://github.com/llvm/llvm-project/commit/243bfed68367263cfc3fb3f396660acf60051fbf
Author: Artem Dergachev <adergachev at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
A clang/test/Analysis/html_diagnostics/counter.c
Log Message:
-----------
[analyzer][HTMLRewriter] Cache partial rewrite results. (#80220)
This is a follow-up for 721dd3bc2 [analyzer] NFC: Don't regenerate
duplicate HTML reports.
Because HTMLRewriter re-runs the Lexer for syntax highlighting and macro
expansion purposes, it may get fairly expensive when the rewriter is
invoked multiple times on the same file. In the static analyzer (which
uses HTMLRewriter for HTML output mode) we only get away with this
because there are usually very few reports emitted per file. But if loud
checkers are enabled, such as `webkit.*`, this may explode in complexity
and even cause the compiler to run over the 32-bit SourceLocation
addressing limit.
This patch caches intermediate results so that re-lexing only needed to
happen once.
As the clever __COUNTER__ test demonstrates, "once" is still too many.
Ideally we shouldn't re-lex anything at all, which remains a TODO.
Commit: 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
https://github.com/llvm/llvm-project/commit/8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
Author: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI]Add support for strided loads/stores.
Added basic legality check and cost estimation functions for strided loads and stores.
These interfaces will be built upon in https://github.com/llvm/llvm-project/pull/80310.
Reviewers: preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/80329
Commit: 59e559067b1e47b72f3c631483c1f71919d5358e
https://github.com/llvm/llvm-project/commit/59e559067b1e47b72f3c631483c1f71919d5358e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
Log Message:
-----------
Revert "[RISCV] Refine cost on Min/Max reduction" (#80340)
Reverts llvm/llvm-project#79402. Crash reported. On closer inspection,
this patch does not handle Intrinsic::maximum and Intrinsic::minimum.
Commit: edbd93d3706b806e7c91dfd2c359476488dfcc96
https://github.com/llvm/llvm-project/commit/edbd93d3706b806e7c91dfd2c359476488dfcc96
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/stdc_leading_ones_uc.cpp
M libc/src/stdbit/stdc_leading_ones_uc.h
M libc/src/stdbit/stdc_leading_ones_ul.cpp
M libc/src/stdbit/stdc_leading_ones_ul.h
M libc/src/stdbit/stdc_leading_ones_ull.cpp
M libc/src/stdbit/stdc_leading_ones_ull.h
M libc/src/stdbit/stdc_leading_ones_us.cpp
M libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
Log Message:
-----------
[libc][stdbit] fix return types (#80337)
All of the functions I've previously implemented return an unsigned int; not
the parameter type.
Commit: 5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
https://github.com/llvm/llvm-project/commit/5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/StackSlotColoring.cpp
A llvm/test/CodeGen/RISCV/pr80052.mir
M llvm/test/CodeGen/X86/pr30821.mir
Log Message:
-----------
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
The stack slot coloring pass is concerned with optimizing spill
slots. If any change is a pass is made over the function to remove
stack stores that use the same register and stack slot as an
immediately preceding load.
The register check is too simple for constant registers like AArch64
and RISC-V's zero register. This register can be used as the result
of a load if we want to discard the result, but still have the memory
access performed. Like for a volatile or atomic load.
If the code sees a load from the zero register followed by a store
of the zero register at the same stack slot, the pass mistakenly
believes the store isn't needed.
Since the main stack coloring optimization is only concerned with
spill slots, it seems reasonable that RemoveDeadStores should
only be concerned with spills. Since we never generate a reload of
x0, this avoids the issue seen by RISC-V.
Test case concept is adapted from pr30821.mir from X86. That test
had to be updated to mark the stack slot as a spill slot.
Fixes #80052.
Commit: 33b463ad9976fa7a27c1a22419297fcccd79f99f
https://github.com/llvm/llvm-project/commit/33b463ad9976fa7a27c1a22419297fcccd79f99f
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
A mlir/test/Dialect/SparseTensor/external.mlir
Log Message:
-----------
[mlir][sparse] external entry method wrapper for sparse tensors (#80326)
Similar to the emit_c_interface, this pull request adds a pass that
converts public entry methods that use sparse tensors as input
parameters and/or output return values into wrapper functions that
[dis]assemble the individual tensors that constitute the actual storage
used externally into MLIR sparse tensors. This pass can be used to
prepare the public entry methods of a program that is compiled by the
MLIR sparsifier to interface with an external runtime, e.g., when
passing sparse tensors as numpy arrays from and to Python. Note that
eventual bufferization decisions (e.g. who [de]allocates the underlying
memory) should be resolved in agreement with the external runtime
(Python, PyTorch, JAX, etc.)
Commit: 5d228eaf0f5d9c873ba12fc439609148f3f88733
https://github.com/llvm/llvm-project/commit/5d228eaf0f5d9c873ba12fc439609148f3f88733
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add beginner-focused office hours (#80308)
These are initially being hosted by a rotating cast of: @danakj
@gburgessiv @nickdesaulniers @sudonatalie
Commit: 9258f3e692493a69e0f4755bb129a5391ef10b50
https://github.com/llvm/llvm-project/commit/9258f3e692493a69e0f4755bb129a5391ef10b50
Author: Greg Clayton <gclayton at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
Log Message:
-----------
[lldb] Fix a crash when using .dwp files and make type lookup reliable with the index cache (#79544)
When using split DWARF with .dwp files we had an issue where sometimes
the DWO file within the .dwp file would be parsed _before_ the skeleton
compile unit. The DWO file expects to be able to always be able to get a
link back to the skeleton compile unit. Prior to this fix, the only time
the skeleton compile unit backlink would get set, was if the unit
headers for the main executable have been parsed _and_ if the unit DIE
was parsed in that DWARFUnit. This patch ensures that we can always get
the skeleton compile unit for a DWO file by adding a function:
```
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
```
Prior to this fix DWARFUnit had some unsafe accessors that were used to
store two different things:
```
void *DWARFUnit::GetUserData() const;
void DWARFUnit::SetUserData(void *d);
```
This was used by SymbolFileDWARF to cache the `lldb_private::CompileUnit
*` for a SymbolFileDWARF and was also used to store the `DWARFUnit *`
for SymbolFileDWARFDwo. This patch clears up this unsafe usage by adding
two separate accessors and ivars for this:
```
lldb_private::CompileUnit *DWARFUnit::GetLLDBCompUnit() const { return m_lldb_cu; }
void DWARFUnit::SetLLDBCompUnit(lldb_private::CompileUnit *cu) { m_lldb_cu = cu; }
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
void DWARFUnit::SetSkeletonUnit(DWARFUnit *skeleton_unit);
```
This will stop anyone from calling `void *DWARFUnit::GetUserData()
const;` and casting the value to an incorrect value.
A crash could occur in `SymbolFileDWARF::GetCompUnitForDWARFCompUnit()`
when the `non_dwo_cu`, which is a backlink to the skeleton compile unit,
was not set and was NULL. There is an assert() in the code, and then the
code just will kill the program if the assert isn't enabled because the
code looked like:
```
if (dwarf_cu.IsDWOUnit()) {
DWARFCompileUnit *non_dwo_cu =
static_cast<DWARFCompileUnit *>(dwarf_cu.GetUserData());
assert(non_dwo_cu);
return non_dwo_cu->GetSymbolFileDWARF().GetCompUnitForDWARFCompUnit(
*non_dwo_cu);
}
```
This is now fixed by calling the `DWARFUnit::GetSkeletonUnit()` which
will correctly always get the skeleton compile uint for a DWO file
regardless of if the skeleton unit headers have been parse or if the
skeleton unit DIE wasn't parsed yet.
To implement the ability to get the skeleton compile units, I added code
the DWARFDebugInfo.cpp/.h that make a map of DWO ID -> skeleton
DWARFUnit * that gets filled in for DWARF5 when the unit headers are
parsed. The `DWARFUnit::GetSkeletonUnit()` will end up parsing the unit
headers of the main executable to fill in this map if it already hasn't
been done. For DWARF4 and earlier we maintain a separate map that gets
filled in only for any DWARF4 compile units that have a DW_AT_dwo_id or
DW_AT_gnu_dwo_id attributes. This is more expensive, so this is done
lazily and in a thread safe manor. This allows us to be as efficient as
possible when using DWARF5 and also be backward compatible with DWARF4 +
split DWARF.
There was also an issue that stopped type lookups from succeeding in
`DWARFDIE SymbolFileDWARF::GetDIE(const DIERef &die_ref)` where it
directly was accessing the `m_dwp_symfile` ivar without calling the
accessor function that could end up needing to locate and load the .dwp
file. This was fixed by calling the
`SymbolFileDWARF::GetDwpSymbolFile()` accessor to ensure we always get a
valid value back if we can find the .dwp file. Prior to this fix it was
down which APIs were called and if any APIs were called that loaded the
.dwp file, it worked fine, but it might not if no APIs were called that
did cause it to get loaded.
When we have valid debug info indexes and when the lldb index cache was
enabled, this would cause this issue to show up more often.
I modified an existing test case to test that all of this works
correctly and doesn't crash.
Commit: 1bc7be6bce861acfe477f0c9abd349c1dc6ea160
https://github.com/llvm/llvm-project/commit/1bc7be6bce861acfe477f0c9abd349c1dc6ea160
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost model coverage for vp.strided.load and vp.strided.store
Commit: 391393179a6e316909add3b8455eb6d7c7c38ddb
https://github.com/llvm/llvm-project/commit/391393179a6e316909add3b8455eb6d7c7c38ddb
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
Log Message:
-----------
[lld-macho] icf objc stubs (#79730)
This supports icf for objc stubs.
Commit: ecdbffe59e80666c9cadf3f80bd20bb34828fb47
https://github.com/llvm/llvm-project/commit/ecdbffe59e80666c9cadf3f80bd20bb34828fb47
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/src/sys/epoll/linux/epoll_wait.cpp
Log Message:
-----------
[libc] Support epoll_wait using epoll_pwait (#80224)
The epoll_wait syscall is equivalent to calling epoll_pwait with a null
sigset. This is useful to support systems that have epoll_pwait but not
epoll_wait.
Commit: bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
https://github.com/llvm/llvm-project/commit/bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
Author: Hana Dusíková <hanicka at hanicka.net>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/test/CoverageMapping/if.cpp
Log Message:
-----------
[coverage] fix crash in code coverage and `if constexpr` with `ExprWithCleanups` (#80292)
Fixes https://github.com/llvm/llvm-project/issues/80285
Commit: 375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
https://github.com/llvm/llvm-project/commit/375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add aligned/unaligned tests for vp.strided.load and vp.strided.store
Commit: 07bf1ddb4eb0abfff20542fd4459bace1f72107f
https://github.com/llvm/llvm-project/commit/07bf1ddb4eb0abfff20542fd4459bace1f72107f
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
Log Message:
-----------
[mlir][sparse] support non-id map for [Dis]assembleOp (#80355)
Commit: 4eac14683855e040adaf507ed6b14e28a09f983e
https://github.com/llvm/llvm-project/commit/4eac14683855e040adaf507ed6b14e28a09f983e
Author: Greg Clayton <clayborg at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
Log Message:
-----------
Fix buildbots after #79544
https://github.com/llvm/llvm-project/pull/79544
Commit: 4a653b4df5d84c4d2df8f6d4040ef46413ac3816
https://github.com/llvm/llvm-project/commit/4a653b4df5d84c4d2df8f6d4040ef46413ac3816
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
Log Message:
-----------
[mlir][sparse] Support pretty print to debug sparse iteration. (#80207)
Commit: 8fd0bce43c4c8334bcb31d214a32260914f59515
https://github.com/llvm/llvm-project/commit/8fd0bce43c4c8334bcb31d214a32260914f59515
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
Log Message:
-----------
[mlir][spirv][memref] Calculate alignment for `PhysicalStorageBuffer`s (#80243)
The SPIR-V spec requires that memory accesses to
`PhysicalStorageBuffer`s are annotated with appropriate alignment
attributes [1]. Calculate these based on memref alignment attributes or
scalar type sizes.
[1] Otherwise spirv-val complains:
```
[VULKAN] ! Validation Error: [ VUID-VkShaderModuleCreateInfo-pCode-01379 ] | MessageID = 0x2a1bf17f | SPIR-V module not valid: [VUID-StandaloneSpirv-PhysicalStorageBuffer64-04708] Memory accesses with PhysicalStorageBuffer must use Aligned.
%48 = OpLoad %float %47
```
Commit: 4d89356fef1a568de790ad8b3f53dc494b461e5b
https://github.com/llvm/llvm-project/commit/4d89356fef1a568de790ad8b3f53dc494b461e5b
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
Log Message:
-----------
[libc][bazel] disable epoll_pwait2 (#80362)
Similar to #80051. The epoll_pwait2 syscall isn't available on all
target platforms, and this is causing downstream test failures. This
patch disables it until it can be detected whether or not it is
available.
Commit: ff3194037071e7f5fe859ad2173a5b67eed08b3b
https://github.com/llvm/llvm-project/commit/ff3194037071e7f5fe859ad2173a5b67eed08b3b
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port ecb5a1b0e236
Commit: 59eadcd28f787a98a2fd5f057beb3df7950654ee
https://github.com/llvm/llvm-project/commit/59eadcd28f787a98a2fd5f057beb3df7950654ee
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/test/python/dialects/memref.py
Log Message:
-----------
[mlir][py] Reduce size of allocation memrefs in test.
Commit: cc0d752f345f0e8995bec8807e3f365f38864fb6
https://github.com/llvm/llvm-project/commit/cc0d752f345f0e8995bec8807e3f365f38864fb6
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add git to actions container image (#80341)
Commit: 70eab122bceb94b15218c86db7045ff2448ea979
https://github.com/llvm/llvm-project/commit/70eab122bceb94b15218c86db7045ff2448ea979
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[AArch64][MachinePipeliner] Add pipeliner support for AArch64 (#79589)
Add AArch64 implementations for the interfaces of MachinePipeliner pass.
The pass is disabled by default for AArch64. It is enabled by specifying
--aarch64-enable-pipeliner.
5 tests in llvm-test-suites show performance improvement by more than 5%
on a Neoverse V1 processor.
| test | improvement |
| ---------------------------------------------------------------- |
-----------:|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl.test | 16%
|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-flt.test | 16%
|
| SingleSource/Benchmarks/Adobe-C++/loop_unroll.test | 14% |
| SingleSource/Benchmarks/Misc/flops-5.test | 13% |
| SingleSource/Benchmarks/BenchmarkGame/spectral-norm.test | 6% |
(base flags: -mcpu=neoverse-v1 -O3 -mrecip, flags for pipelining: -mllvm
-aarch64-enable-pipeliner -mllvm
-pipeliner-max-stages=100 -mllvm -pipeliner-max-mii=100 -mllvm
-pipeliner-enable-copytophi=0)
On the other hand, there are cases of significant performance
degradation. Algorithm improvements and adding the option/pragma will be
needed in the future.
Commit: acec6419e811a46050b0603dfa72fc6a169aa0f7
https://github.com/llvm/llvm-project/commit/acec6419e811a46050b0603dfa72fc6a169aa0f7
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/basic-block-address-map.c
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
A lld/test/ELF/lto/basic-block-address-map.ll
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
A llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
A llvm/test/CodeGen/X86/basic-block-address-map.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels.ll
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP] Allow basic-block-sections and labels be used together by decoupling the handling of the two features. (#74128)
Today `-split-machine-functions` and `-fbasic-block-sections={all,list}`
cannot be combined with `-basic-block-sections=labels` (the labels
option will be ignored).
The inconsistency comes from the way basic block address map -- the
underlying mechanism for basic block labels -- encodes basic block
addresses
(https://lists.llvm.org/pipermail/llvm-dev/2020-July/143512.html).
Specifically, basic block offsets are computed relative to the function
begin symbol. This relies on functions being contiguous which is not the
case for MFS and basic block section binaries. This means Propeller
cannot use binary profiles collected from these binaries, which limits
the applicability of Propeller for iterative optimization.
To make the `SHT_LLVM_BB_ADDR_MAP` feature work with basic block section
binaries, we propose modifying the encoding of this section as follows.
First let us review the current encoding which emits the address of each
function and its number of basic blocks, followed by basic block entries
for each basic block.
| | |
|--|--|
| Address of the function | Function Address |
| Number of basic blocks in this function | NumBlocks |
| BB entry 1
| BB entry 2
| ...
| BB entry #NumBlocks
To make this work for basic block sections, we treat each basic block
section similar to a function, except that basic block sections of the
same function must be encapsulated in the same structure so we can map
all of them to their single function.
We modify the encoding to first emit the number of basic block sections
(BB ranges) in the function. Then we emit the address map of each basic
block section section as before: the base address of the section, its
number of blocks, and BB entries for its basic block. The first section
in the BB address map is always the function entry section.
| | |
|--|--|
| Number of sections for this function | NumBBRanges |
| Section 1 begin address | BaseAddress[1] |
| Number of basic blocks in section 1 | NumBlocks[1] |
| BB entries for Section 1
|..................|
| Section #NumBBRanges begin address | BaseAddress[NumBBRanges] |
| Number of basic blocks in section #NumBBRanges |
NumBlocks[NumBBRanges] |
| BB entries for Section #NumBBRanges
The encoding of basic block entries remains as before with the minor
change that each basic block offset is now computed relative to the
begin symbol of its containing BB section.
This patch adds a new boolean codegen option `-basic-block-address-map`.
Correspondingly, the front-end flag `-fbasic-block-address-map` and LLD
flag `--lto-basic-block-address-map` are introduced.
Analogously, we add a new TargetOption field `BBAddrMap`. This means BB
address maps are either generated for all functions in the compiling
unit, or for none (depending on `TargetOptions::BBAddrMap`).
This patch keeps the functionality of the old
`-fbasic-block-sections=labels` option but does not remove it. A
subsequent patch will remove the obsolete option.
We refactor the `BasicBlockSections` pass by separating the BB address
map and BB sections handing to their own functions (named
`handleBBAddrMap` and `handleBBSections`). `handleBBSections` renumbers
basic blocks and places them in their assigned sections.
`handleBBAddrMap` is invoked after `handleBBSections` (if requested) and
only renumbers the blocks.
- New tests added:
- Two tests basic-block-address-map-with-basic-block-sections.ll and
basic-block-address-map-with-mfs.ll to exercise the combination of
`-basic-block-address-map` with `-basic-block-sections=list` and
'-split-machine-functions`.
- A driver sanity test for the `-fbasic-block-address-map` option
(basic-block-address-map.c).
- An LLD test for testing the `--lto-basic-block-address-map` option.
This reuses the LLVM IR from `lld/test/ELF/lto/basic-block-sections.ll`.
- Renamed and modified the two existing codegen tests for basic block
address map (`basic-block-sections-labels-functions-sections.ll` and
`basic-block-sections-labels.ll`)
- Removed `SHT_LLVM_BB_ADDR_MAP_V0` tests. Full deprecation of
`SHT_LLVM_BB_ADDR_MAP_V0` and `SHT_LLVM_BB_ADDR_MAP` version less than 2
will happen in a separate PR in a few months.
Commit: 3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
https://github.com/llvm/llvm-project/commit/3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
Log Message:
-----------
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)
Commit: 58c494f47cf56a30bf50024d22661c75003db809
https://github.com/llvm/llvm-project/commit/58c494f47cf56a30bf50024d22661c75003db809
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (#79399)
This is a good portion of the extensions mentioned in the RVA23 profile
here
https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc
I don't believe these add any new CSRs. Sstc does add new CSRs, but we
already added them without the extension name a while back.
I tried to keep the descriptions in RISCVFeatures.td fairly short since
the strings show up in `-print-supported-extensions`.
Commit: 082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
https://github.com/llvm/llvm-project/commit/082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Remove duplicate expression (#80380)
Reported by cpp check static analyzer in #80111.
Fixes #80111.
Commit: e270ec47cda26a8f0a3cdd195aa60992f109df8a
https://github.com/llvm/llvm-project/commit/e270ec47cda26a8f0a3cdd195aa60992f109df8a
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
Log Message:
-----------
[X86] X86InstrInfo.cpp - Remove dead code for memory folding, NFCI
`commuteInstruction(MI, false, OpNum, CommuteOpIdx2)` should never create
any new instruction, so we don't need to check and erase it.
Commit: 7dd790db8b77c4a833c06632e903dc4f13877a64
https://github.com/llvm/llvm-project/commit/7dd790db8b77c4a833c06632e903dc4f13877a64
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
[lldb] NFC fixes addressing David's feedback
David Spickett had several suggestions for
https://github.com/llvm/llvm-project/pull/79962 after I'd
already merged it. Address those.
Commit: dee8786f70a3d62b639113343fa36ef55bdbad63
https://github.com/llvm/llvm-project/commit/dee8786f70a3d62b639113343fa36ef55bdbad63
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/insert-before.test
Log Message:
-----------
[ELF] Fix compareSections assertion failure when OutputDescs in sectionCommands are non-contiguous
In a `--defsym y0=0 -T a.lds` link where a.lds contains only INSERT
commands, the `script->sectionCommands` layout may be:
```
orphan sections
SymbolAssignment due to --defsym
sections created by INSERT commands
```
The `OutputDesc` objects are not contiguous in sortInputSections, and
`compareSections` will be called with a SymbolAssignment argument,
leading to an assertion failure.
Commit: 374a600df7207fbe2002e754a799c7595a0e4833
https://github.com/llvm/llvm-project/commit/374a600df7207fbe2002e754a799c7595a0e4833
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[MachinePipeliner] Fix missing requirements for tests (#80386)
Add asserts requirements for tests that verify debug output.
Commit: 2147a2a4f3ef344a561677b55444ce4d028ec59f
https://github.com/llvm/llvm-project/commit/2147a2a4f3ef344a561677b55444ce4d028ec59f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/auto-type.c
Log Message:
-----------
[clang][Interp] Not all TypeTraitExprs are of bool type
In C, they return an integer, so emit their value as such.
Commit: 58ceefe09cd992c3692bb3af7c2807ac8949ba67
https://github.com/llvm/llvm-project/commit/58ceefe09cd992c3692bb3af7c2807ac8949ba67
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Support ChooseExprs
Commit: a2da7d06c7e1ec75812ff8ced29541d4af3668c9
https://github.com/llvm/llvm-project/commit/a2da7d06c7e1ec75812ff8ced29541d4af3668c9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Ignore LValueToRValue casts before doing the load
If the SubExpr results in an invalid pointer, we will otherwise
reject the constant expression.
Commit: 65ac8c16e028b23b49fd6b03817faa1ab6c0229d
https://github.com/llvm/llvm-project/commit/65ac8c16e028b23b49fd6b03817faa1ab6c0229d
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir] Skip invalid test on big endian platform (s390x) (#80246)
The buildbot test running on s390x platform keeps failing since [this
time](https://lab.llvm.org/buildbot/#/builders/199/builds/31136). This
is because of the dependency on the endianness of the platform. It
expects the format invalid in the big endian platform (s390x). We can
simply skip it.
See: https://discourse.llvm.org/t/mlir-s390x-linux-failure/76695
Commit: a8b5994b337cf1d461202a65204a4ee6c5eae341
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp][NFC] Add a broken test case
The LHS of the subtraction returns 16 right now, but should
return 0.
Commit: d9c20e437fe110fb79b5ca73a52762e5b930b361
https://github.com/llvm/llvm-project/commit/d9c20e437fe110fb79b5ca73a52762e5b930b361
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aarch64-inline-asm.c
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
Log Message:
-----------
[AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276)
This enables specifing "za" or "zt0" to the clobber list for inline asm.
This complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276
Commit: 0be39155bd22258b3e90468b6184bfd87a948bec
https://github.com/llvm/llvm-project/commit/0be39155bd22258b3e90468b6184bfd87a948bec
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/Sema/warn-cast-qual.c
Log Message:
-----------
[clang][Interp] Protect stores against dummy pointers
Commit: 3be79790ede30762f73b95218be8877c3b2c3774
https://github.com/llvm/llvm-project/commit/3be79790ede30762f73b95218be8877c3b2c3774
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang] Update documentation for `#pragma diagnostic` (#78095)
GCC has changed over the past decade, and we're not implementing
everything they do.
Fixes #51472
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 75c4339ef31922bf8c883a7a5dfe638ec6818ab2
https://github.com/llvm/llvm-project/commit/75c4339ef31922bf8c883a7a5dfe638ec6818ab2
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/EvaluationResult.cpp
Log Message:
-----------
[clang][Interp][NFC] Implement dumping Invalid/Valid results
This was just an omission from an earlier commit, clearly
we can print them.
Commit: 0f26441cb83c1dea9aef12c748a79e3f38e3230a
https://github.com/llvm/llvm-project/commit/0f26441cb83c1dea9aef12c748a79e3f38e3230a
Author: Maciej Gabka <maciej.gabka at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[TLI][AArch64] Adjust TLI mappings to vector functions taking linear pointers (#80296)
The masked symbols in SLEEF are incorrectly implemented as calls to non
masked variants, what only works fine for functions which do not modify
memory.
For vector variants which modify memory we can only use a non masked
symbols for now.
The SVE ArmPL mappings need to be removed for now as well.
Commit: 237a799e938aca86dc7e62def792b26974bbae5d
https://github.com/llvm/llvm-project/commit/237a799e938aca86dc7e62def792b26974bbae5d
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/IR/Builders.cpp
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Notify about block insertion when cloning an op (#80262)
`OpBuilder::clone(Operation &)` should trigger not only
`notifyOperationInserted` but also `notifyBlockInserted` (for all block
contained in `op`).
Commit: a792cb6e3e03aff22dabb6cc94db68d15d953a55
https://github.com/llvm/llvm-project/commit/a792cb6e3e03aff22dabb6cc94db68d15d953a55
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/IR/Builders.cpp
Log Message:
-----------
[mlir][IR] Do not trigger `notifyOperationInserted` for unlinked ops (#80278)
This commit changes `OpBuilder::create` and `OpBuilder::createOrFold`
such that `notifyOperationInserted` is no longer triggered if no
insertion point is set. In such a case, an unlinked operation is created
but not inserted, so `notifyOperationInserted` should not be triggered.
Note: Inserting another op into a block that belongs to an unlinked op
(e.g., by the builder of the unlinked op) will trigger a notification.
Commit: c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
https://github.com/llvm/llvm-project/commit/c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
Author: ManuelvOK <info at manuel-thieme.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
Log Message:
-----------
[Coverage] Map regions from system headers (#76950)
In 2155195131a57f2f01e7cfabb85bb027518c2dc6, the
"system-headers-coverage" option has been added but not used in all
necessary places.
This is the recommit since it has been reverted in
faef68bca852d08511ea0311d8a0d221cb202e73
Potential reviewers: @gulfemsavrun @petrhosek
Co-authored-by: Manuel Kalettka <manuel.kalettka at kernkonzept.com>
Commit: b840d2968391dd610b792a65133a1edc1bcc397c
https://github.com/llvm/llvm-project/commit/b840d2968391dd610b792a65133a1edc1bcc397c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Send notifications for `cloneRegionBefore` (#66871)
Similar to `OpBuilder::clone`, operation/block insertion notifications
should be sent when cloning the contents of a region. E.g., this is to
ensure that the newly created operations are put on the worklist of the
greedy pattern rewriter driver.
Also move `cloneRegionBefore` from `RewriterBase` to `OpBuilder`. It
only creates new IR, so it should be part of the builder API (like
`clone(Operation &)`). The function does not have to be virtual. Now
that notifications are properly sent, the override in the dialect
conversion is no longer needed.
Commit: 73e546625d6567e5a33454741d257b6929c89635
https://github.com/llvm/llvm-project/commit/73e546625d6567e5a33454741d257b6929c89635
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix up broken test case
This was not working right on armv8:
https://lab.llvm.org/buildbot/#/builders/245/builds/20020
Commit: 9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
https://github.com/llvm/llvm-project/commit/9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[mlir][memref] `memref.subview`: Verify result strides with rank reductions (#80158)
This is a follow-up on #79865. Result strides are now also verified if
the `memref.subview` op has rank reductions.
Commit: 9e649518e6038a5b9ea38cfa424468657d3be59e
https://github.com/llvm/llvm-project/commit/9e649518e6038a5b9ea38cfa424468657d3be59e
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/init-aarch64.c
Log Message:
-----------
[Clang][AArch64] Add missing SME macros (#80293)
__ARM_STATE_ZA and __ARM_STATE_ZT0 are set when the compiler can parse
the "za" and "zt0" strings in the SME attributes.
__ARM_FEATURE_SME and __ARM_FEATURE_SME2 are set when the compiler can
generate code for attributes with "za" and "zt0" state, respectively.
__ARM_FEATURE_LOCALLY_STREAMING is set when the compiler supports the
__arm_locally_streaming attribute.
Commit: 438fe1db09b0c20708ea1020519d8073c37feae8
https://github.com/llvm/llvm-project/commit/438fe1db09b0c20708ea1020519d8073c37feae8
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
Log Message:
-----------
CoverageMappingWriter: Emit `Decision` before `Expansion` (#78966)
To relax scanning record, tweak order by `Decision < Expansion`, or
`Expansion` could not be distinguished whether it belonged to `Decision`
or not.
Relevant to #77871
Commit: acf6811d0f2b6b453be46ddf7e046e1346991c98
https://github.com/llvm/llvm-project/commit/acf6811d0f2b6b453be46ddf7e046e1346991c98
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
A llvm/test/TableGen/deftype.td
Log Message:
-----------
[TableGen] Support type aliases via new keyword deftype
We can use `deftype` (not using `typedef` here to be consistent
with `def`, `defm`, `defset`, `defvar`, etc) to define type aliases.
Currently, only primitive types and type aliases are supported to be
the source type and `deftype` statements can only appear at the top
level.
Reviewers: fpetrogalli, Artem-B, nhaehnle, jroelofs
Reviewed By: jroelofs, nhaehnle, Artem-B
Pull Request: https://github.com/llvm/llvm-project/pull/79570
Commit: a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
https://github.com/llvm/llvm-project/commit/a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Lex/PPMacroExpansion.cpp
A clang/test/Preprocessor/has_builtin_cpuid.c
Log Message:
-----------
[Preprocessor] Fix __has_builtin for CPU ID functions (#80058)
My recent commit (67c1c1d) made the CPU ID builtins target-independent
so they can be used on PPC as well. However, that had the unintended
consequence of changing the behaviour of __has_builtin in that it
reports these as supported at the pre-processor level. This makes it
impossible to guard the use of these with this feature test macro which
is clearly not ideal.
This patch restores the behaviour of __has_builtin for __builtin_cpu_is,
__builtin_cpu_init,
__builtin_cpu_supports. Now the preprocessor queries the target to
determine whether the target supports the builtin.
Commit: 42ec9934e1079742e0b5d839e420bc3f746fc73b
https://github.com/llvm/llvm-project/commit/42ec9934e1079742e0b5d839e420bc3f746fc73b
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Fix gcc -Wparentheses warning [NFC]
Without this gcc warns like
../lib/Target/PowerPC/PPCAsmPrinter.cpp:1650:33: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
1650 | (InstDisp >= -32768) &&
| ~~~~~~~~~~~~~~~~~~~~~^~
1651 | "Expecting the instruction displacement for local-exec TLS "
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1652 | "variables to be between [-32768, 32768)!");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
https://github.com/llvm/llvm-project/commit/5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[SCEVExpander] Do not reuse disjoint or (#80281)
SCEV treats "or disjoint" the same as "add nsw nuw". However, when
expanding, we cannot generally replace an add SCEV node with an "or
disjoint" instruction. Just dropping the poison flag is insufficient in
this case, we would have to actually convert the or into an add.
This is a partial fix for #79861.
Commit: 84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
https://github.com/llvm/llvm-project/commit/84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
Log Message:
-----------
[MLIR][Vector] Implement memory effect for print (#80400)
Add write memory effect for the print operation. The exact memory
behavior is implemented in other print-like operations such as
`transform::PrintOp` or `gpu::printf`.
Providing memory behavior allows using the operation in passes like
buffer deallocation instead of emitting an error.
Commit: c2dea7122cd9f559f64cd0b34431d21e61f5bf15
https://github.com/llvm/llvm-project/commit/c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
Log Message:
-----------
[mlir][ArmSME] Fold extracts from 3D create_masks of SME-like masks (#80148)
When unrolling the reduction dimension of something like a matmul for
SME, it is possible to get 3D masks, which are vectors of SME-like
masks. The 2D masks for individual operations are then extracted from
the 3D masks.
i.e.:
```mlir
%mask = vector.create_mask %nonConstantDim, %a, %b : vector<4x[4]x[4]xi1>
%subMask = vector.extract %mask[2]
: vector<[4]x[4]xi1> from vector<4x[4]x[4]xi1>
```
ArmSME only supports lowering 2D create_masks, so we must fold the
extract into the create_mask. This can be done by checking if the
extraction index is within the true region, then using that select the
first dimension of the 2D mask. This is shown below.
```mlir
%extractionInTrueRegion = arith.cmpi slt, %c2, %nonConstantDim : index
%newMaskFrontDim = arith.select %extractionInTrueRegion, %a, %c0 : index
%subMask = vector.create_mask %newMaskFrontDim, %b : vector<[4]x[4]xi1>
```
Commit: 6d1d2c67e7597dc417c097d5027558b0159ed2e2
https://github.com/llvm/llvm-project/commit/6d1d2c67e7597dc417c097d5027558b0159ed2e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
[clang] Fix a possible out-of-bounds read (#80023)
Fixes #79964
Commit: 4b8e514334786e1aa6f86d7d777385aa9702d835
https://github.com/llvm/llvm-project/commit/4b8e514334786e1aa6f86d7d777385aa9702d835
Author: Tuan Chuong Goh <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Pre-Commit tests for Legalize BSWAP Vectors
Commit: 2cf415f2a03433fd3661938fb2f4af0754ad2274
https://github.com/llvm/llvm-project/commit/2cf415f2a03433fd3661938fb2f4af0754ad2274
Author: Peter Smith <peter.smith at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/SecurityTransparencyReports.rst
Log Message:
-----------
Add security group 2023 transparency report. (#80320)
Commit: ffb3589b8cb3468713d25ff2a4378918eafa7044
https://github.com/llvm/llvm-project/commit/ffb3589b8cb3468713d25ff2a4378918eafa7044
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Remove transitive <locale> include from <vector> (#80282)
This reduces the time to include `<vector>` from 468ms to 367ms.
Commit: 9410019ac977141bc73aee19690b5896ded59219
https://github.com/llvm/llvm-project/commit/9410019ac977141bc73aee19690b5896ded59219
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-combine.ll
M llvm/test/CodeGen/X86/popcnt.ll
Log Message:
-----------
[X86] Add i8 CTPOP lowering using i32 MUL (#79989)
This is the first basic proposal in #79823 - we can investigate improving support for other widths if we can find further use cases.
Commit: 10943695f76f513503162026669e84cb72275e84
https://github.com/llvm/llvm-project/commit/10943695f76f513503162026669e84cb72275e84
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)
Add support of i16 vector operation for BSWAP and change to TableGen to
select instructions
Handle vector types that are smaller/larger than legal for BSWAP
Commit: cca9f9b78fc657c280f7e4024a552af43a315bdb
https://github.com/llvm/llvm-project/commit/cca9f9b78fc657c280f7e4024a552af43a315bdb
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Commit: 2d1f5af8b0b07a4ac19eae699aa660debb1a5613
https://github.com/llvm/llvm-project/commit/2d1f5af8b0b07a4ac19eae699aa660debb1a5613
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
Use !tolower instead of repeating the name when defining a renamed Real
instruction.
Commit: 589b21f38932ed1150906fc30307f030c62f6e8f
https://github.com/llvm/llvm-project/commit/589b21f38932ed1150906fc30307f030c62f6e8f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__memory/temporary_buffer.h
Log Message:
-----------
[libc++][NFC] Remove <__type_traits/alignment_of.h> include
Commit: 2e669ff59ebb096d67d02ec51dbb7050dc5e2235
https://github.com/llvm/llvm-project/commit/2e669ff59ebb096d67d02ec51dbb7050dc5e2235
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerBuildVector* - share the same SDLoc argument instead of recreating it over and over again.
Commit: b5d35feacb7246573c6a4ab2bddc4919a4228ed5
https://github.com/llvm/llvm-project/commit/b5d35feacb7246573c6a4ab2bddc4919a4228ed5
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/avx512-arith.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/combine-addo.ll
M llvm/test/CodeGen/X86/combine-and.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-pavg.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/combine-sub.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/combine-urem.ll
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/extract-concat.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-shuffle.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/packus.ll
M llvm/test/CodeGen/X86/paddus.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/pr48215.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr61964.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/pr63507.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-512.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-512.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - load+sign-extend vector constants that can be stored in a truncated form (#79815)
Reduce the size of the vector constant by storing it in the constant pool in a truncated form, and sign-extend it as part of the load.
I've extended the existing FixupConstant functionality to support these sext constant rebuilds - we still select the smallest stored constant entry and prefer vzload/broadcast/vextload for same bitwidth to avoid domain flips.
I intend to add the matching load+zero-extend handling in a future PR, but that requires some alterations to the existing MC shuffle comments handling first.
Commit: ffd84a6a9afc43968fe24c9057bd4f86e148e283
https://github.com/llvm/llvm-project/commit/ffd84a6a9afc43968fe24c9057bd4f86e148e283
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in MemRefOps.cpp (NFC)
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2763:23:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() == droppedDims.size() && "incorrect number of bits");
~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2764:38:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() - t2.getRank() == droppedDims.count() &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~
Commit: d912f1f0cb49465b08f82fae89ece222404e5640
https://github.com/llvm/llvm-project/commit/d912f1f0cb49465b08f82fae89ece222404e5640
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
A llvm/test/tools/llvm-cov/mcdc-macro.test
Log Message:
-----------
[Coverage] Let `Decision` take account of expansions (#78969)
The current implementation (D138849) assumes `Branch`(es) would follow
after the corresponding `Decision`. It is not true if `Branch`(es) are
forwarded to expanded file ID. As a result, consecutive `Decision`(s)
would be confused with insufficient number of `Branch`(es).
`Expansion` will point `Branch`(es) in other file IDs if `Expansion` is
included in the range of `Decision`.
Fixes #77871
---------
Co-authored-by: Alan Phipps <a-phipps at ti.com>
Commit: 4cf2ed4396ddeda1487d6c5151a7dfdf14573920
https://github.com/llvm/llvm-project/commit/4cf2ed4396ddeda1487d6c5151a7dfdf14573920
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Fix -Wsign-compare in X86MCInstLower.cpp (NFC)
llvm-project/llvm/lib/Target/X86/X86MCInstLower.cpp:1588:48:
error: comparison of integers of different signs: 'unsigned int' and 'int' [-Werror,-Wsign-compare]
if (C && C->getType()->getScalarSizeInBits() == SrcEltBits) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~
1 error generated.
Commit: 319f4c03ba2909c7240ac157cc46216bf1518c10
https://github.com/llvm/llvm-project/commit/319f4c03ba2909c7240ac157cc46216bf1518c10
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/aarch64-sme-func-attrs.c
Log Message:
-----------
[Clang][AArch64] Emit 'unimplemented' diagnostic for SME (#80295)
When a function F has ZA and ZT0 state, calls another function G that
only shares ZT0 state with its caller, F will have to save ZA before
the call to G, and restore it afterwards (rather than setting up a
lazy-sve).
This is not yet implemented in LLVM and does not result in a
compile-time error either. So instead of silently generating incorrect
code, it's better to emit an error saying this is not yet implemented.
Commit: b8025d1482a9664463cfc727a0e51cad86fdf2fe
https://github.com/llvm/llvm-project/commit/b8025d1482a9664463cfc727a0e51cad86fdf2fe
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
Reapply "[AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode." (#80303)
Reapply #71556 with added lit test constraint: `REQUIRES: amdgpu-registered-target`.
This reverts commit 9791e5414960f92396582b9e9ee503ac15799312.
Commit: c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
https://github.com/llvm/llvm-project/commit/c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
Log Message:
-----------
[SCEV] Add SCEV analysis tests with congruent IVs.
This patch adds a set of tests taken
from/llvm/test/Transforms/IndVarSimplify/iv-poison.ll with multiple
congruent IVs but different set of flags on the increments.
Extra tests for https://github.com/llvm/llvm-project/pull/80430.
Commit: 7a4570acdb1a32935d96831142748ba3298a2b7f
https://github.com/llvm/llvm-project/commit/7a4570acdb1a32935d96831142748ba3298a2b7f
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/HLFIR/array-ctor-character.f90
Log Message:
-----------
[flang] sanitize set_length in lowering (#80412)
In fortran, it is possible to give a negative "i" in "character(i)" in
which case the standard says the length is zero. So the length must be
sanitized as max(0, user_input) in lowering.
This is already done when lowering specification parts, but was not done
when "character(i)" appears in array constructors. Sanitize the length
when lowering SetLength in lowering.
Fixes https://github.com/llvm/llvm-project/issues/80270
Commit: 92bbf615f50c67030ed536f08cc5bb266e0718db
https://github.com/llvm/llvm-project/commit/92bbf615f50c67030ed536f08cc5bb266e0718db
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Use function-attached target attributes for OpenMP lowering (#78291)
This patch removes the omp.target module attribute, since the
information it held on the target CPU and features is available through
the fir.target_cpu and fir.target_features module attributes. Target
outlining during the MLIR to LLVM IR translation stage is updated, so
that these attributes, at that point available as llvm.func attributes,
are passed along to the newly created function.
Commit: 3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
https://github.com/llvm/llvm-project/commit/3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] FP<->INT helpers - share the same SDLoc argument instead of recreating it over and over again.
Commit: a1df10da59e8eb0c1d90df81bf9000d2f7869328
https://github.com/llvm/llvm-project/commit/a1df10da59e8eb0c1d90df81bf9000d2f7869328
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
AMDGPU/NFC: Add predicate for supporting ds_add_f64 (#80379)
Commit: 1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
https://github.com/llvm/llvm-project/commit/1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix broken test case again
Instead of asserting that it's wrong, assert the correct
value.
See the discussion in
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Commit: 274d1b000cae57acf2dc988fcb65cfe7383ed2b0
https://github.com/llvm/llvm-project/commit/274d1b000cae57acf2dc988fcb65cfe7383ed2b0
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[NFC] Add useFPRegsForHalfType(). (#74147)
Currently, half operations can be promoted in one of two ways.
* If softPromoteHalfType() returns false, fp16 values are passed around
in fp32 registers, and whole chains of fp16 operations are promoted to
fp32 in one go.
* If softPromoteHalfType() returns true, fp16 values are passed around
in i16 registers, and individual fp16 operations are promoted to fp32
and the result truncated to fp16 right away.
The softPromoteHalfType behavior is necessary for correctness, but
changing this for an existing target breaks the ABI. Therefore, this
commit adds a third option:
* If softPromoteHalfType() returns true and useFPRegsForHalfType()
returns true as well, fp16 values are passed around in fp32 registers,
but individual fp16 operations are promoted to fp32 and the result
truncated to fp16 right away.
This change does not yet update any target to make use of it.
Commit: 1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
https://github.com/llvm/llvm-project/commit/1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
Author: lifengxiang1025 <lifengxiang.1025 at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
Log Message:
-----------
[MemProf] Fix when CallStackTrie has a single chain to leaf with multi alloc type (#79433)
Fix one corner case when `CallStackTrie` has a single chain to leaf with
multi alloc type. This will cause stackIds in function summary is empty.
Commit: 275729ae06d568e9589392c142a416fb8c2bb1a8
https://github.com/llvm/llvm-project/commit/275729ae06d568e9589392c142a416fb8c2bb1a8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
Log Message:
-----------
[X86] Generalize i8 CTPOP expansion to work with any input with 8 or less active bits
Extend #79989 slightly to use KnownBits on the CTPOP input - this should make it easier to add additional cases identified in #79823
Commit: 66b339aa6ba3ee63806c87630aec1dc6a45e63c5
https://github.com/llvm/llvm-project/commit/66b339aa6ba3ee63806c87630aec1dc6a45e63c5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
Log Message:
-----------
[IndVars] Regenerate test checks (NFC)
Commit: a986f5e218ab8a68097fcc1fd3234b8743839ef8
https://github.com/llvm/llvm-project/commit/a986f5e218ab8a68097fcc1fd3234b8743839ef8
Author: alexfh <alexfh at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
Fix clang crash when printing highlighted code in diagnostic (after #66514) (#80442)
Implements the fix proposed by Evgeny Eltsin on
https://github.com/llvm/llvm-project/pull/66514#issuecomment-1924039038.
No test case provided, since the bug is extremely sensitive to the
preprocessor
state (headers, macros, including the ones defined on command line), and
it
turned out to be non-trivial to create an isolated test.
Commit: fbf9356be07408efc05621a7a8d0472a61c66228
https://github.com/llvm/llvm-project/commit/fbf9356be07408efc05621a7a8d0472a61c66228
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Add ctpop-mask.ll - test coverage based off #79823
Commit: 46b6756255029f442165148115bad99d04057622
https://github.com/llvm/llvm-project/commit/46b6756255029f442165148115bad99d04057622
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
M clang/test/Driver/hip-options.hip
Log Message:
-----------
[AMDGPU] Diagnose unaligned atomic (#80322)
AMDGPU does not support unaligned atomics, therefore make the warning an
error.
This patch is transferred from
https://reviews.llvm.org/D99201
Commit: 43dd1e84df1ecdad872e1004af47b489e08fc228
https://github.com/llvm/llvm-project/commit/43dd1e84df1ecdad872e1004af47b489e08fc228
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[SCEV] Move canReuseInstruction() helper into SCEV (NFC)
To allow reusing it in IndVars.
Commit: 7524b037257cdeb67e3ed80364da94eab8e98122
https://github.com/llvm/llvm-project/commit/7524b037257cdeb67e3ed80364da94eab8e98122
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add note about calendar timezones (#80346)
Commit: 67eee4a029797c09129889c3655416d1be487cfe
https://github.com/llvm/llvm-project/commit/67eee4a029797c09129889c3655416d1be487cfe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
[libc++] Optimize vector growing of trivially relocatable types (#76657)
This patch introduces a new trait to represent whether a type is
trivially
relocatable, and uses that trait to optimize the growth of a std::vector
of trivially relocatable objects.
```
--------------------------------------------------
Benchmark old new
--------------------------------------------------
bm_grow<int> 1354 ns 1301 ns
bm_grow<std::string> 5584 ns 3370 ns
bm_grow<std::unique_ptr<int>> 3506 ns 1994 ns
bm_grow<std::deque<int>> 27114 ns 27209 ns
```
This also changes to order of moving and destroying the objects when
growing the vector. This should not affect our conformance.
Commit: 30503116550c2bffe706366e93dbaee15850014c
https://github.com/llvm/llvm-project/commit/30503116550c2bffe706366e93dbaee15850014c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 67eee4a02979
Commit: b629414ae13d6dcd641e92d0389c5d4b7638a644
https://github.com/llvm/llvm-project/commit/b629414ae13d6dcd641e92d0389c5d4b7638a644
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
Log Message:
-----------
[libc][NFC] Simplify logic in `sqrt` (#80426)
Commit: 28865da37451904c4654f20cdaddee815fdeff1d
https://github.com/llvm/llvm-project/commit/28865da37451904c4654f20cdaddee815fdeff1d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Log Message:
-----------
[LSR][term-fold] Adjust expansion budget based on trip count (#80304)
Follow up to https://github.com/llvm/llvm-project/pull/74747
This change extends the previously added fixed expansion threshold by
scaling down the cost allowed for an expansion for a loop with either a
small known trip count or a profile which indicates the trip count is
likely small. The goal here is to improve code generation for a loop
nest where the outer loop has a high trip count, and the inner loop runs
only a handful of iterations.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 1437a83491cbe4af1b452a3f862a6b609057c26d
https://github.com/llvm/llvm-project/commit/1437a83491cbe4af1b452a3f862a6b609057c26d
Author: Rushi Bhamani <99245918+rushiraj7677 at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
Log Message:
-----------
Add --abort-on-invalid-reduction to more lit tests (#80263)
Commit: b78b264518e0f341d99a4291cbf24134c7536f6d
https://github.com/llvm/llvm-project/commit/b78b264518e0f341d99a4291cbf24134c7536f6d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/RISCV/gep.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[TTI] Add costing for vp.strided.load and vp.strided.store (#80360)
The primary motivation of this patch is to add testing infrastructure
atop the recently landed 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7, so
that we can separate the costing aspects of strided memory operations
from the SLP implementation details.
I want to be clear that I am *not* proposing that we use the
vp.strided.* forms as our canonical IR representation. I'm merely using
them as a testing vehicle to exercise the costing machinery. The
canonical IR form remains a masked.gather or masked.scatter. I do want
to explore adding a non-vp strided load/store intrinsic, but that's a
separate line of work.
There is one costing change included in this. As I wrote my test, I
discovered that the default implementation was scalarized (if invoked
via generic routines such as getInstructionCost), and when adding the
call into the strided specific costing discovered that we hadn't modeled
the fallback to scalarization properly in the initial patch. After
fixing that, there is a minor difference in scalarization cost reported
for the unaligned case but I believe that to be uninteresting.
For the record, I did confirm that vp.strided.store is lowered to a
strided store on RISCV. :)
Commit: a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
https://github.com/llvm/llvm-project/commit/a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
Author: Manish Kausik H <46352931+Nirhar at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
A llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
Log Message:
-----------
[SelectionDAG] Use unaligned store to move AVX registers onto stack for `extractelement` (#78422)
Prior to this patch, SelectionDAG generated aligned move onto stacks for
AVX registers when the function was marked as a no-realign-stack
function. This lead to misalignment between the stack and the
instruction generated. This patch fixes the issue.
Fixes #77730
Commit: 7b08b4360b488b35428c97132b3f9d2a777bd770
https://github.com/llvm/llvm-project/commit/7b08b4360b488b35428c97132b3f9d2a777bd770
Author: Nathan Gauër <brioche at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
Log Message:
-----------
[SPIR-V] add convergence region analysis (#78456)
This new analysis returns a hierarchical view of the convergence regions
in the given function.
This will allow our passes to query which basic block belongs to which
convergence region, and structurize the code in consequence.
Definition
----------
A convergence region is a CFG with:
- a single entry node.
- one or multiple exit nodes (different from LLVM's regions).
- one back-edge
- zero or more subregions.
Excluding sub-regions nodes, the nodes of a region can only reference a
single convergence token. A subregion uses a different convergence
token.
Algorithm
---------
This algorithm assumes all loops are in the Simplify form.
Create an initial convergence region for the whole function.
- the convergence token is the function entry token.
- the entry is the function entrypoint.
- Exits are all the basic blocks terminating with a return instruction.
Take the function CFG, and process it in DAG order (ignoring
back-edges). If a basic block is a loop header:
- Create a new region.
- The parent region is the parent's loop region if any, otherwise, the
top level region.
- The region blocks are all the blocks belonging to this loop.
- For each loop exit: - visit the rest of the CFG in DAG order (ignore
back-edges). - if the region's convergence token is found, add all the
blocks dominated by the exit from which the token is reachable to the
region.
- continue the algorithm with the loop headers successors.
Commit: 7ecfb66c77ad77dabbb705cbb1f3b17a3d1391a4
https://github.com/llvm/llvm-project/commit/7ecfb66c77ad77dabbb705cbb1f3b17a3d1391a4
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.meaning.general/p3.cpp
Log Message:
-----------
[Clang][Sema] Correctly look up primary template for variable template specializations (#80359)
Consider the following:
```
namespace N0 {
namespace N1 {
template<typename T>
int x1 = 0;
}
using namespace N1;
}
template<>
int N0::x1<int>;
```
According to [dcl.meaning.general] p3.3:
> - If the _declarator_ declares an explicit instantiation or a partial
or explicit specialization, the _declarator_ does not bind a name. If it
declares a class member, the terminal name of the _declarator-id_ is not
looked up; otherwise, **only those lookup results that are nominable in
`S` are considered when identifying any function template specialization
being declared**.
In particular, the requirement for lookup results to be nominal in the
lookup context of the terminal name of the _declarator-id_ only applies
to function template specializations -- not variable template
specializations. We currently reject the above declaration, but we do
(correctly) accept it if the using-directive is replaced with a `using`
declaration naming `N0::N1::x1`. This patch makes it so the above
specialization is (correctly) accepted.
Commit: 3a758076f54d521d20e32856a62c7d24803ee9e8
https://github.com/llvm/llvm-project/commit/3a758076f54d521d20e32856a62c7d24803ee9e8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Allow i8 CTPOP expansion to work with a 'shifted' active bits value of 8 bits or less
Shift down the value so the active bits are at the lsb
Commit: faeb3d1f106d607f51babe3770e899bc9bda7f3a
https://github.com/llvm/llvm-project/commit/faeb3d1f106d607f51babe3770e899bc9bda7f3a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
Log Message:
-----------
[AMDGPU] Regenerate ctpop64.ll test checks
Commit: 1156bbc5b1837e688b0e5d6952f1a900aca29062
https://github.com/llvm/llvm-project/commit/1156bbc5b1837e688b0e5d6952f1a900aca29062
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/TypeLoc.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/drs/dr7xx.cpp
M clang/test/CXX/temp/temp.decls/temp.class/temp.mem.func/p1.cpp
A clang/test/CXX/temp/temp.names/p5.cpp
M clang/test/CXX/temp/temp.spec/part.spec.cpp
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaTemplate/class-template-spec.cpp
Log Message:
-----------
[Clang][Sema] Diagnose use of template keyword after declarative nested-name-specifiers (#78595)
According to [temp.names] p5:
> The keyword template shall not appear immediately after a declarative nested-name-specifier.
[expr.prim.id.qual] p2 defines a declarative nested-name-specifier as follows:
> A nested-name-specifier is declarative if it is part of
> - a class-head-name,
> - an enum-head-name,
> - a qualified-id that is the id-expression of a declarator-id, or
> - a declarative nested-name-specifier.
Note: I believe this definition is defective as it doesn't include _nested-name-specifiers_ appearing in _elaborated-type-specifiers_ that declare partial/explicit specializations and explicit instantiations. See my post to the core reflector. Minus a few bugs that are addressed by this PR, this is how we implement it.
This means that declarations like:
```
template<typename>
struct A
{
template<typename>
struct B
{
void f();
};
};
template<typename T>
template<typename U>
void A<T>::template B<U>::f() { } // error: 'template' cannot be used after a declarative nested name specifier
```
are ill-formed. This PR add diagnostics for such declarations. The name of the diagnostic group is `template-in-declaration-name`.
Regarding the aforementioned "few bugs that are addressed by this PR" in order to correctly implement this:
- `CheckClassTemplate` did not call `diagnoseQualifiedDeclaration` when the semantic context was dependent. This allowed for constructs like:
```
struct A
{
template<typename T>
struct B
{
template<typename U>
struct C;
};
};
template<typename T>
template<typename U>
struct decltype(A())::B<T>::C { };
```
- `ActOnClassTemplateSpecialization` did not call `diagnoseQualifiedDeclaration` at all, allowing for qualified partial/explicit specializations at class scope and other related nonsense
- `TreeTransform::TransformNestedNameSpecifierLoc` would rebuild a `NestedNameSpecifier::TypeSpecWithTemplate` as a `NestedNameSpecifier::TypeSpec`
- `TemplateSpecializationTypeLoc::initializeLocal` would set the `template` keyword `SourceLocation` to the provided `Loc` parameter, which would result in a `TemplateSpecializationTypeLoc` obtained via `ASTContext::getTrivialTypeSourceInfo` being displayed as always having a `template` prefix (since the presence of the keyword is not stored anywhere else).
Commit: 9cc2122bf5a81f7063c2a32b2cb78c8d615578a1
https://github.com/llvm/llvm-project/commit/9cc2122bf5a81f7063c2a32b2cb78c8d615578a1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/type-traits.cpp
M libcxx/include/__type_traits/is_nothrow_convertible.h
Log Message:
-----------
[Clang][libc++] Implement __is_nothrow_convertible and use it in libc++ (#80436)
GCC 13 has implemented this builtin.
Commit: d4de4c3eafa9b70c255a4d6d5a14dccff79d10e9
https://github.com/llvm/llvm-project/commit/d4de4c3eafa9b70c255a4d6d5a14dccff79d10e9
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/Sema/inline-asm-validate-aarch64.c
M llvm/docs/LangRef.rst
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
Log Message:
-----------
[AArch64] Support optional constant offset for constraint "S" (#80255)
Modify the initial implementation (https://reviews.llvm.org/D46745) to
support a constant offset so that the following code will compile:
```
int a[2][2];
void foo() { asm("// %0" :: "S"(&a[1][1])); }
```
We use the generic code path for "s". In GCC's aarch64 port, "S" is
supported for PIC while "s" isn't, making "s" less useful. We implement
"S" but not "s".
Similar to #80201 for RISC-V.
Commit: ef1f999e13bd58394bc1099c87a470d91682153d
https://github.com/llvm/llvm-project/commit/ef1f999e13bd58394bc1099c87a470d91682153d
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M lld/wasm/InputFiles.cpp
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/Object/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
Log Message:
-----------
[Object][Wasm] Move WasmSymbolInfo directly into WasmSymbol (NFC) (#80219)
Move the WasmSymbolInfos from their own vector on the WasmLinkingData
directly into the WasmSymbol object. Removing the const-ref to an
external object allows the vector of WasmSymbols to be safely
expanded/reallocated; generating symbol info from the name section will
require this, as the numbers of function and data segment names are
stored separately.
This is a step toward generating symbol information from name sections
for #76107
Commit: 74fb205876be681d2ca9d8bdd23e171e671df5e1
https://github.com/llvm/llvm-project/commit/74fb205876be681d2ca9d8bdd23e171e671df5e1
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.signed_integral.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.unsigned_integral.pass.cpp
Log Message:
-----------
[libc++][format] Improves tests. (#76291)
Tests the returned type. This was first done for the vector<bool>
formatters. This adds it to the other formatters where it wasn't done
yet.
Commit: 7ca4012e115a39c09647bbd28105ea7e5edcd441
https://github.com/llvm/llvm-project/commit/7ca4012e115a39c09647bbd28105ea7e5edcd441
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/docs/AliasingAnalysisFIR.md
M flang/docs/FIRArrayOperations.md
M flang/docs/FlangDriver.md
M flang/docs/HighLevelFIR.md
M flang/docs/OpenACC-descriptor-management.md
M flang/docs/Overview.md
M flang/docs/ParameterizedDerivedTypes.md
M flang/docs/PolymorphicEntities.md
M flang/docs/ProcedurePointer.md
M flang/docs/conf.py
M flang/docs/index.md
Log Message:
-----------
[flang][docs] Fix broken flang website (#80363)
These are several fixes for the flang site. The look has been changed to
match clang since flang, like clang, is a frontend. Some broken links
were removed. Most fixes are to secton titles so the table of contents
is generated correctly. A minor typo has been fixed.
Commit: ad0acf9ef6ff219795159663dbf59116fef416db
https://github.com/llvm/llvm-project/commit/ad0acf9ef6ff219795159663dbf59116fef416db
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
Log Message:
-----------
[GISEL] More accounting for scalable vectors when operating on LLTs (#80372)
This is stacked on by #80377 and #80378
Commit: bc06cd5cbcfc22dd976f6742d10bc934e1353b8a
https://github.com/llvm/llvm-project/commit/bc06cd5cbcfc22dd976f6742d10bc934e1353b8a
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A .github/workflows/issue-write.yml
M .github/workflows/pr-code-format.yml
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
[workflows] Split pr-code-format into two parts to make it more secure (#78216)
Actions triggered by pull_request_target events have access to all
repository secrets, so it is unsafe to use them when executing untrusted
code. The pr-code-format workflow does not execute any untrusted code,
but it passes untrused input into clang-format. An attacker could use
this to exploit a flaw in clang-format and potentially gain access to
the repository secrets.
By splitting the workflow, we can use the pull_request target which is
more secure and isolate the issue write permissions in a separate job.
The pull_request target also makes it easier to test changes to the
code-format-helepr.py script, because the version of the script from the
pull request will be used rather than the version of the script from
main.
Fixes #77142
Commit: dd0356d741aefa25ece973d6cc4b55dcb73b84b4
https://github.com/llvm/llvm-project/commit/dd0356d741aefa25ece973d6cc4b55dcb73b84b4
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/utils/perf-training/CMakeLists.txt
M clang/utils/perf-training/perf-helper.py
M llvm/docs/AdvancedBuilds.rst
Log Message:
-----------
[CMake][PGO] Add option for using an external project to generate profile data (#78879)
The new CLANG_PGO_TRAINING_DATA_SOURCE_DIR allows users to specify a
CMake project to use for generating the profile data. For example, to
use the llvm-test-suite to generate profile data you would do:
$ cmake -G Ninja -B build -S llvm -C <path to
source>/clang/cmake/caches/PGO.cmake \
-DBOOTSTRAP_CLANG_PGO_TRAINING_DATA_SOURCE_DIR=<path to llvm-test-suite>
\
-DBOOTSTRAP_CLANG_PGO_TRAINING_DEPS=runtimes
Note that the CLANG_PERF_TRAINING_DEPS has been renamed to
CLANG_PGO_TRAINING_DEPS.
---------
Co-authored-by: Petr Hosek <phosek at google.com>
Commit: e12be9cde44f92bc5a788930508a7fd13db78f11
https://github.com/llvm/llvm-project/commit/e12be9cde44f92bc5a788930508a7fd13db78f11
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/test/CodeGen/RISCV/rv64-legal-i32/condops.ll
Log Message:
-----------
[RISCV] Don't promote ISD::SELECT with rv64-legal-i32 when XTHeadCondMov is enabled.
Fixes an infinite loop.
Test copied from the non-rv64-legal-i32 test.
Commit: 1ac68462637749d44695361cfce3225cc107fd4e
https://github.com/llvm/llvm-project/commit/1ac68462637749d44695361cfce3225cc107fd4e
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
A mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dilated_conv_2d_nhwc_hwcf.mlir
Log Message:
-----------
[mlir][sparse] support sparse dilated convolution. (#80470)
Commit: 9a4a4c3f740226ecfe78db407b5b4333bfe2f8bc
https://github.com/llvm/llvm-project/commit/9a4a4c3f740226ecfe78db407b5b4333bfe2f8bc
Author: David Blaikie <dblaikie at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/ADT/StringMap.h
M llvm/lib/Support/StringMap.cpp
M llvm/unittests/ADT/StringMapTest.cpp
Log Message:
-----------
Reapply "[ADT][StringMap] Add ability to precompute and reuse the string hash"
Reverted due to an internally discovered lld crash, which turned out to
be an existing lld bug that got tickled by this changes. That's
addressed in dee8786f70a3d62b639113343fa36ef55bdbad63 so let's have
another go with this change.
Original commit message:
Useful for lldb's const string pool, using the hash to determine which
string map to lock and query/insert.
Derived from https://reviews.llvm.org/D122974 by Luboš Luňák
This reverts commit f976719fb2cb23364957e5993f7fc3684ee15391.
Effectively reapplying 67c631d283fc96d652304199cd625be426b98f8e.
Commit: f6b387589d648945372528a4ac77c58f310e5165
https://github.com/llvm/llvm-project/commit/f6b387589d648945372528a4ac77c58f310e5165
Author: David Blaikie <dblaikie at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M lldb/source/Utility/ConstString.cpp
M llvm/lib/Support/StringMap.cpp
Log Message:
-----------
Reapply "lldb: Cache string hash during ConstString pool queries/insertions"
Reverted due to an internally discovered lld crash due to the underlying
StringMap changes, which turned out to be an existing lld bug that got
tickled by the StringMap changes. That's addressed in
dee8786f70a3d62b639113343fa36ef55bdbad63 so let's have another go with
this change.
Original commit message:
lldb was rehashing the string 3 times (once to determine which StringMap
to use, once to query the StringMap, once to insert) on insertion (twice
on successful lookup).
This patch allows the lldb to benefit from hash improvements in LLVM
(from djbHash to xxh3).
Though further changes would be needed to cache this value to disk - we
shouldn't rely on the StringMap::hash remaining the same in the
future/this value should not be serialized to disk. If we want cache
this value StringMap should take a hashing template parameter to allow
for a fixed hash to be requested.
This reverts commit 5bc1adff69315dcef670e9fcbe04067b5d5963fb.
Effectively reapplying the original 2e197602305be18b963928e6ae024a004a95af6d.
Commit: 06c14c03dae6dcd0b24b5b0e427bbecd97cf0eff
https://github.com/llvm/llvm-project/commit/06c14c03dae6dcd0b24b5b0e427bbecd97cf0eff
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
R .github/workflows/issue-write.yml
M .github/workflows/pr-code-format.yml
M llvm/utils/git/code-format-helper.py
Log Message:
-----------
Revert "[workflows] Split pr-code-format into two parts to make it more secure (#78216)"
This reverts commit bc06cd5cbcfc22dd976f6742d10bc934e1353b8a.
This caused the job to fail for PRs which still had an older version
of code-format-helper.py in their tree.
Commit: 095367a521fc9ff714e1779e507bdd91d4fe9c7d
https://github.com/llvm/llvm-project/commit/095367a521fc9ff714e1779e507bdd91d4fe9c7d
Author: Alexander Yermolovich <43973793+ayermolo at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
Log Message:
-----------
[LLVM][DWARF] Chnage order for .debug_names abbrev print out (#80229)
This stemps from conversatin in:
https://github.com/llvm/llvm-project/pull/77457#discussion_r1457889792.
Right now Abbrev code for abbrev is combination of DIE TAG and other
attributes.
In the future it will be changed to be an index. Since DenseSet does not
preserve an order, added a sort based on abbrev code. Once change to
index is
made, it will print out abbrevs in the order they are stored.
Commit: 2352fdd2026e36c4206053331deba1a70b70d925
https://github.com/llvm/llvm-project/commit/2352fdd2026e36c4206053331deba1a70b70d925
Author: Kirill Stoimenov <kstoimenov at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
R libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
R libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
Revert "[libc++] Optimize vector growing of trivially relocatable types (#76657)"
Broke sanitizer bots: https://lab.llvm.org/buildbot/#/builders/5/builds/40641
This reverts commit 67eee4a029797c09129889c3655416d1be487cfe.
Commit: cc38cd856d9a9df77d5d727377e38a891807774b
https://github.com/llvm/llvm-project/commit/cc38cd856d9a9df77d5d727377e38a891807774b
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.h
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.h
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.h
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.cpp
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.h
M clang-tools-extra/clang-tidy/llvm/HeaderGuardCheck.h
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.h
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.h
M clang-tools-extra/clang-tidy/utils/HeaderGuard.cpp
M clang-tools-extra/clang-tidy/utils/HeaderGuard.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/suspicious-include.rst
M clang-tools-extra/docs/clang-tidy/checks/google/build-namespaces.rst
M clang-tools-extra/docs/clang-tidy/checks/google/global-names-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/header-guard.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/definitions-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unused-using-decls.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-anonymous-namespace.rst
Log Message:
-----------
[clang-tidy] Remove check-specific HeaderFileExtensions and Implement… (#80333)
…ationFileExtensions
Deprecated since clang-tidy 17. Use the corresponding global options
instead.
Fixes #61947
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: 7f828c4a2b7d9508ba369efff4dc259974eba048
https://github.com/llvm/llvm-project/commit/7f828c4a2b7d9508ba369efff4dc259974eba048
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn] Add dummy build file for SPIRVTests
sync_source_lists_from_cmake.py checks that every unittest in CMake
also exists in the GN build. 7b08b4360b48 added SPRIVTests, but the GN
build doesn't include the SPIRV target. So add a dummy target for this
to placate the check.
See also VETests in the gn build, which has the same setup.
Commit: 4ca0e00af569d74c479c66d19a5ffaf41fcb08d9
https://github.com/llvm/llvm-project/commit/4ca0e00af569d74c479c66d19a5ffaf41fcb08d9
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
Log Message:
-----------
[gn] Fix typo in SPIRVTests dummy target comment
Commit: 9c2446ea7c7149af6057c10a22e55b833bf4cc7a
https://github.com/llvm/llvm-project/commit/9c2446ea7c7149af6057c10a22e55b833bf4cc7a
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 2352fdd2026e
Commit: 05a6cb208635a54fb63622f13420e4d8549e5ba1
https://github.com/llvm/llvm-project/commit/05a6cb208635a54fb63622f13420e4d8549e5ba1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
A clang/test/SemaCXX/libstdcxx_is_nothrow_convertible_hack.cpp
Log Message:
-----------
[Clang] Allow __is_nothrow_convertible to be used as an identifier (#80476)
`__is_nothrow_convertible` has been used by libstdc++ previously as an
identifier.
Commit: a4cd9812bacf959ba7a1e7dbb022b7546f5952e3
https://github.com/llvm/llvm-project/commit/a4cd9812bacf959ba7a1e7dbb022b7546f5952e3
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
A llvm/include/llvm/IR/Analysis.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
Log Message:
-----------
[NFC][PassManager] Remove PreservedAnalysesT template parameter (#80324)
This is always PreservedAnalyses. Perhaps in the past there was the idea
to make some types of passes return more invalidation information, but
that hasn't happened.
Requires splitting out some analysis classes into a header so
PassManagerInternal.h can see the definition of PreservedAnalyses.
Commit: 52864d9c7bd49ca41191bd34fcee47f61cfea743
https://github.com/llvm/llvm-project/commit/52864d9c7bd49ca41191bd34fcee47f61cfea743
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/arm-half-promote.ll
M llvm/test/CodeGen/ARM/fp16-args.ll
M llvm/test/CodeGen/ARM/fp16-instructions.ll
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/ARM/llvm.exp10.ll
M llvm/test/CodeGen/ARM/llvm.frexp.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/Thumb2/mve-vabd.ll
Log Message:
-----------
[ARM] Switch to soft promoting half types. (#80440)
The traditional promotion is known to generate wrong code.
Fixes #73805.
Commit: 659419ac2f05035cd8ff19806a9e48ccc725d3ba
https://github.com/llvm/llvm-project/commit/659419ac2f05035cd8ff19806a9e48ccc725d3ba
Author: Jon Roelofs <jonathan_roelofs at apple.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc
Log Message:
-----------
[builtins][FMV] Remove dead include from fmv/apple.inc. NFC
Commit: ec73441f2b5bea696e6cb5af07e740fa34fb4d47
https://github.com/llvm/llvm-project/commit/ec73441f2b5bea696e6cb5af07e740fa34fb4d47
Author: Usama Hameed <u_hameed at apple.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/Instrumentation/AddressSanitizer/global_with_comdat.ll
Log Message:
-----------
[Clang][Test] Delete hardcoded version string from test (#80384)
Remove hardcoded string from test
rdar://120498671
Commit: 0d6ed8399f35cc8b23a8e6d094379e3d0dd71c45
https://github.com/llvm/llvm-project/commit/0d6ed8399f35cc8b23a8e6d094379e3d0dd71c45
Author: Florian Mayer <fmayer at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
Log Message:
-----------
[NFC] reorder AND to check cheaper condition first
Commit: 5294ad1d5c995850ecc903ff2c3464d37cfb49c2
https://github.com/llvm/llvm-project/commit/5294ad1d5c995850ecc903ff2c3464d37cfb49c2
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Dialect/Arith/canonicalize.mlir
Log Message:
-----------
[mlir][arith] Improve `extf` folder (#80232)
* Use APFloat conversion function to avoid losing information by
converting to `double`. This would be the case with large types like
`f80` or `f128`.
* Check for potential information loss. This is intended for small
floating point types that may have values not present in larger ones
(e.g., f8m2e5fnuz and f16).
* Support folding vector constants.
Commit: 7a94acb2da5b20d12f13f3c5f4eb0f3f46e78e73
https://github.com/llvm/llvm-project/commit/7a94acb2da5b20d12f13f3c5f4eb0f3f46e78e73
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/AST/TypePrinter.cpp
A clang/test/AST/ast-dump-pack-indexing-crash.cpp
Log Message:
-----------
[Clang] Fix a crash when dumping a pack indexing type. (#80439)
Fix a crash caused by incorrect assumptions
Reported here
https://github.com/llvm/llvm-project/pull/72644#discussion_r1469525524
Commit: 5eae09519c8ca208e0d971acce35870955612615
https://github.com/llvm/llvm-project/commit/5eae09519c8ca208e0d971acce35870955612615
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Rename some SubtargetFeature names to remove an extra 's'. NFC
I wrote FeaturesStdExt instead of FeatureStdExt in a previous patch.
Commit: 0ce61e48ce0a2ca401599318401079e42ed5b0f9
https://github.com/llvm/llvm-project/commit/0ce61e48ce0a2ca401599318401079e42ed5b0f9
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libc/docs/index.rst
A libc/docs/search.rst
Log Message:
-----------
[libc] add doc for search.h (#80492)
Commit: 2d2f962c9b646e809c58eccf6a46ed6b619ac252
https://github.com/llvm/llvm-project/commit/2d2f962c9b646e809c58eccf6a46ed6b619ac252
Author: Martin Storsjö <martin at martin.st>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M openmp/runtime/src/CMakeLists.txt
Log Message:
-----------
[openmp] Add a dependency on the separate import library (#80449)
Currently, when doing e.g. "ninja check-openmp", the check-openmp target
only depends on the target "omp", which builds the library. Thus by
doing that, the separate import library "libomp.lib", which is generated
directly from a def file, never gets created, unless one does a separate
invocation first, that builds all targets.
To fix this, make the "omp" target depend on the target for the separate
import library, whenever that is created/used.
Commit: 820f244aa92f11292e59440c9bc5afbdec395b20
https://github.com/llvm/llvm-project/commit/820f244aa92f11292e59440c9bc5afbdec395b20
Author: Yijia Gu <yijiagu at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bazel] Add missing dependency in ArithDialect
Commit: 31350c2681b4893a5018ea19ca8f0ed322b8b0b2
https://github.com/llvm/llvm-project/commit/31350c2681b4893a5018ea19ca8f0ed322b8b0b2
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
Log Message:
-----------
[mlir][openacc][NFC] Add information about getters for operands with device_type (#80389)
Add information in the operation's description about which operands must
be accessed with special getters for device_type support.
Commit: 0da21043630c3f5af3806945eb64e1c5ef261798
https://github.com/llvm/llvm-project/commit/0da21043630c3f5af3806945eb64e1c5ef261798
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/lib/Optimizer/Dialect/FIROps.cpp
A flang/test/Fir/OpenACC/propagate-attr-folding.fir
Log Message:
-----------
[flang][openacc] Do not loose attributes on folding (#80516)
hlfir.declare introduce some boxes that can be later optimized away. The
OpenACC lowering is currently setting some attributes on FIR operations
to track declare variables. When the boxes are optimized away these
attributes are lost. This patch propagate OpenACC attributes from
box_addr op to the defining op of the folding result.
Commit: 42d6eb54752c37c2583301158e30648cf09195a4
https://github.com/llvm/llvm-project/commit/42d6eb54752c37c2583301158e30648cf09195a4
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
Log Message:
-----------
[MemCpyOpt] Handle scalable aggregate types in memmove/memset formation (#80487)
Without this change, the included test cases crash the compiler. I
believe this is fallout from the homogenous scalable struct work from a
while back; I think we just forgot to update this case.
Likely to fix https://github.com/llvm/llvm-project/issues/80463.
Commit: b49fa212891983517f2988c60529c6994e2fed7c
https://github.com/llvm/llvm-project/commit/b49fa212891983517f2988c60529c6994e2fed7c
Author: yubingex007-a11y <bing1.yu at intel.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/concat-fpext-v2bf16.ll
Log Message:
-----------
[X86] Stop custom-widening v2f32 = fpext v2bf16 (#80106)
Commit: 82a32140acb52472241f04644cdcf88a4cf4bee8
https://github.com/llvm/llvm-project/commit/82a32140acb52472241f04644cdcf88a4cf4bee8
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaType.cpp
M clang/test/SemaCXX/function-type-qual.cpp
Log Message:
-----------
[Clang][Sema] Fix crash with const qualified member operator new (#80327)
We should diagnose a const qualified member operator new but we fail to
do so and this leads to crash during debug info generation.
The fix is to diagnose this as ill-formed in the front-end.
Fixes: https://github.com/llvm/llvm-project/issues/79748
Commit: b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c
https://github.com/llvm/llvm-project/commit/b8d92e1c4726ba6da9f7a6f388c08b3acd5cb62c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix crash in lowerVPSpliceExperimental with RV64LegalI32.
EVL1 will be i32 and not get type legalized to i64 so we need to
manually promote it to XLenVT.
Commit: 78b4e7c5e349d8c101b50affbd260eb109748f8f
https://github.com/llvm/llvm-project/commit/78b4e7c5e349d8c101b50affbd260eb109748f8f
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/test/MC/WebAssembly/tables.s
M llvm/test/MC/WebAssembly/type-checker-errors.s
Log Message:
-----------
[WebAssembly] validate `table.grow` correctly (#80437)
This PR add support in wasm asm type checker to implement checker of
`table.grow`
Fixes: #79966.
Commit: 141de749597c7b59ebe2c4aa7ee573d124dc903c
https://github.com/llvm/llvm-project/commit/141de749597c7b59ebe2c4aa7ee573d124dc903c
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaOverload.cpp
M clang/test/SemaTemplate/concepts-recovery-expr.cpp
Log Message:
-----------
[clang][Sema] Populate function template depth at AddTemplateOverloadCandidate (#80395)
This is yet another one-line patch to fix crashes on constraint
substitution.
```cpp
template <class, class> struct formatter;
template <class, class> struct basic_format_context {};
template <typename CharType>
concept has_format_function = format(basic_format_context<CharType, CharType>());
template <typename ValueType, typename CharType>
requires has_format_function<CharType>
struct formatter<ValueType, CharType> {
template <typename OutputIt>
CharType format(basic_format_context<OutputIt, CharType>);
};
```
In this case, we would build up a `RecoveryExpr` for a call within a
constraint expression due to the absence of viable functions. The
heuristic algorithm attempted to find such a function inside of a
ClassTemplatePartialSpecialization, from which we started to substitute
its requires-expression, and it succeeded with a FunctionTemplate such
that
1) It has only one parameter, which is dependent.
2) The only one parameter depends on two template parameters. They are,
in canonical form, `<template-parameter-1-0>` and
`<template-parameter-0-1>` respectively.
Before we emit an error, we still want to recover the most viable
functions. This goes downhill to deducing template parameters against
its arguments, where we would collect the argument type with the same
depth as the parameter type into a Deduced set. The size of the set is
presumed to be that of function template parameters, which is 1 in this
case. However, since we haven't yet properly set the template depth
before the dance, we'll end up putting the type for
`<template-parameter-0-1>` to the second position of Deduced set, which
is unfortunately an access violation!
The bug seems to appear since clang 12.0.
This fixes [the
case](https://github.com/llvm/llvm-project/issues/58548#issuecomment-1287935336).
Commit: 7278cb5a388e0f2f4000dc8d6b3b421de66a945b
https://github.com/llvm/llvm-project/commit/7278cb5a388e0f2f4000dc8d6b3b421de66a945b
Author: joyhou-hw <houzhenyu at huawei.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.h
M clang/test/Sema/attr-aligned.c
Log Message:
-----------
[X86] [iamcu] Fix wrong alignment value for attr (aligned) with -miamcu (#80401)
attribute ((aligned)) should be 4 for -miamcu.
relate: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=66818
Commit: e7ec0c972e6f5ddd01099fd05ca24352cb992b44
https://github.com/llvm/llvm-project/commit/e7ec0c972e6f5ddd01099fd05ca24352cb992b44
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[CodeGen] Port PrintMIR to new pass manager (#79440)
The legacy version print machine functions to a string stream, then
output the module and string in `doFinalization`. This patch break
`MIRPrintingPass` into two parts `PrintMIRPreparePass` and
`PrintMIRPass`. `PrintMIRPreparePass` output the original IR in yaml
string, `PrintMIRPass` just print the machine function, so we can avoid
the `doFinalization`.
Commit: f5154b9c9888f3b1b243d9a142585fabf643f422
https://github.com/llvm/llvm-project/commit/f5154b9c9888f3b1b243d9a142585fabf643f422
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
Log Message:
-----------
[clang][RISCV] Enable struct of homogeneous scalable vector as function argument (#78550)
llvm IR supports struct as function input, so RISCV tuple
type can just use struct of homogeneous scalable vector instead
of flatten them.
Commit: d9850fe23cc69b784cf655405cdfae7defa44573
https://github.com/llvm/llvm-project/commit/d9850fe23cc69b784cf655405cdfae7defa44573
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvtbf16.c
Log Message:
-----------
[RISCV][clang] Add Zvfbfmin C intrinsics support (#79618)
Commit: cca3db93e0d441f943387d519702db2d3095f4ca
https://github.com/llvm/llvm-project/commit/cca3db93e0d441f943387d519702db2d3095f4ca
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M libc/src/__support/CPP/expected.h
Log Message:
-----------
[libc][NFC] Fix accessor qualifiers for `cpp::expected` (#80424)
Commit: cba1b64099a0558499c7a355db4c59bb5851b6aa
https://github.com/llvm/llvm-project/commit/cba1b64099a0558499c7a355db4c59bb5851b6aa
Author: Michael Klemm <michael.klemm at amd.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/acosd.f90
A flang/test/Lower/Intrinsics/asind.f90
Log Message:
-----------
[flang] Implement ACOSD and ASIND (#80448)
This PR implements two missing intrinsics from F2023: ACOSD and ASIND.
The implementation breaks them down to the existing ACOS and ASIN
implementation.
Commit: 260fe032c2506cd53c6a813a71c2f096ba161e7f
https://github.com/llvm/llvm-project/commit/260fe032c2506cd53c6a813a71c2f096ba161e7f
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[llvm][AArch64][TargetParser][NFC] Use parseArchExtension in parseModifier. (#80427)
This allows making changes in parseArchExtension to make their way in
the command line as well, not only in target attributes.
Commit: 514d0691f4da40d5bb6d618a673e975b8eacfb77
https://github.com/llvm/llvm-project/commit/514d0691f4da40d5bb6d618a673e975b8eacfb77
Author: Danny Mösch <danny.moesch at icloud.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/add_new_check.py
Log Message:
-----------
[clang-tidy] Fix warnings caused by "new check" template (#80537)
Commit: 752c172bc7d628fe5ce4a78f3620893b8d7bcfba
https://github.com/llvm/llvm-project/commit/752c172bc7d628fe5ce4a78f3620893b8d7bcfba
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiate.cpp
A clang/test/SemaTemplate/default-parm-init.cpp
Log Message:
-----------
[Clang][Sema] fix outline member function template with default align crash (#80288)
Try to fix [issue](https://github.com/llvm/llvm-project/issues/68490 )
and some extented problem. Root cause of current issue is that error
handling in instantiation of function parameter with default
initialization on sizeof or align expression. When instance an
out-of-line template member function, depth of `TemplateTypeParmDecl` in
default initialization doesn't change while depth of other template
parameter does and this will lead to some template parameter
uninstanced. Also, sometime it will leader to wrong instantiation when
it uses the template parameter of the template class.
Fix it by add template args of context. This will make
MultiLevelTemplateArgumentList::getNumLevels matching the depth of
template parameter. Testcase with some static_assert demonstrates the
template parameter has been instanced correctly.
But, the default initialization of lambda expression compiles failed
when only checking if the member function is out-of-line. We should
check the `PrimaryFunctionTemplateDecl` of the funtion if it's
out-of-line.
Co-authored-by: huqizhi <836744285 at qq.com>
Commit: 248aeac1ad2cf4f583490dd1312a5b448d2bb8cc
https://github.com/llvm/llvm-project/commit/248aeac1ad2cf4f583490dd1312a5b448d2bb8cc
Author: Martin Storsjö <martin at martin.st>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M compiler-rt/lib/builtins/i386/chkstk.S
M compiler-rt/lib/builtins/x86_64/chkstk.S
Log Message:
-----------
[compiler-rt] Remove duplicate MS names for chkstk symbols (#80450)
Prior to 885d7b759b5c166c07c07f4c58c6e0ba110fb0c2, the builtins library
contained two chkstk implementations for each of i386 and x86_64, one
that was used in mingw environments, and one unused (with a symbol name
not matching anything that is used anywhere). Some of the functions
additionally had other, also unused, aliases.
After cleaning this up in 885d7b759b5c166c07c07f4c58c6e0ba110fb0c2, the
unused symbol names were removed.
At the same time, symbol aliases were added for the names as they are
used by MSVC; the functions are functionally equivalent, but have
different names between mingw and MSVC style environments.
By adding a symbol alias (so that one object file contains two different
symbols for the same function), users can run into problems with
duplicate definitions, if they themselves define one of the symbols (for
various reasons), but need to link in the other one.
This happens for Wine, which provides their own definition of
"__chkstk", but when built in mingw mode does need compiler-rt to
provide the mingw specific symbol names; see
https://github.com/mstorsjo/llvm-mingw/issues/397.
To avoid the issue, remove the extra MS style names. They weren't
entirely usable as such for MSVC style environments anyway, as
compiler-rt builtins don't build these object files at all, when built
in MSVC mode; thus, the effort to provide them for MSVC style
environments in 885d7b759b5c166c07c07f4c58c6e0ba110fb0c2 was a
half-hearted step towards that.
If we really do want to provide those functions (as an alternative to
the ones provided by MSVC itself), we should do it in a separate object
file (even if the function implementation is the same), so that users
who have a definition of one of them but need a definition of the other,
won't have conflicts.
Additionally, if we do want to provide them for MSVC, those files
actually should be built when building the builtins in MSVC mode as well
(see compiler-rt/lib/builtins/CMakeLists.txt).
If we do that, there's a risk that an MSVC style build ends up linking
in and preferring our implementation over the one provided by MSVC,
which would be suboptimal. Our implementation always probes the
requested amount of stack, while the MSVC one checks the amount of
allocated stack and only probes as much as really is needed.
In short - this reverts the situation to what it was in the 17.x release
series (except for unused functions that have been removed).
Commit: 2906f3626b54136b885d82d2b28b7991f3d728ae
https://github.com/llvm/llvm-project/commit/2906f3626b54136b885d82d2b28b7991f3d728ae
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Update ::onlyScalarsGenerated to take IsScalable bool (NFCI).
Instead of passing in a full VF, just pass IsScalable as bool.
Commit: 693647902076034e7c81f380d1b937a65aef8ae6
https://github.com/llvm/llvm-project/commit/693647902076034e7c81f380d1b937a65aef8ae6
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Mark vputils::onlyFirstLaneUsed arg as const (NFC)
Split off https://github.com/llvm/llvm-project/pull/80269 as suggested.
Commit: 3444240540b0b36902dc8b9b11339b8969f7bca9
https://github.com/llvm/llvm-project/commit/3444240540b0b36902dc8b9b11339b8969f7bca9
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
Log Message:
-----------
[VPlan] Mark vputils::onlyFirstPartUsed arg as const (NFC)
Split off https://github.com/llvm/llvm-project/pull/80269 as
suggested.
Commit: 47abbf4fe956ad1c12832de03c8ae3294eb5cb78
https://github.com/llvm/llvm-project/commit/47abbf4fe956ad1c12832de03c8ae3294eb5cb78
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
Log Message:
-----------
[VPlan] Update VPInst::onlyFirstLaneUsed to check users. (#80269)
A VPInstruction only has its first lane used if all users use its first
lane only. Use vputils::onlyFirstLaneUsed to continue checking the
recipe's users to handle more cases.
Besides allowing additional introduction of scalar steps when
interleaving in some cases, this also enables using an Add VPInstruction
to model the increment - as a follow up.
Commit: 5ca2777c69f8708d583e230c56ac7f5f6376fb40
https://github.com/llvm/llvm-project/commit/5ca2777c69f8708d583e230c56ac7f5f6376fb40
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M libcxx/include/valarray
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/get.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/and_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/divide_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/minus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/modulo_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/or_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/plus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_left_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_right_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/times_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/xor_valarray.pass.cpp
Log Message:
-----------
[libc++] Fixes valarray proxy type compound assignment operations. (#76528)
The valarray<>::operator[](...) const functions return proxy objects.
The valarray<>::operator[](...) functions return valarray objects.
However the standard allows functions returning valarray objects to
return custom proxy objects instead. Libc++ returns __val_expr proxies.
Functions taking a valarray object must work with the custom proxies
too. Therefore several operations have a custom proxy overload instead
of valarray overloads.
Libc++ doesn't specify a valarray overload. This is an issue with the
standard proxy types; these can implicitly be converted to a valarray.
The solution is to allow the standard proxies to behave as-if they are
custom proxies.
This patch fixes the valarray compound assignments. Other operations,
like the binary non-member functions are not fixed. These will be done
in a followup patch.
Fixes: https://github.com/llvm/llvm-project/issues/21320
Commit: 7189219ec9fc768f159917052b4b5998d077c39f
https://github.com/llvm/llvm-project/commit/7189219ec9fc768f159917052b4b5998d077c39f
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/include/llvm/TextAPI/Utils.h
M llvm/lib/TextAPI/Utils.cpp
A llvm/test/tools/llvm-readtapi/Inputs/libSystem.1.yaml
A llvm/test/tools/llvm-readtapi/stubify-delete.test
A llvm/test/tools/llvm-readtapi/stubify-simple.test
A llvm/test/tools/llvm-readtapi/stubify-symlink.test
R llvm/test/tools/llvm-readtapi/stubify.test
M llvm/tools/llvm-readtapi/TapiOpts.td
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[readtapi] Add support for stubify-ing directories (#76885)
When given a directory input `llvm-readtapi` traverses through the
directory to find dylibs or tbd files to operate on. TBD files will be
created with the same base file name as the dylib. Symlinks should be
created if the input is one.
This also introduces options to delete input files which are defined as
library files that existed before `readtapi -stubify` was invoked. Also
the ability to delete private libraries where private libraries are in a
predefined file system locations on darwin based platforms.
Commit: ab9a69878c7a14b85389c16e130ea117ee4f4358
https://github.com/llvm/llvm-project/commit/ab9a69878c7a14b85389c16e130ea117ee4f4358
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M flang/lib/Parser/preprocessor.cpp
Log Message:
-----------
[flang] Simplify a string comparison (NFC)
Commit: 8926af426f202c158dd17b2034c044e85eceb108
https://github.com/llvm/llvm-project/commit/8926af426f202c158dd17b2034c044e85eceb108
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Support/VirtualFileSystem.cpp
Log Message:
-----------
[Support] Use StringRef::starts_with (NFC)
Commit: 9ad78b0994a2a1d7c28f463a89585a0ffd5310e4
https://github.com/llvm/llvm-project/commit/9ad78b0994a2a1d7c28f463a89585a0ffd5310e4
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
Log Message:
-----------
[Lanai] Use StringRef::consume_back (NFC)
Commit: 06da452ba7d8d4959cb5070727b842eea4c8af71
https://github.com/llvm/llvm-project/commit/06da452ba7d8d4959cb5070727b842eea4c8af71
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Analysis/LoopInfo.cpp
Log Message:
-----------
[Analysis] Use range-based for loops (NFC)
Commit: 0ed02621b9d87342daff0dcd9014319d4eeb2735
https://github.com/llvm/llvm-project/commit/0ed02621b9d87342daff0dcd9014319d4eeb2735
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
A llvm/test/tools/llvm-readtapi/stubify-symlink-darwin.test
R llvm/test/tools/llvm-readtapi/stubify-symlink.test
Log Message:
-----------
[readtapi] make symlink test darwin only
Appeases bots for now.
Commit: 5bcd91058ee4855804780c4ae35ac87ed45a4b58
https://github.com/llvm/llvm-project/commit/5bcd91058ee4855804780c4ae35ac87ed45a4b58
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
Log Message:
-----------
[readtapi] Use ExitOnError instead of errorcodes for `readlink` wrapper
Silences: ` error C4716: 'read_link': must return a value` windows error
Commit: f87e3b61c8b6af896aebf551a03b2387e71dfe73
https://github.com/llvm/llvm-project/commit/f87e3b61c8b6af896aebf551a03b2387e71dfe73
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
M libcxx/include/__locale
A libcxx/include/__locale_dir/locale_base_api.h
A libcxx/include/__locale_dir/locale_base_api/android.h
A libcxx/include/__locale_dir/locale_base_api/fuchsia.h
A libcxx/include/__locale_dir/locale_base_api/ibm.h
A libcxx/include/__locale_dir/locale_base_api/musl.h
A libcxx/include/__locale_dir/locale_base_api/newlib.h
A libcxx/include/__locale_dir/locale_base_api/openbsd.h
A libcxx/include/__locale_dir/locale_base_api/win32.h
R libcxx/include/__support/android/locale_bionic.h
R libcxx/include/__support/fuchsia/xlocale.h
R libcxx/include/__support/ibm/xlocale.h
R libcxx/include/__support/musl/xlocale.h
R libcxx/include/__support/newlib/xlocale.h
R libcxx/include/__support/openbsd/xlocale.h
R libcxx/include/__support/win32/locale_win32.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/src/locale.cpp
Log Message:
-----------
[libc++] Move the locale support headers to __locale_dir/locale_base_api/ (#74522)
Differential Revision: https://reviews.llvm.org/D147869
Commit: b205ea15c1573fd3c55d2356a22a9068c55c8065
https://github.com/llvm/llvm-project/commit/b205ea15c1573fd3c55d2356a22a9068c55c8065
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port f87e3b61c8b6
Commit: de4360d7d535ffff9e655fdb40657cf95871ec6c
https://github.com/llvm/llvm-project/commit/de4360d7d535ffff9e655fdb40657cf95871ec6c
Author: David Green <david.green at arm.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] Add extra scalable typesize and offset tests. NFC
A collection of tests from #69152 and for constant offsets with scalable typesizes.
Commit: d62c5706a8fabca8b14484ce5078b03756f8a37b
https://github.com/llvm/llvm-project/commit/d62c5706a8fabca8b14484ce5078b03756f8a37b
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Custom legalize i32 SMULO with RV64LegalI32.
The default lowering will use shifts to make use of an i32 setcc.
We don't support i32 setcc, so its better to sig extend the low
32 bits and compare the full 64 bit result. This gives produces
mul+mulw+xor+snez like we do without RV64LegalI32.
Commit: f09092434423be14f32781d8ae263dc041d24551
https://github.com/llvm/llvm-project/commit/f09092434423be14f32781d8ae263dc041d24551
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Custom legalize i32 SADDO/SSUBO with RV64LegaI32.
The default legalization uses 2 compares and an xor. We can instead
use add+addw+xor+snez like we do without RV64LegaI32.
Commit: ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44
https://github.com/llvm/llvm-project/commit/ea59b15cf70b53f6a4f3ba0d495d0566a0e77e44
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Add more RUN lines to rv64-legal-i32/xaluo.ll. NFC
This matches the non-rv64-legal-i32 version.
Commit: 9d00c3413299f537748e448e7197d6942c4651ea
https://github.com/llvm/llvm-project/commit/9d00c3413299f537748e448e7197d6942c4651ea
Author: David Green <david.green at arm.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/neon-mov.ll
Log Message:
-----------
[AArch64] Extend and cleanup movi tests. NFC
Commit: 2333865546cb6d4cda7b511ed07b8cb66a0d4eab
https://github.com/llvm/llvm-project/commit/2333865546cb6d4cda7b511ed07b8cb66a0d4eab
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M openmp/libomptarget/include/device.h
M openmp/libomptarget/src/omptarget.cpp
M openmp/libomptarget/test/offloading/dynamic_module_load.c
Log Message:
-----------
[Libomptarget] Fix data mapping on dynamic loads (#80559)
Summary:
The current logic tries to map target mapping tables to the current
device. Right now it assumes that data is only mapped a single time per
device. This is only true if we have a single instance of the runtime
running on a single program. However, in the case of dynamic library
loads or shared libraries, this may happen multiple times.
Given a case of a simple dynamic library load which has its own target
kernel instruction, the current logic had only the first call to
`__tgt_target_kernel` to the data mapping for that device. Then, when
the next dynamic library load got called, it would see that the global
were already mapped for that device and skip registering its own
entires, even though they were distinct. This resulted in none of the
mappings being done and hitting an assertion.
This patch simply gets rid of this per-device check. The check should
instead be on the host offloading entries. We already have logic that
calls `continue` if we already have entries for that pointer, so we can
simply rely on that instead.
Commit: 08e942aca64d4d16e55a25d7e7eda8ef192727fd
https://github.com/llvm/llvm-project/commit/08e942aca64d4d16e55a25d7e7eda8ef192727fd
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll
Log Message:
-----------
[RISCV] Combine (xor (trunc (X cc Y)) 1) -> (trunc (X !cc Y)) for RV64LegalI32.
This is needed with RV64LegalI32 when the setcc is created after type
legalization. An i1 xor would have been promoted to i32, but the setcc
would have i64 result.
Commit: 390b99743bdd60649414fe470d7a9bacc9992231
https://github.com/llvm/llvm-project/commit/390b99743bdd60649414fe470d7a9bacc9992231
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
A llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
Log Message:
-----------
[InstCombine] Handle isNanOrInf idioms (#80414)
This patch folds:
```
(icmp eq (and (bitcast X to int), ExponentMask), ExponentMask) --> llvm.is.fpclass(X, fcInf|fcNan)
(icmp ne (and (bitcast X to int), ExponentMask), ExponentMask) --> llvm.is.fpclass(X, ~(fcInf|fcNan))
```
Alive2: https://alive2.llvm.org/ce/z/_hXAAF
Commit: 4e112e5c1c8511056030294af3264da35f95d93c
https://github.com/llvm/llvm-project/commit/4e112e5c1c8511056030294af3264da35f95d93c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
A libcxx/test/std/containers/sequences/vector/vector.modifiers/destory_elements.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
Reapply "[libc++] Optimize vector growing of trivially relocatable types" (#80558)
This reapplies #76657. Non-trivial elements didn't get destroyed
previously. This fixes the bug and adds tests for all the vector
insertion functions.
Commit: 6ad692b7b3416f632e1d38cef3cc83f618f428b0
https://github.com/llvm/llvm-project/commit/6ad692b7b3416f632e1d38cef3cc83f618f428b0
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 4e112e5c1c85
Commit: 61ff9f8db8d18002767ea27f83a4bfb8ed47f255
https://github.com/llvm/llvm-project/commit/61ff9f8db8d18002767ea27f83a4bfb8ed47f255
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
Log Message:
-----------
[X86] Add strictfp version of PR43024 test. (#80573)
For the current version of the PR43024 test, we should be able to
optimize away the operations but fail to do so. This commit adds a
strictfp version of the test where we should not be able to optimize
away the operations, as a verification that changes to improve the other
effect have no adverse effect.
Commit: 1da2921bbdff847eb57184f3d5e7ae5c363b9e88
https://github.com/llvm/llvm-project/commit/1da2921bbdff847eb57184f3d5e7ae5c363b9e88
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Add missing extload test cases to xtheadmemidx.ll. NFC
We had the isel patterns, but no tests that used them. We only had
sextload and zextload tests.
Also reduce the alignment on some of the test cases that were
unnecessarily over aligned.
Commit: f2cf8da636ee2b27b54f14fea540d7ef75cebc05
https://github.com/llvm/llvm-project/commit/f2cf8da636ee2b27b54f14fea540d7ef75cebc05
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmemidx.ll
Log Message:
-----------
[RISCV] Add more XTheadMemIdx patterns for -riscv-experimental-rv64-legal-i32.
Commit: a3d8b78333b80b47209ad0dc8f8159d70c7fcb39
https://github.com/llvm/llvm-project/commit/a3d8b78333b80b47209ad0dc8f8159d70c7fcb39
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenCXX/dynamic-cast-dead.cpp
M clang/test/CodeGenCXX/dynamic-cast.cpp
Log Message:
-----------
[Clang][CodeGen] Mark `__dynamic_cast` as `willreturn` (#80409)
According to the C++ standard, `dynamic_cast` of pointers either returns
a pointer (7.6.1.7) or results in undefined behavior (11.9.5). This
patch marks `__dynamic_cast` as `willreturn` to remove unused calls.
Fixes #77606.
Commit: 9dfdea6fbddfa871dab32c3322259babcc13dcdc
https://github.com/llvm/llvm-project/commit/9dfdea6fbddfa871dab32c3322259babcc13dcdc
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmac.ll
Log Message:
-----------
[RISCV] Add XTheadMac patterns for -riscv-experimental-rv64-legal-i32.
Commit: b0f0babff22e9c0af74535b05e2c6424392bb24a
https://github.com/llvm/llvm-project/commit/b0f0babff22e9c0af74535b05e2c6424392bb24a
Author: Koakuma <koachan at protonmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/sparc64-codemodel.c
Log Message:
-----------
[clang] Add GCC-compatible code model names for sparc64
This adds GCC-compatible names for code model selection on 64-bit SPARC
with absolute code.
Testing with a 2-stage build then running codegen tests works okay under
all of the supported code models.
(32-bit target does not have selectable code models)
Reviewed By: @brad0, @MaskRay
Commit: b4eb7a10c01162b17cb5dc94a97d9d137bb6fe57
https://github.com/llvm/llvm-project/commit/b4eb7a10c01162b17cb5dc94a97d9d137bb6fe57
Author: Serge Pavlov <sepavloff at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
A llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
Log Message:
-----------
[GlobalISel][ARM] Legalze set_fpenv and get_fpenv (#79852)
Implement handling of get/set floating point environment for ARM in
Global Instruction Selector. Lowering of these intrinsics to operations
on FPSCR was previously inplemented in DAG selector, in GlobalISel it is
reused.
Commit: d25022bb689b9bf48a24c0ae6c29c1d3c2f32823
https://github.com/llvm/llvm-project/commit/d25022bb689b9bf48a24c0ae6c29c1d3c2f32823
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[workflows] Stop using the build-test-llvm-project action (#80580)
This action is really just a wrapper around cmake and ninja. It doesn't
add any value to the builds, and I don't think we need it now that there
are reusable workflows.
Commit: 2193c95e2459887e7e6e4f9f4aacf9252e99858f
https://github.com/llvm/llvm-project/commit/2193c95e2459887e7e6e4f9f4aacf9252e99858f
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[workflows] Only run code formatter on the main branch (#80348)
Modifying a cherry-picked patch to fix code formatting issues can be
risky, so we don't typically do this. Therefore, it's not necessary to
run this job on the release branches.
Commit: 7d269a484142459a1154ba81c68bf0c31f291fc8
https://github.com/llvm/llvm-project/commit/7d269a484142459a1154ba81c68bf0c31f291fc8
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
Log Message:
-----------
[CodeGen] Use range-based for loops (NFC)
Commit: 3be989e8c30f3cad61e5e1fa54199fc45edf7ff7
https://github.com/llvm/llvm-project/commit/3be989e8c30f3cad61e5e1fa54199fc45edf7ff7
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
Log Message:
-----------
[FileCheck] Use StringRef::rtrim (NFC)
Commit: 3c93c037c9ede2eaa0bdea6924c92d646ca0cfe5
https://github.com/llvm/llvm-project/commit/3c93c037c9ede2eaa0bdea6924c92d646ca0cfe5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
Log Message:
-----------
[Basic] Use StringRef::ends_with (NFC)
Commit: 34fba4fb1e32f06237e5024373cc0163cecc3fd5
https://github.com/llvm/llvm-project/commit/34fba4fb1e32f06237e5024373cc0163cecc3fd5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M clang/lib/Basic/Sarif.cpp
Log Message:
-----------
[Basic] Use StringRef::contains (NFC)
Commit: a37e8b85ee5187bc7a1fed7adce8ed5693215795
https://github.com/llvm/llvm-project/commit/a37e8b85ee5187bc7a1fed7adce8ed5693215795
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
Log Message:
-----------
[ExecutionEngine] Simplify a string comparison (NFC)
Commit: 1b33b3f27f8bf3902d754ed83da29f9a6f15e4e1
https://github.com/llvm/llvm-project/commit/1b33b3f27f8bf3902d754ed83da29f9a6f15e4e1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
Log Message:
-----------
[MIRParser] Simplify a string comparison (NFC)
Commit: 9d2e8dca12c8bbb70223eeb74330fe603e215ce3
https://github.com/llvm/llvm-project/commit/9d2e8dca12c8bbb70223eeb74330fe603e215ce3
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/test/MC/WebAssembly/tables.s
M llvm/test/MC/WebAssembly/type-checker-errors.s
Log Message:
-----------
[WebAssembly] fix `table.grow` type checker (#80572)
table.grow is valid with type `[t i32] -> [i32]`.
Fixes: #79966.
Commit: 3bcb1f2bdd5c70b2ac4aff3290996486d9ae0236
https://github.com/llvm/llvm-project/commit/3bcb1f2bdd5c70b2ac4aff3290996486d9ae0236
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV] Rework isSignExtendingOpW to store Register in the worklist.
Previously we stored MachineInstr which restricted the implementation
to only handle operand 0.
The TH_LWD instruction has two sign extended destinations.
Commit: bc9c2be3577c58d3daabff995360bd9bea44b0b9
https://github.com/llvm/llvm-project/commit/bc9c2be3577c58d3daabff995360bd9bea44b0b9
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/minmax.ll
Log Message:
-----------
[ConstraintElim] Simplify `MinMaxIntrinsic` (#75306)
This patch replaces min/max intrinsic with one of its operands if
possible.
Alive2: https://alive2.llvm.org/ce/z/LoHfYf
Fixes #75155.
Commit: 72105605d1fbc816c1219bb1d719693291322011
https://github.com/llvm/llvm-project/commit/72105605d1fbc816c1219bb1d719693291322011
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/test/CodeGen/target-builtin-noerror.c
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Support more ISAs to enable __builtin_cpu_supports (#79086)
This patch will also expand supports for attribute/target, while
the priority of newly supported ISAs will be set to zero.
Commit: d71ef3e75c6325f0c10c19ee34e2c0337a0fd452
https://github.com/llvm/llvm-project/commit/d71ef3e75c6325f0c10c19ee34e2c0337a0fd452
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Merge identical setOperationAction calls. NFC.
Commit: 114a33be4751328c549c6b8b05e9ece19e452189
https://github.com/llvm/llvm-project/commit/114a33be4751328c549c6b8b05e9ece19e452189
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
Log Message:
-----------
[DAG] getStackAlignedMMO - return the getMachineMemOperand result directly (style). NFC.
Commit: dea855de46bd4d3e103646a7f459856d88dd7488
https://github.com/llvm/llvm-project/commit/dea855de46bd4d3e103646a7f459856d88dd7488
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M mlir/include/mlir/Conversion/SCFToEmitC/SCFToEmitC.h
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
Log Message:
-----------
[mlir][EmitC] Drop unused code (NFC) (#80325)
To register the conversion the autogenerated function
`registerSCFToEmitC()` calls `createSCFToEmitC()`, which itself is also
autogenerated. The removed function, however, isn't used in the upstream
codebase.
Commit: 859b09da08c2a47026ba0a7d2f21b7dca705864d
https://github.com/llvm/llvm-project/commit/859b09da08c2a47026ba0a7d2f21b7dca705864d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rv64-legal-i32/vararg.ll
Log Message:
-----------
[RISCV] Promote i32 ISD::VAARG to i64 for -riscv-experimental-rv64-legal-i32.
Commit: 9ff83f12fe406f9c3c6b2cd0ee96660a7485f29f
https://github.com/llvm/llvm-project/commit/9ff83f12fe406f9c3c6b2cd0ee96660a7485f29f
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M lldb/include/lldb/DataFormatters/FormatCache.h
M lldb/source/DataFormatters/FormatCache.cpp
Log Message:
-----------
[lldb] Remove unnecessary FormatCache::GetEntry (NFC) (#80603)
The implementation of `FormatCache::Entry
&FormatCache::GetEntry(ConstString)` is effectively a duplication of
`std::map::operator[]`. This change deletes `GetEntry` and replaces its
use with `operator[]`.
Commit: 256200732111afd03bb7437564f3a3d77c0ec3f5
https://github.com/llvm/llvm-project/commit/256200732111afd03bb7437564f3a3d77c0ec3f5
Author: rmarker <37921131+rmarker at users.noreply.github.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/docs/ClangFormatStyleOptions.rst
M clang/include/clang/Format/Format.h
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
Log Message:
-----------
[clang-format] Add Automatic and ExceptShortType options for AlwaysBreakAfterReturnType. (#78011)
The RTBS_None option in Clang-format avoids breaking after a short
return type.
However, there was an issue with the behaviour in that it wouldn't take
the leading indentation of the line into account.
This meant that the behaviour wasn't applying when intended.
In order to address this situation without breaking the existing
formatting, RTBS_None has been deprecated.
In its place are two new options for AlwaysBreakAfterReturnType.
The option RTBS_Automatic will break after the return type based on
PenaltyReturnTypeOnItsOwnLine.
The option RTBS_ExceptShortType will take the leading indentation into
account and prevent breaking after short return types.
This allows the inconsistent behaviour of RTBS_None to be avoided and
users to decide whether they want to allow breaking after short return
types or not.
Resolves #78010
Commit: 32b99617acbc4773caee45df10a7fd602b8db0ff
https://github.com/llvm/llvm-project/commit/32b99617acbc4773caee45df10a7fd602b8db0ff
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
Log Message:
-----------
[RISCV] Custom promote i32 UADDSAT/USUBSAT for -riscv-experimental-rv64-legal-i32 with Zbb.
Commit: 146e5ce481f3a9232f2188cc664a65e98f8a0985
https://github.com/llvm/llvm-project/commit/146e5ce481f3a9232f2188cc664a65e98f8a0985
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/test/CodeGen/RISCV/rv64-legal-i32/rv64zbb.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/uadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/usub_sat_plus.ll
Log Message:
-----------
[RISCV] Add i32 zext.h pattern for -riscv-experimental-rv64-legal-i32.
Commit: ae36790be4a2a6c9dc8900f659c861647cab66d5
https://github.com/llvm/llvm-project/commit/ae36790be4a2a6c9dc8900f659c861647cab66d5
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.proftext
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.proftext
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.proftext
M llvm/test/tools/llvm-cov/mcdc-const.test
M llvm/test/tools/llvm-cov/mcdc-general-none.test
M llvm/test/tools/llvm-cov/mcdc-general.test
Log Message:
-----------
test/llvm-cov: Regenerate MC/DC tests (#80610)
* Revise instructions for regeneration, not to create executables.
* Add instructions to regenerate both object files and test vectors
(except for `mcdc-general-none.proftext`)
* Reformat
Commit: dcb83692cdeaf7fb620fd14992848b6cbc94f773
https://github.com/llvm/llvm-project/commit/dcb83692cdeaf7fb620fd14992848b6cbc94f773
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
Log Message:
-----------
[Bitcode] Use range-based for loops (NFC)
Commit: 90e9c6e36e8b928240dfd61c2dfd30cf26108c07
https://github.com/llvm/llvm-project/commit/90e9c6e36e8b928240dfd61c2dfd30cf26108c07
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Object/COFFModuleDefinition.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/Support/FormatVariadic.cpp
Log Message:
-----------
[llvm] Use StringRef::consume_front (NFC)
Commit: ffaedc2735cfcf2595fe65a75ed910a9c661391b
https://github.com/llvm/llvm-project/commit/ffaedc2735cfcf2595fe65a75ed910a9c661391b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
Log Message:
-----------
[Basic] Simplify uses of StringRef::consume_front (NFC)
Commit: e7d3a4f34adbe9ea183c2ec4aea97691d4ec06f5
https://github.com/llvm/llvm-project/commit/e7d3a4f34adbe9ea183c2ec4aea97691d4ec06f5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/FileCheck/FileCheck.cpp
Log Message:
-----------
[FileCheck] Simplify a use of StringRef::consume_front (NFC)
Commit: 92d5f644281cba56baa9b42dfc298db7f2c30003
https://github.com/llvm/llvm-project/commit/92d5f644281cba56baa9b42dfc298db7f2c30003
Author: Kazu Hirata <kazu at google.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
Log Message:
-----------
[clang-tidy] Use StringRef::contains (NFC)
Commit: f72da9f4fd389951c4d65055f5471e208f256212
https://github.com/llvm/llvm-project/commit/f72da9f4fd389951c4d65055f5471e208f256212
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
Log Message:
-----------
[SelectionDAG] Use getShiftAmountConstant to simplify code. NFC (#80561)
Replace calls to getShiftAmountTy+getConstant with
getShiftAmountContant.
Commit: 6590d0fed5180a403c32c991baed56f9d39e045a
https://github.com/llvm/llvm-project/commit/6590d0fed5180a403c32c991baed56f9d39e045a
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/test/CodeGen/ARM/shift-combine.ll
M llvm/test/CodeGen/X86/h-registers-2.ll
Log Message:
-----------
[DAGCombiner][ARM] Teach reduceLoadWidth to handle (and (srl (load), C, ShiftedMask)) (#80342)
If we have a shifted mask, we may be able to reduce the load width
to the width of the non-zero part of the mask and use an offset
to the base address to remove the srl. The offset is given by
C+trailingzeros(ShiftedMask).
Then we add a final shl to restore the trailing zero bits.
I've use the ARM test because that's where the existing (and (srl
(load))) tests were.
The X86 test was modified to keep the H register.
Commit: 34c4a0fa2b9c2181bfdbd3009e7956a50a28dab6
https://github.com/llvm/llvm-project/commit/34c4a0fa2b9c2181bfdbd3009e7956a50a28dab6
Author: ZijunZhaoCCK <88353225+ZijunZhaoCCK at users.noreply.github.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-char.cpp
M clang/lib/Driver/Driver.cpp
M clang/test/CodeGen/fp128_complex.c
M clang/test/Driver/mips-features.c
M clang/test/Frontend/fixed_point_bit_widths.c
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
Log Message:
-----------
[Driver] Report invalid target triple versions for all environment types. (#78655)
Followup for https://github.com/llvm/llvm-project/pull/75373
1. Make this feature not just available for android, but everyone.
2. Correct some target triples.
3. Add opencl to the environment type list.
Commit: b53169dfec89d89b292c550d6f6dec3ed6a61ba5
https://github.com/llvm/llvm-project/commit/b53169dfec89d89b292c550d6f6dec3ed6a61ba5
Author: Sheng <ox59616e at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/AffineMap.h
Log Message:
-----------
[NFC][mlir] Fix Typo.
Commit: 067882cfe970a4ad7fef1432f5fa24fa33150d25
https://github.com/llvm/llvm-project/commit/067882cfe970a4ad7fef1432f5fa24fa33150d25
Author: Anton Korobeynikov <anton at korobeynikov.info>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
A .github/workflows/email-check.yaml
Log Message:
-----------
Add github workflow that checks if a private email address was used to contribute to the repo and warn in this case (#80514)
Following the Discourse discussion, warn in case of a private email address was used in a PR.
Commit: 4926f12ff53fd4e67ac08b7355aeffed15584088
https://github.com/llvm/llvm-project/commit/4926f12ff53fd4e67ac08b7355aeffed15584088
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
[Coverage] ProfileData: Handle MC/DC Bitmap as BitVector. NFC. (#80608)
* `getFunctionBitmap()` stores not `std::vector<uint8_t>` but
`BitVector`.
* `CounterMappingContext` holds `Bitmap` (instead of the ref of bytes)
* `Bitmap` and `BitmapIdx` are used instead of `evaluateBitmap()`.
FIXME: `InstrProfRecord` itself should handle `Bitmap` as `BitVector`.
Commit: 115c0c6513d538ace464887414d1d8f1da7d7208
https://github.com/llvm/llvm-project/commit/115c0c6513d538ace464887414d1d8f1da7d7208
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrAVX512.td
A llvm/test/CodeGen/X86/fold-broadcast.ll
Log Message:
-----------
[X86][test] Remove useless pattern for VDPBF16PSZmb and add a test for broadcast folding (#80629)
llvm-issue: https://github.com/llvm/llvm-project/issues/68810
Commit: db060ab0531dd7d8fce9003c0047fb51ec7e4b5d
https://github.com/llvm/llvm-project/commit/db060ab0531dd7d8fce9003c0047fb51ec7e4b5d
Author: Chia <sun1011jacobi at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vwsub-mask.ll
A llvm/test/CodeGen/RISCV/rvv/vwsub-mask-sdnode.ll
Log Message:
-----------
[RISCV][ISel] Remove redundant vmerge for vwsub(u).wv. (#80523)
Commit: 4b34558f43121df9b863ff2492f74fb2e65a5af1
https://github.com/llvm/llvm-project/commit/4b34558f43121df9b863ff2492f74fb2e65a5af1
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M .github/workflows/pr-code-format.yml
Log Message:
-----------
[Github] Fix triggers formatting in code format action
A recent comment modified the job to only run on the main branch, but
the formatting was slightly off, causing the job to not run. This patch
fixes the formatting so the job will run as expected.
Commit: 5afeba051e5c3ad1860cf1642a99e60452d514de
https://github.com/llvm/llvm-project/commit/5afeba051e5c3ad1860cf1642a99e60452d514de
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
A llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/sadd_sat_plus.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat.ll
A llvm/test/CodeGen/RISCV/rv64-legal-i32/ssub_sat_plus.ll
Log Message:
-----------
[RISCV] Custom legalize i32 UADDSAT/USUBSAT for -riscv-experimental-rv64-legal-i32 with Zbb.
This matches the codegen we get from type legalization without
-riscv-experimental-rv64-legal-i32.
Commit: a9670fb0de1cb87fb1556e8cf28d528171f5bd9b
https://github.com/llvm/llvm-project/commit/a9670fb0de1cb87fb1556e8cf28d528171f5bd9b
Author: Kai Luo <lkail at cn.ibm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Fix assertion of InstDisp for local-exec TLS. NFC.
Fixes https://github.com/llvm/llvm-project/issues/80557.
Commit: f035c018a6a581c38680651d4856631d9c6ccb0a
https://github.com/llvm/llvm-project/commit/f035c018a6a581c38680651d4856631d9c6ccb0a
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProfReader.cpp
Log Message:
-----------
InstrProf::getFunctionBitmap: Fix BE hosts (#80608)
Commit: ae5ed2a5d873e1785f06bd74cb583a4e88604317
https://github.com/llvm/llvm-project/commit/ae5ed2a5d873e1785f06bd74cb583a4e88604317
Author: Brandon Wu <brandon.wu at sifive.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/Sema/SemaRISCVVectorLookup.cpp
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
M clang/test/Sema/rvv-required-features-invalid.c
M clang/utils/TableGen/RISCVVEmitter.cpp
Log Message:
-----------
[RISCV][clang] Add Zvfbfwma C intrinsics support (#79615)
Commit: 8ed046fc15eae08a9cf7ec02974330d52606c663
https://github.com/llvm/llvm-project/commit/8ed046fc15eae08a9cf7ec02974330d52606c663
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-04 (Sun, 04 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/sadd_sat.ll
M llvm/test/CodeGen/RISCV/sadd_sat_plus.ll
M llvm/test/CodeGen/RISCV/ssub_sat.ll
M llvm/test/CodeGen/RISCV/ssub_sat_plus.ll
Log Message:
-----------
[RISCV] Custom type legalize i32 SADDSAT/SSUBSAT without Zbb.
While working on -riscv-experimental-rv64-legal-i32, I noticed this
missed optimization in our current codegen.
This expands to SADDO/SSUBO+select while still in i32. These will
be type legalized individually.
Commit: 500846d2f542c93e349161a39a1baae0f1f6fad0
https://github.com/llvm/llvm-project/commit/500846d2f542c93e349161a39a1baae0f1f6fad0
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/CodeGenCUDA/amdgpu-code-object-version-linking.cu
M clang/test/CodeGenCUDA/amdgpu-code-object-version.cu
M clang/test/CodeGenCUDA/amdgpu-workgroup-size.cu
A clang/test/Driver/Inputs/rocm/amdgcn/bitcode/oclc_abi_version_600.bc
M clang/test/Driver/hip-code-object-version.hip
M clang/test/Driver/hip-device-libs.hip
M clang/test/Misc/warning-flags.c
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/test/Lower/AMD/code-object-version.f90
M lld/ELF/Arch/AMDGPU.cpp
M lld/test/ELF/amdgpu-tid.s
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/Support/AMDGPUMetadata.h
M llvm/include/llvm/Support/ScopedPrinter.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.s
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.test
R llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[AMDGPU] Introduce Code Object V6 (#76954)
Introduce Code Object V6 in Clang, LLD, Flang and LLVM. This is the same
as V5 except a new "generic version" flag can be present in EFLAGS. This
is related to new generic targets that'll be added in a follow-up patch.
It's also likely V6 will have new changes (possibly new metadata
entries) added later.
Docs change are part of the follow-up patch #76955
Commit: 6e3e8856d442295d8912d8e0c87f6018b4553972
https://github.com/llvm/llvm-project/commit/6e3e8856d442295d8912d8e0c87f6018b4553972
Author: Dani <DanielKristofKiss at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenModule.cpp
Log Message:
-----------
[NFC][Clang] Replace Arch with Triplet. (#80465)
Commit: 0f8680b9d87fa9e8839bd8e39ce605d64148ace6
https://github.com/llvm/llvm-project/commit/0f8680b9d87fa9e8839bd8e39ce605d64148ace6
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.s
Log Message:
-----------
[llvm-readobj] Require AMDGPU target for generic_version.s
Commit: cfa0833ccc7450a322e709583e894e4c96ce682e
https://github.com/llvm/llvm-project/commit/cfa0833ccc7450a322e709583e894e4c96ce682e
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
A llvm/utils/TableGen/GlobalISel/CombinerUtils.cpp
M llvm/utils/TableGen/GlobalISel/CombinerUtils.h
A llvm/utils/TableGen/GlobalISel/PatternParser.cpp
A llvm/utils/TableGen/GlobalISel/PatternParser.h
M llvm/utils/TableGen/GlobalISel/Patterns.cpp
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
[NFC][TableGen][GlobalISel] Move MIR Pattern Parsing out of Combiner Impl (#80257)
This just moves code around so the MIR pattern parsing logic is
separated and reusable.
Commit: a73baf620b8374805b7e927cc79cc157a30e0ac8
https://github.com/llvm/llvm-project/commit/a73baf620b8374805b7e927cc79cc157a30e0ac8
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/Analysis/ReachableCode.cpp
A clang/test/SemaCXX/coroutine-unreachable-warning.cpp
Log Message:
-----------
[coroutine] Suppress unreachable-code warning on coroutine statements. (#77454)
This fixes #69219.
Consider an example:
```
CoTask my_coroutine() {
std::abort();
co_return 1; // unreachable code warning.
}
```
Clang emits a CFG-based unreachable warning on the `co_return` statement
(precisely the `1` subexpr). If we remove this statement, the program
semantic is changed (my_coroutine is not a coroutine anymore).
This patch fixes this issue by never considering coroutine statements as
dead statements.
Commit: ab460797f3af80bd262648d4dd306ef751d4e0f6
https://github.com/llvm/llvm-project/commit/ab460797f3af80bd262648d4dd306ef751d4e0f6
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
[TableGen] Trying fix for PatternParser linker error
There is an implicit dependency here and we can't call CodeGenIntrinsics.cpp functions from PatternParser.cpp reliably, so some build bots were failing.
Try to add LLVMTableGenCommon to the list of source files to see if it fixes it, if it doesn't , I'll revert.
Commit: 0a888fade2600dce737bc356a158e44c8f59b616
https://github.com/llvm/llvm-project/commit/0a888fade2600dce737bc356a158e44c8f59b616
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
Log Message:
-----------
[clangd] Handle IndirectFieldDecl in kindForDecl (#80588)
Fixes https://github.com/clangd/clangd/issues/1925
Commit: d11c912f42113764074cf3c8f0aae49f2d288303
https://github.com/llvm/llvm-project/commit/d11c912f42113764074cf3c8f0aae49f2d288303
Author: David Green <david.green at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/ssub_sat.ll
M llvm/test/CodeGen/AArch64/ssub_sat_plus.ll
M llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
M llvm/test/CodeGen/AArch64/uadd_sat.ll
M llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/usub_sat.ll
M llvm/test/CodeGen/AArch64/usub_sat_plus.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
Log Message:
-----------
[AArch64][GlobalISel] Addition GISel testing for u/s add_sat and sub_sat. NFC
Commit: 722db781d090fc2fd636c299e5f75a0b72c22372
https://github.com/llvm/llvm-project/commit/722db781d090fc2fd636c299e5f75a0b72c22372
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
[TableGen] Exclude LLVMTableGenGlobalISel from "all"
Commit: 991d04d7213bf2747583413ac9b98c7163cf679d
https://github.com/llvm/llvm-project/commit/991d04d7213bf2747583413ac9b98c7163cf679d
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
R llvm/utils/TableGen/GlobalISel/CombinerUtils.cpp
M llvm/utils/TableGen/GlobalISel/CombinerUtils.h
R llvm/utils/TableGen/GlobalISel/PatternParser.cpp
R llvm/utils/TableGen/GlobalISel/PatternParser.h
M llvm/utils/TableGen/GlobalISel/Patterns.cpp
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
Log Message:
-----------
Revert "[NFC][TableGen][GlobalISel] Move MIR Pattern Parsing out of Combiner Impl (#80257)"
This reverts commit cfa0833ccc7450a322e709583e894e4c96ce682e.
Commit: d2b0e23247832c472fe9a96a6bb5784addc92de5
https://github.com/llvm/llvm-project/commit/d2b0e23247832c472fe9a96a6bb5784addc92de5
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
Revert "[TableGen] Trying fix for PatternParser linker error"
This reverts commit ab460797f3af80bd262648d4dd306ef751d4e0f6.
Commit: 6deb7cfd74cacda4b460a7f8e1e7a1be012b1b9e
https://github.com/llvm/llvm-project/commit/6deb7cfd74cacda4b460a7f8e1e7a1be012b1b9e
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/TableGen/GlobalISel/CMakeLists.txt
Log Message:
-----------
Revert "[TableGen] Exclude LLVMTableGenGlobalISel from "all""
This reverts commit 722db781d090fc2fd636c299e5f75a0b72c22372.
Commit: 7d2b6f0b355bc98bbe3aa5bae83316a708da33ee
https://github.com/llvm/llvm-project/commit/7d2b6f0b355bc98bbe3aa5bae83316a708da33ee
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/test/Transforms/IndVarSimplify/pr55925.ll
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[IndVarSimplify] Fix poison-safety when reusing instructions (#80458)
IndVars may replace an instruction with one of its operands, if they
have the same SCEV expression. However, such a replacement may be more
poisonous.
First, check whether the operand being poison implies that the
instruction is also poison, in which case the replacement is always
safe. If this fails, check whether SCEV can determine that reusing the
instruction is safe, using the same check as SCEVExpander.
Fixes https://github.com/llvm/llvm-project/issues/79861.
Commit: 0a45d172d3229074d414e1942d6bafa2b4ae9126
https://github.com/llvm/llvm-project/commit/0a45d172d3229074d414e1942d6bafa2b4ae9126
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Lower/PFTBuilder.h
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/nullify-polymorphic.f90
Log Message:
-----------
[flang] Do not instantiate runtime info globals in functions (#80447)
Runtime globals are compiler generated globals injected in user scopes.
They are never referred to directly in lowering code, we only need th
fur.global for them. Yet lowering was creating hlfir.declare for them in
module procedures. In modern fortran apps, this blows up the generated
IR for nothing (Types with dozens of components, type bound procedures
and parents can create in the order of 10 000 runtime info globals to
describe them, if there is a 100 module procedure, that is that is a few
million operations generated and processed in each pass for nothing).
Commit: d91bb2fcd35e6fc8fe325d5da035295e34b146ca
https://github.com/llvm/llvm-project/commit/d91bb2fcd35e6fc8fe325d5da035295e34b146ca
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
M llvm/test/Assembler/incomplete-ir-declarations.ll
Log Message:
-----------
[AsmParser] Check whether use is callee when determining function type
The code ended up treating a use in a call argument as if it were
a call. Make sure this is actually the callee use.
Commit: 25ab2fc06b6780335c291fa1fc23c2aec01c34a6
https://github.com/llvm/llvm-project/commit/25ab2fc06b6780335c291fa1fc23c2aec01c34a6
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
Log Message:
-----------
[libc][NFC] Make FPRep more testable (#80453)
Commit: f33a0a483550e3441aae4059d6b3d81eab6a398c
https://github.com/llvm/llvm-project/commit/f33a0a483550e3441aae4059d6b3d81eab6a398c
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/NVGPU/tmaload-transform.mlir
Log Message:
-----------
[mlir][nvgpu] Improve `tensormap.descriptor` Type Verifier (#77904)
This PR improves the verifier for the `nvgpu.tensormap.descriptor` type.
The descriptor contains information for TMA, and the compile-time check
ensures its restrictions, such as the last memory dimension being
128-byte. This prevents runtime crashes.
See cuda driver for more explanation:
https://docs.nvidia.com/cuda/cuda-driver-api/group__CUDA__TENSOR__MEMORY.html#group__CUDA__TENSOR__MEMORY_1ga7c7d2aaac9e49294304e755e6f341d7
Commit: 3e230bb6e1a2668e920ee496121e5e40baeb4552
https://github.com/llvm/llvm-project/commit/3e230bb6e1a2668e920ee496121e5e40baeb4552
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
Log Message:
-----------
[CodeGen] Return ArrayRef from TargetRegisterClass::getRegisters. NFCI. (#80411)
This will allow future patches to use indexing and methods like
drop_front on the result.
Commit: 95403b42da0de500f4f86add7a60b0daf8ec98d0
https://github.com/llvm/llvm-project/commit/95403b42da0de500f4f86add7a60b0daf8ec98d0
Author: Dmitry Polukhin <34227995+dmpolukhin at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.yaml
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.yaml
A clang-tools-extra/test/clang-apply-replacements/format-header.cpp
Log Message:
-----------
Apply format only if --format is specified (#79466)
clang-apply-replacements used to apply format even without --format is
specified. This because, methods like createReplacementsForHeaders only
takes the Spec.Style and would re-order the headers even when it was not
requested. The fix is to set up Spec.Style only if --format is provided.
Also added note to ReleaseNotes.rst
Based on https://github.com/llvm/llvm-project/pull/70801
---------
Co-authored-by: Kugan <34810920+kuganv at users.noreply.github.com>
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: b05ba231bf79c43ac7914920b893511b5e362eb2
https://github.com/llvm/llvm-project/commit/b05ba231bf79c43ac7914920b893511b5e362eb2
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Add `next_toward_inf` fo `FPBits` (#80654)
It is needed to provide correct rounding when building FPRep from
greater precision representations.
Commit: 04c1cce33cc9a3f78898a86567459481f02068bb
https://github.com/llvm/llvm-project/commit/04c1cce33cc9a3f78898a86567459481f02068bb
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
Log Message:
-----------
[docs][RISCV] Remove Zicond from release notes now it was backported
Zicond's graduation to non-experimental was backported to 18.x in #80018,
so remove the release note.
Commit: 7d879bc85129cba6608145d9ae5ccfc9d2fcfa1c
https://github.com/llvm/llvm-project/commit/7d879bc85129cba6608145d9ae5ccfc9d2fcfa1c
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/test/CodeGen/AArch64/sign-return-address-tailcall.ll
Log Message:
-----------
[AArch64][PAC] Refine authenticated pointer check methods (#74074)
Align the values of the immediate operand of BRK instruction with those
used by the existing arm64e implementation.
Make AuthCheckMethod::DummyLoad use the requested register
instead of LR.
Commit: 2d69827c5c754f0eca98e497ecf0e52ed54b4fd3
https://github.com/llvm/llvm-project/commit/2d69827c5c754f0eca98e497ecf0e52ed54b4fd3
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
M llvm/test/Transforms/ArgumentPromotion/X86/thiscall.ll
M llvm/test/Transforms/ArgumentPromotion/store-into-inself.ll
M llvm/test/Transforms/Attributor/convergent.ll
M llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
M llvm/test/Transforms/Attributor/dereferenceable-2.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
M llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-infinite-loop-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-start-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-coro-id-async-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-end-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-no-cse-swift-async-context-addr.ll
M llvm/test/Transforms/Coroutines/coro-async-phi.ll
M llvm/test/Transforms/Coroutines/coro-async-unreachable.ll
M llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
M llvm/test/Transforms/CorrelatedValuePropagation/minmaxabs.ll
M llvm/test/Transforms/CorrelatedValuePropagation/range.ll
M llvm/test/Transforms/CorrelatedValuePropagation/select.ll
M llvm/test/Transforms/CorrelatedValuePropagation/sub.ll
M llvm/test/Transforms/DeadArgElim/byref.ll
M llvm/test/Transforms/DeadArgElim/fct_ptr.ll
M llvm/test/Transforms/GVN/condprop-memdep-invalidation.ll
M llvm/test/Transforms/GVN/pr17732.ll
M llvm/test/Transforms/GVNHoist/hoist-recursive-geps.ll
M llvm/test/Transforms/GVNHoist/infinite-loop-direct.ll
M llvm/test/Transforms/GVNHoist/infinite-loop-indirect.ll
M llvm/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll
M llvm/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll
M llvm/test/Transforms/GlobalOpt/GSROA-section.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-gep-constexpr.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-other-constexpr.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-ptrtoint-add-constexpr.ll
M llvm/test/Transforms/GlobalOpt/externally-initialized-aggregate.ll
M llvm/test/Transforms/GlobalOpt/globalsra-partial.ll
M llvm/test/Transforms/GlobalOpt/globalsra.ll
M llvm/test/Transforms/GlobalOpt/invariant.ll
M llvm/test/Transforms/GlobalOpt/malloc-promote-opaque-ptr.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores-initializers.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores-once.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores.ll
M llvm/test/Transforms/IROutliner/nooutline-attribute.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/insert-pos-assert.ll
M llvm/test/Transforms/Inline/call-intrinsic-objectsize.ll
M llvm/test/Transforms/Inline/inline-byval-bonus.ll
M llvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll
M llvm/test/Transforms/Inline/inlined-loop-metadata.ll
M llvm/test/Transforms/InstCombine/alloca.ll
M llvm/test/Transforms/InstCombine/call.ll
M llvm/test/Transforms/InstCombine/fmul.ll
M llvm/test/Transforms/InstCombine/memchr-8.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoopDistribute/symbolic-stride.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-negative.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-version.ll
M llvm/test/Transforms/LoopFlatten/widen-iv.ll
M llvm/test/Transforms/LoopIdiom/lir-heurs-multi-block-loop.ll
M llvm/test/Transforms/LoopInterchange/profitability.ll
M llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
M llvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll
M llvm/test/Transforms/LoopSimplify/do-preheader-dbg.ll
M llvm/test/Transforms/LoopStrengthReduce/Power/memory-intrinsic.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll
M llvm/test/Transforms/LoopUnroll/ARM/mve-nounroll.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/MoveAutoInit/clobber.ll
M llvm/test/Transforms/NewGVN/flags-simplify.ll
M llvm/test/Transforms/NewGVN/no_speculative_loads_with_asan.ll
M llvm/test/Transforms/NewGVN/pr17732.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
M llvm/test/Transforms/PGOProfile/coverage.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-abs.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
M llvm/test/Transforms/SROA/invariant-group.ll
M llvm/test/Transforms/SROA/phi-gep.ll
M llvm/test/Transforms/SROA/scalable-vector-struct.ll
M llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/streaming-compatible-expand-masked-gather-scatter.ll
M llvm/test/Transforms/Util/pr49185.ll
M llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
M llvm/test/Transforms/VectorCombine/X86/load-widening.ll
Log Message:
-----------
[Transforms] Convert tests to opaque pointers (NFC)
Commit: ddd95b15d102331ecb7ce94dcf3a7280e0a133fa
https://github.com/llvm/llvm-project/commit/ddd95b15d102331ecb7ce94dcf3a7280e0a133fa
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
Log Message:
-----------
[RemoveDIs] Handle DPValues in hoistCommonCodeFromSuccessors (#79476)
Hoist DPValues attached to each instruction being considered for hoisting if
they are identical in lock-step. This includes the final instructions which
are considered but not hoisted, because the corresponding dbg.values would
appear before those instruction and thus hoisted if identical.
Identical debug records hoisted:
llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
Non-identical debug records not hoisted:
llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll
Debug records attached to first not-hoisted instructions are hoisted:
llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll
Commit: 9dd40f8c85a30b247dfa47d7ec4353eb69522876
https://github.com/llvm/llvm-project/commit/9dd40f8c85a30b247dfa47d7ec4353eb69522876
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
Log Message:
-----------
[docs][RISCV] Update release notes to include Zalasr and S* extensions from profiles spec
Also reflow the line for Zabha, as we normally line-wrap this file.
Commit: 1aee1e1f4c4b504becc06521546de992a662694b
https://github.com/llvm/llvm-project/commit/1aee1e1f4c4b504becc06521546de992a662694b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/assume-index-positive.ll
M llvm/test/Analysis/BasicAA/index-size.ll
M llvm/test/Analysis/BasicAA/noalias-bugs.ll
M llvm/test/Analysis/BasicAA/vscale.ll
M llvm/test/Analysis/BlockFrequencyInfo/basic.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_pgo.ll
M llvm/test/Analysis/BlockFrequencyInfo/loop_with_invoke.ll
M llvm/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll
M llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
M llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
M llvm/test/Analysis/Dominators/invoke.ll
M llvm/test/Analysis/FunctionPropertiesAnalysis/matmul.ll
M llvm/test/Analysis/IVUsers/deep_recursion_in_scev.ll
M llvm/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll
M llvm/test/Analysis/LazyValueAnalysis/invalidation.ll
M llvm/test/Analysis/LoopAccessAnalysis/forked-pointers.ll
M llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/LoopnestFixedSize.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/loads-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matvecmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/single-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
M llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-complex.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-simple.ll
M llvm/test/Analysis/LoopNestAnalysis/duplicate-successors.ll
M llvm/test/Analysis/LoopNestAnalysis/imperfectnest.ll
M llvm/test/Analysis/LoopNestAnalysis/infinite.ll
M llvm/test/Analysis/LoopNestAnalysis/perfectnest.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/atomics.ll
Log Message:
-----------
[Analysis] Convert tests to opaque pointers (NFC)
Commit: 0940be158104e055ab255ccb5c1af9c7ccc7358f
https://github.com/llvm/llvm-project/commit/0940be158104e055ab255ccb5c1af9c7ccc7358f
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/docs/Bufferization.md
M mlir/include/mlir/Dialect/Bufferization/Pipelines/Passes.h
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-callop-interface.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-function-boundaries.mlir
Log Message:
-----------
[mlir][bufferization] Never pass ownership to functions (#80655)
Even when `private-function-dynamic-ownership` is set, ownership should
never be passed to the callee. This can lead to double deallocs (#77096)
or use-after-free in the caller because ownership is currently passed
regardless of whether there are any further uses of the buffer in the
caller or not.
Note: This is consistent with the fact that ownership is never passed to
nested regions.
This commit fixes #77096.
Commit: 13e52b32790e3c3d2fb16139f082a588b4e0f4db
https://github.com/llvm/llvm-project/commit/13e52b32790e3c3d2fb16139f082a588b4e0f4db
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
Log Message:
-----------
[docs][RISCV] Add missed release note for Zimop codegen support
Commit: 84ea236af9f36d409d2c45c66f8a8b6eb027935d
https://github.com/llvm/llvm-project/commit/84ea236af9f36d409d2c45c66f8a8b6eb027935d
Author: David Green <david.green at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/AliasSet/memloc-vscale.ll
M llvm/test/Analysis/BasicAA/vscale.ll
Log Message:
-----------
[BasicAA] Handle scalable type sizes with constant offsets (#80445)
This is a separate, but related issue to #69152 that was attempting to improve
AA with scalable dependency distances. This patch attempts to improve when
there are scalable accesses with a constant offset between them. We happen to
get a report of such a thing recently, where so long as the vscale_range is
known, the maximum size of the access can be assessed and better aliasing
results can be returned.
The Upper range of the vscale_range, along with known part of the typesize are
used to prove that Off >= CR.upper * LSize. It does not try to produce
PartialAlias results at the moment from the lower vscale_range. It also enables
the added benefit of allowing better alias analysis when the RHS of the two
values is scalable, but the LHS is normal and can be treated like any other
aliasing query.
Commit: 1ee315ae7964c8433b772e0b5d667834994ba753
https://github.com/llvm/llvm-project/commit/1ee315ae7964c8433b772e0b5d667834994ba753
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global-pic.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-xclass-copies.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
M llvm/test/CodeGen/AArch64/PBQP-csr.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
M llvm/test/CodeGen/AArch64/add-i256.ll
M llvm/test/CodeGen/AArch64/addrsig-macho.ll
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-bad-outline.mir
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
M llvm/test/CodeGen/AArch64/arm64-ldp.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
M llvm/test/CodeGen/AArch64/compute-call-frame-size-unreachable-pass.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
M llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/divrem.ll
M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/fmov-imm-licm.ll
M llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/irg-nomem.mir
M llvm/test/CodeGen/AArch64/ldradr.ll
M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
M llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
M llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
M llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
M llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
M llvm/test/CodeGen/AArch64/merge-store.ll
M llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
M llvm/test/CodeGen/AArch64/sched-movprfx.ll
M llvm/test/CodeGen/AArch64/settag-merge.mir
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
M llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
M llvm/test/CodeGen/AArch64/speculation-hardening.mir
M llvm/test/CodeGen/AArch64/spillfill-sve.ll
M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
M llvm/test/CodeGen/AArch64/stack-guard-sve.ll
M llvm/test/CodeGen/AArch64/stack-probing-64k.ll
M llvm/test/CodeGen/AArch64/stack-tagging-cfi.ll
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
M llvm/test/CodeGen/AArch64/sub-of-bias.ll
M llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
M llvm/test/CodeGen/AArch64/sve-alloca.ll
M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
M llvm/test/CodeGen/AArch64/sve-fp.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
M llvm/test/CodeGen/AArch64/sve-gep.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-setcc.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-varargs-callee-broken.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-ld1-single.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-loads.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll
M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
M llvm/test/CodeGen/AArch64/taildup-addrtaken.mir
M llvm/test/CodeGen/AArch64/tailmerging_in_mbp.ll
M llvm/test/CodeGen/AArch64/tiny-model-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-static.ll
M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
M llvm/test/CodeGen/AArch64/v3f-to-int.ll
M llvm/test/CodeGen/AArch64/win-catchpad-nested-cxx.ll
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
M llvm/test/CodeGen/AArch64/zero-reg.ll
Log Message:
-----------
[AArch64] Convert tests to opaque pointers (NFC)
Commit: 1d3d8936baf9f15e23603bbb1cfe0a5610d458d3
https://github.com/llvm/llvm-project/commit/1d3d8936baf9f15e23603bbb1cfe0a5610d458d3
Author: Yi Wu <yi.wu2 at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/atan2d.f90
A flang/test/Lower/Intrinsics/atan2pi.f90
M flang/test/Lower/Intrinsics/atand.f90
A flang/test/Lower/Intrinsics/atanpi.f90
Log Message:
-----------
[flang] Fix for atand(Y,X), and implment atan2d(Y,X), atanpi(X), atanpi(Y,X), atan2pi(Y,X) (#79002)
Fix: https://github.com/llvm/llvm-project/issues/78568
---------
Co-authored-by: jeanPerier <jean.perier.polytechnique at gmail.com>
Commit: 00a4e248dc65d3a60fd900b342d4ba410bf70af0
https://github.com/llvm/llvm-project/commit/00a4e248dc65d3a60fd900b342d4ba410bf70af0
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
Log Message:
-----------
[AMDGPU] Convert tests to opaque pointers (NFC)
Commit: 6e83c0a1cbfdb0c0f13c282312c47c7945970f55
https://github.com/llvm/llvm-project/commit/6e83c0a1cbfdb0c0f13c282312c47c7945970f55
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/AMX/amx-combine.ll
M llvm/test/CodeGen/X86/AMX/amx-tile-complex-internals.ll
M llvm/test/CodeGen/X86/GlobalISel/x86_64-irtranslator-struct-return.ll
M llvm/test/CodeGen/X86/MergeConsecutiveStores.ll
M llvm/test/CodeGen/X86/PR37310.mir
M llvm/test/CodeGen/X86/atomic-dagsched.ll
M llvm/test/CodeGen/X86/atomic-nocx16.ll
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change2.mir
M llvm/test/CodeGen/X86/avoid-sfb-g-no-change3.mir
M llvm/test/CodeGen/X86/avoid-sfb-kill-flags.mir
M llvm/test/CodeGen/X86/avoid-sfb-offset.mir
M llvm/test/CodeGen/X86/avx512f-256-set0.mir
M llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
M llvm/test/CodeGen/X86/basic-block-labels-mir-parse.mir
M llvm/test/CodeGen/X86/basic-block-sections-module1.ll
M llvm/test/CodeGen/X86/basic-block-sections-module2.ll
M llvm/test/CodeGen/X86/block-placement.ll
M llvm/test/CodeGen/X86/callbr-asm-sink.ll
M llvm/test/CodeGen/X86/cmp.ll
M llvm/test/CodeGen/X86/code-model-kernel.ll
M llvm/test/CodeGen/X86/code_placement.ll
M llvm/test/CodeGen/X86/complex-asm.ll
M llvm/test/CodeGen/X86/crash.ll
M llvm/test/CodeGen/X86/fastisel-memset-flush.ll
M llvm/test/CodeGen/X86/function-alias.ll
M llvm/test/CodeGen/X86/funnel-shift.ll
M llvm/test/CodeGen/X86/large-constants-x32.ll
M llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
M llvm/test/CodeGen/X86/madd.ll
M llvm/test/CodeGen/X86/memcpy-scoped-aa.ll
M llvm/test/CodeGen/X86/merge-store-partially-alias-loads.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/post-ra-sched-with-debug.mir
M llvm/test/CodeGen/X86/pr44140.ll
M llvm/test/CodeGen/X86/pr48064.mir
M llvm/test/CodeGen/X86/pre-coalesce-2.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/CodeGen/X86/select-neg.ll
M llvm/test/CodeGen/X86/sse-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/stack-protector-dbginfo.ll
M llvm/test/CodeGen/X86/statepoint-cmp-sunk-past-statepoint.ll
M llvm/test/CodeGen/X86/tail-dup-merge-loop-headers.ll
M llvm/test/CodeGen/X86/tailcc-dwarf.ll
M llvm/test/CodeGen/X86/threadlocal_address.ll
M llvm/test/CodeGen/X86/win64-byval.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppCondiTemps.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll
Log Message:
-----------
[X86] Convert tests to opaque pointers (NFC)
Commit: 60732c0fae56829c5475091de678ad46f0ce6287
https://github.com/llvm/llvm-project/commit/60732c0fae56829c5475091de678ad46f0ce6287
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/EvaluationResult.cpp
Log Message:
-----------
[clang][Interp][NFC] Remove superfluous return statement
Commit: 69ffa7be3bda5547d7a41233f86b88539616e386
https://github.com/llvm/llvm-project/commit/69ffa7be3bda5547d7a41233f86b88539616e386
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sadd_sat_vec.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/sse41.ll
M llvm/test/CodeGen/X86/ssub_sat_vec.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_cmp_sint-128.ll
M llvm/test/CodeGen/X86/vec_compare-sse4.ll
M llvm/test/CodeGen/X86/vec_minmax_sint.ll
M llvm/test/CodeGen/X86/vec_saddo.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_ssubo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect-post-combine.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - load+zero vector constants that can be stored in a truncated form (#80428)
Further develops the vsextload support added in #79815 / b5d35feacb7246573c6a4ab2bddc4919a4228ed5 - reduces the size of the vector constant by storing it in the constant pool in a truncated form, and zero-extend it as part of the load.
Commit: bc82d1a6b7f8a795e923b10e8ef0fdc34628a48e
https://github.com/llvm/llvm-project/commit/bc82d1a6b7f8a795e923b10e8ef0fdc34628a48e
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-teams.mlir
Log Message:
-----------
[OpenMPIRBuilder][MLIR] Pass target-cpu and target-features to outlined functions (#80283)
This patch adds support for forwarding the target-cpu and
target-features attributes to functions outlined in the OpenMPIRBuilder.
This, in turn, results in the addition of these attributes for functions
created during the translation of the `omp.parallel`, `omp.task` and
`omp.teams` operations, and for the `omp.wsloop` operation when doing
codegen for an OpenMP target device.
Commit: c391f285afdfd800a251b4ef6d0bbadbbe9069ff
https://github.com/llvm/llvm-project/commit/c391f285afdfd800a251b4ef6d0bbadbbe9069ff
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A clang/test/AST/Interp/atomic.cpp
Log Message:
-----------
[clang][Interp][NFC] Add simple test case for atomic types
Commit: 6ba9d2988ba471d3a1620da64d5a08f2edfe91ed
https://github.com/llvm/llvm-project/commit/6ba9d2988ba471d3a1620da64d5a08f2edfe91ed
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
A libc/src/math/ceilf128.h
A libc/src/math/floorf128.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/ceilf128.cpp
A libc/src/math/generic/floorf128.cpp
A libc/src/math/generic/roundf128.cpp
A libc/src/math/generic/truncf128.cpp
A libc/src/math/roundf128.h
A libc/src/math/truncf128.h
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/ceilf128_test.cpp
A libc/test/src/math/smoke/floorf128_test.cpp
A libc/test/src/math/smoke/roundf128_test.cpp
A libc/test/src/math/smoke/truncf128_test.cpp
Log Message:
-----------
[libc][math] Add float128 rounding functions (ceilf128, floorf128, roundf128, truncf128). (#80634)
Commit: d4ef4b818929732bcb68a536ef2c91891c0ad179
https://github.com/llvm/llvm-project/commit/d4ef4b818929732bcb68a536ef2c91891c0ad179
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/float128.h
M libc/spec/spec.td
M libc/spec/stdc.td
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/macros/properties/CMakeLists.txt
M libc/src/__support/macros/properties/float.h
Log Message:
-----------
[libc] Fix generated float128 header for aarch64 target. (#78017)
Commit: 7bdc80f35c325d148b1ddbdfce7dea8c6ba7af84
https://github.com/llvm/llvm-project/commit/7bdc80f35c325d148b1ddbdfce7dea8c6ba7af84
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
M llvm/test/CodeGen/AVR/ctors.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/elpm.ll
M llvm/test/CodeGen/AVR/features/avr-tiny.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
M llvm/test/CodeGen/AVR/inline-asm/loadstore.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lpmx.ll
M llvm/test/CodeGen/AVR/pr43443-ctor-alias.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-trait-object.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/struct.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
Log Message:
-----------
[AVR] Convert tests to opaque pointers (NFC)
Commit: b31fffbc7f1e0491bf599e82b7195e320d26e140
https://github.com/llvm/llvm-project/commit/b31fffbc7f1e0491bf599e82b7195e320d26e140
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
M llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
M llvm/test/CodeGen/ARM/Windows/wineh-basic.ll
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/aliases.ll
M llvm/test/CodeGen/ARM/code-placement.ll
M llvm/test/CodeGen/ARM/constant-island-movwt.mir
M llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
M llvm/test/CodeGen/ARM/debug-info-blocks.ll
M llvm/test/CodeGen/ARM/debug-info-d16-reg.ll
M llvm/test/CodeGen/ARM/debug-info-s16-reg.ll
M llvm/test/CodeGen/ARM/dwarf-eh.ll
M llvm/test/CodeGen/ARM/ldrcppic.ll
M llvm/test/CodeGen/ARM/misched-copy-arm.ll
M llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
M llvm/test/CodeGen/ARM/readonly-aliases.ll
M llvm/test/CodeGen/ARM/tail-dup-kill-flags.ll
M llvm/test/CodeGen/Thumb/PR36658.mir
M llvm/test/CodeGen/Thumb/branch-to-return.ll
M llvm/test/CodeGen/Thumb/tbb-reuse.mir
M llvm/test/CodeGen/Thumb2/2012-01-13-CBNZBug.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/add_reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-default.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize-strd-lr.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/biquad-cascade-optsize.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/constbound.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/count_dominates_start.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/disjoint-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/dont-remove-loop-update.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/emptyblock.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/extract-element.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-16.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-32.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/incorrect-sub-8.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpnot-3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-1.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/inloop-vpsel-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/invariant-qreg.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/it-block-chain-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp-reordered.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-two-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/iv-vcmp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/livereg-no-loop-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-chain.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-copy-prev-iteration.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/loop-dec-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/lstp-insertion-position.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-after-dlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-lr-terminator.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mov-operand.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-def-before-start.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/move-start-after-def.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-block-cond-iter-count.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multi-cond-iter-count.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/multiple-do-loops.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-cbnz.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec-reorder.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-dec.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/no-vpsel-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-load.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/non-masked-store.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-invariant.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout-unknown-lanes.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/predicated-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions-vpt-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/reductions.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-non-header.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/skip-vpt-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/subreg-liveness.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/tp-multiple-vpst.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredicated-max.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unpredload.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/unrolled-and-vector.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vaddv.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vcmp-vpst-combination.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-add-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt-2.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-in-vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subi3.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp-subri12.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vctp16-reduce.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vector-arith-codegen.ll
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmaxmin_vpred_r.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vmldava_in_vpt.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/vpt-block-debug.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wls-revert-placement.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wlstp.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-liveout-lsr-shift.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-opcode-liveout.mir
M llvm/test/CodeGen/Thumb2/LowOverheadLoops/wrong-vctp-operand-liveout.mir
M llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-optimisation.ll
M llvm/test/CodeGen/Thumb2/mve-gather-scatter-tailpred.ll
M llvm/test/CodeGen/Thumb2/mve-phireg.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-distribute.ll
M llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
M llvm/test/CodeGen/Thumb2/mve-pred-vctpvpsel.ll
M llvm/test/CodeGen/Thumb2/mve-qrintrsplat.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-add-combine.ll
M llvm/test/CodeGen/Thumb2/mve-vecreduce-loops.ll
M llvm/test/CodeGen/Thumb2/mve-vmaxnma-commute.ll
M llvm/test/CodeGen/Thumb2/mve-vmovlloop.ll
M llvm/test/CodeGen/Thumb2/scavenge-lr.mir
M llvm/test/CodeGen/Thumb2/t2-teq-reduce.mir
Log Message:
-----------
[ARM] Convert tests to opaque pointers (NFC)
Commit: 89ec940b4a8020e1399e019d845be1a2d2217f69
https://github.com/llvm/llvm-project/commit/89ec940b4a8020e1399e019d845be1a2d2217f69
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
A llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
Log Message:
-----------
[AMDGPU] Insert spill codes for the SGPRs used for EXEC copy (#79428)
The SGPR registers used for preserving EXEC mask while lowering the
whole-wave register spills and copies should be preserved at the prolog
and epilog if they are in the CSR range. It isn't happening when there
is only wwm-copy lowered and there are no wwm-spills. This patch
addresses that problem.
Commit: 06f711a906be85e141bcce9a88ab304dc81e74ef
https://github.com/llvm/llvm-project/commit/06f711a906be85e141bcce9a88ab304dc81e74ef
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
Log Message:
-----------
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#80003)
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.
TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.
patch 3 from: https://github.com/llvm/llvm-project/pull/73337
Commit: ff9af4c43ad71eeba2cabe99609cfaa0fd54c1d0
https://github.com/llvm/llvm-project/commit/ff9af4c43ad71eeba2cabe99609cfaa0fd54c1d0
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/BPF/BTF/builtin-btf-type-id.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-2.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-struct-3.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-union-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-union-2.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/reloc.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/Generic/DbgValueAggregate.ll
M llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables-x.mir
M llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
M llvm/test/CodeGen/Hexagon/autohvx/fsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfsplat.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
M llvm/test/CodeGen/Hexagon/swp-new-phi.ll
M llvm/test/CodeGen/Hexagon/v5_insns.ll
M llvm/test/CodeGen/Hexagon/v60Vasr.ll
M llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
M llvm/test/CodeGen/Hexagon/vect-regpairs.ll
M llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll
M llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
M llvm/test/CodeGen/Lanai/codemodel.ll
M llvm/test/CodeGen/Lanai/inlineasm-output-template.ll
M llvm/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
M llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
M llvm/test/CodeGen/Lanai/peephole-compare.mir
M llvm/test/CodeGen/Lanai/set_and_hi.ll
M llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
M llvm/test/CodeGen/Lanai/subword.ll
M llvm/test/CodeGen/LoongArch/frame.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
M llvm/test/CodeGen/LoongArch/tail-calls.ll
M llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/AArch64/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AArch64/machine-metadata.mir
M llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
M llvm/test/CodeGen/MIR/AArch64/swp.mir
M llvm/test/CodeGen/MIR/AArch64/target-flags.mir
M llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
M llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir
M llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/MIR/Generic/frame-info.mir
M llvm/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir
M llvm/test/CodeGen/MIR/Mips/memory-operands.mir
M llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
M llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
M llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
M llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
M llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
M llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
M llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
M llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
M llvm/test/CodeGen/MIR/X86/global-value-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
M llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
M llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
M llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/large-index-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-offset-number-error.mir
M llvm/test/CodeGen/MIR/X86/large-size-in-memory-operand-error.mir
M llvm/test/CodeGen/MIR/X86/machine-basic-block-operands.mir
M llvm/test/CodeGen/MIR/X86/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/X86/machine-metadata.mir
M llvm/test/CodeGen/MIR/X86/machine-verifier-address.mir
M llvm/test/CodeGen/MIR/X86/metadata-operands.mir
M llvm/test/CodeGen/MIR/X86/missing-closing-quote.mir
M llvm/test/CodeGen/MIR/X86/missing-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/null-register-operands.mir
M llvm/test/CodeGen/MIR/X86/pr38773.mir
M llvm/test/CodeGen/MIR/X86/register-operands-target-flag-error.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-aliased.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-object-immutable.mir
M llvm/test/CodeGen/MIR/X86/spill-slot-fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/stack-object-debug-info.mir
M llvm/test/CodeGen/MIR/X86/stack-object-invalid-name.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operand-name-mismatch-error.mir
M llvm/test/CodeGen/MIR/X86/stack-object-operands.mir
M llvm/test/CodeGen/MIR/X86/stack-object-redefinition-error.mir
M llvm/test/CodeGen/MIR/X86/stack-objects.mir
M llvm/test/CodeGen/MIR/X86/undefined-fixed-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-ir-block-slot-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/undefined-named-global-value.mir
M llvm/test/CodeGen/MIR/X86/undefined-stack-object.mir
M llvm/test/CodeGen/MIR/X86/undefined-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/unknown-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-keyword.mir
M llvm/test/CodeGen/MIR/X86/unknown-metadata-node.mir
M llvm/test/CodeGen/MIR/X86/unknown-named-machine-basic-block.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-object-size-error.mir
M llvm/test/CodeGen/MIR/X86/variable-sized-stack-objects.mir
M llvm/test/CodeGen/MSP430/2009-05-10-CyclicDAG.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Rot.ll
M llvm/test/CodeGen/MSP430/2009-05-17-Shift.ll
M llvm/test/CodeGen/MSP430/2009-08-25-DynamicStackAlloc.ll
M llvm/test/CodeGen/MSP430/2009-09-18-AbsoluteAddr.ll
M llvm/test/CodeGen/MSP430/2009-10-10-OrImpDef.ll
M llvm/test/CodeGen/MSP430/2009-11-08-InvalidResNo.ll
M llvm/test/CodeGen/MSP430/2009-12-21-FrameAddr.ll
M llvm/test/CodeGen/MSP430/2009-12-22-InlineAsm.ll
M llvm/test/CodeGen/MSP430/2010-05-01-CombinerAnd.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-bis-xr.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-rx.ll
M llvm/test/CodeGen/MSP430/AddrMode-mov-xr.ll
M llvm/test/CodeGen/MSP430/BranchSelector.ll
M llvm/test/CodeGen/MSP430/Inst16mi.ll
M llvm/test/CodeGen/MSP430/Inst16mm.ll
M llvm/test/CodeGen/MSP430/Inst16mr.ll
M llvm/test/CodeGen/MSP430/Inst16rm.ll
M llvm/test/CodeGen/MSP430/Inst8mi.ll
M llvm/test/CodeGen/MSP430/Inst8mm.ll
M llvm/test/CodeGen/MSP430/Inst8mr.ll
M llvm/test/CodeGen/MSP430/Inst8rm.ll
M llvm/test/CodeGen/MSP430/InstII.ll
M llvm/test/CodeGen/MSP430/bit.ll
M llvm/test/CodeGen/MSP430/byval.ll
M llvm/test/CodeGen/MSP430/callee-saved.ll
M llvm/test/CodeGen/MSP430/calls.ll
M llvm/test/CodeGen/MSP430/cc_args.ll
M llvm/test/CodeGen/MSP430/cc_ret.ll
M llvm/test/CodeGen/MSP430/fp.ll
M llvm/test/CodeGen/MSP430/hwmult16.ll
M llvm/test/CodeGen/MSP430/hwmult32.ll
M llvm/test/CodeGen/MSP430/hwmultf5.ll
M llvm/test/CodeGen/MSP430/indirectbr.ll
M llvm/test/CodeGen/MSP430/indirectbr2.ll
M llvm/test/CodeGen/MSP430/inline-asm-absolute-addressing.ll
M llvm/test/CodeGen/MSP430/inline-asm.ll
M llvm/test/CodeGen/MSP430/inlineasm-output-template.ll
M llvm/test/CodeGen/MSP430/interrupt.ll
M llvm/test/CodeGen/MSP430/jumptable.ll
M llvm/test/CodeGen/MSP430/libcalls.ll
M llvm/test/CodeGen/MSP430/memset.ll
M llvm/test/CodeGen/MSP430/misched-msp430.ll
M llvm/test/CodeGen/MSP430/mult-alt-generic-msp430.ll
M llvm/test/CodeGen/MSP430/postinc.ll
M llvm/test/CodeGen/MSP430/promote-i8-mul.ll
M llvm/test/CodeGen/MSP430/spill-to-stack.ll
M llvm/test/CodeGen/MSP430/stacksave_restore.ll
M llvm/test/CodeGen/MSP430/struct-return.ll
M llvm/test/CodeGen/MSP430/struct_layout.ll
M llvm/test/CodeGen/MSP430/transient-stack-alignment.ll
M llvm/test/CodeGen/MSP430/vararg.ll
M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/var_arg.mir
M llvm/test/CodeGen/Mips/GlobalISel/irtranslator/sret_pointer.ll
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/store_split_because_of_memsize_or_align.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/var_arg.mir
M llvm/test/CodeGen/Mips/GlobalISel/mips-prelegalizer-combiner/inline-memcpy.mir
M llvm/test/CodeGen/Mips/GlobalISel/regbankselect/var_arg.mir
M llvm/test/CodeGen/Mips/hf16call32.ll
M llvm/test/CodeGen/Mips/hfptrcall.ll
M llvm/test/CodeGen/Mips/mips16_fpret.ll
M llvm/test/CodeGen/Mips/msa/emergency-spill.mir
M llvm/test/CodeGen/Mips/mulull.ll
M llvm/test/CodeGen/NVPTX/addrspacecast.ll
M llvm/test/CodeGen/NVPTX/bf16x2-instructions.ll
M llvm/test/CodeGen/NVPTX/ld-addrspace.ll
M llvm/test/CodeGen/NVPTX/ldu-ldg.ll
M llvm/test/CodeGen/NVPTX/noreturn.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-ocl.ll
M llvm/test/CodeGen/NVPTX/nvvm-reflect-opaque.ll
M llvm/test/CodeGen/NVPTX/short-ptr.ll
M llvm/test/CodeGen/NVPTX/st-addrspace.ll
M llvm/test/CodeGen/PowerPC/2007-11-04-CoalescerCrash.ll
M llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll
M llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll
M llvm/test/CodeGen/PowerPC/aix-complex.ll
M llvm/test/CodeGen/PowerPC/aix-tls-gd-target-flags.ll
M llvm/test/CodeGen/PowerPC/block-placement.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir
M llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir
M llvm/test/CodeGen/PowerPC/expand-foldable-isel.ll
M llvm/test/CodeGen/PowerPC/fast-isel-branch.ll
M llvm/test/CodeGen/PowerPC/lsr-insns-cost.ll
M llvm/test/CodeGen/PowerPC/ppc-TOC-stats.ll
M llvm/test/CodeGen/PowerPC/ppc32-selectcc-i64.ll
M llvm/test/CodeGen/PowerPC/preincprep-i64-check.ll
M llvm/test/CodeGen/PowerPC/preincprep-nontrans-crash.ll
M llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir
M llvm/test/CodeGen/PowerPC/sink-down-more-instructions-regpressure-high.mir
M llvm/test/CodeGen/PowerPC/sms-phi-1.ll
M llvm/test/CodeGen/PowerPC/sms-phi-3.ll
M llvm/test/CodeGen/PowerPC/stack-coloring-vararg.mir
M llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll
M llvm/test/CodeGen/PowerPC/vsx-infl-copy1.ll
M llvm/test/CodeGen/PowerPC/vsx-infl-copy2.ll
M llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
M llvm/test/CodeGen/RISCV/copy-frameindex.mir
M llvm/test/CodeGen/RISCV/copyprop.ll
M llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
M llvm/test/CodeGen/RISCV/fli-licm.ll
M llvm/test/CodeGen/RISCV/live-sp.mir
M llvm/test/CodeGen/RISCV/make-compressible-rv64.mir
M llvm/test/CodeGen/RISCV/make-compressible.mir
M llvm/test/CodeGen/RISCV/misched-load-clustering.ll
M llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
M llvm/test/CodeGen/RISCV/prefetch.ll
M llvm/test/CodeGen/RISCV/push-pop-popret.ll
M llvm/test/CodeGen/RISCV/regalloc-last-chance-recoloring-failure.ll
M llvm/test/CodeGen/RISCV/rv64-legal-i32/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/rv64-patchpoint.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap-frame-setup.ll
M llvm/test/CodeGen/RISCV/rv64-stackmap.ll
M llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll
M llvm/test/CodeGen/RISCV/rvv/addi-rvv-stack-object.mir
M llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
M llvm/test/CodeGen/RISCV/rvv/alloca-load-store-scalable-struct.ll
M llvm/test/CodeGen/RISCV/rvv/calling-conv-fastcc.ll
M llvm/test/CodeGen/RISCV/rvv/dont-sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/extload-truncstore.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-fp.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-i1.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/frameindex-addr.ll
M llvm/test/CodeGen/RISCV/rvv/implicit-def-copy.ll
M llvm/test/CodeGen/RISCV/rvv/insert-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/load-mask.ll
M llvm/test/CodeGen/RISCV/rvv/localvar.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-load-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-fp.ll
M llvm/test/CodeGen/RISCV/rvv/masked-store-int.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tama.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll
M llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll
M llvm/test/CodeGen/RISCV/rvv/memory-args.ll
M llvm/test/CodeGen/RISCV/rvv/mgather-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/narrow-shift-extend.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops-mir.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
M llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
M llvm/test/CodeGen/RISCV/rvv/scalable-vector-struct.ll
M llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
M llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
M llvm/test/CodeGen/RISCV/rvv/strided-vpload.ll
M llvm/test/CodeGen/RISCV/rvv/tail-agnostic-impdef-copy.mir
M llvm/test/CodeGen/RISCV/rvv/unaligned-loads-stores.ll
M llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll
M llvm/test/CodeGen/RISCV/rvv/vle.ll
M llvm/test/CodeGen/RISCV/rvv/vleff-vlseg2ff-output.ll
M llvm/test/CodeGen/RISCV/rvv/vleff.ll
M llvm/test/CodeGen/RISCV/rvv/vlm.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vloxei.ll
M llvm/test/CodeGen/RISCV/rvv/vlse.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vluxei.ll
M llvm/test/CodeGen/RISCV/rvv/vpload.ll
M llvm/test/CodeGen/RISCV/rvv/vpstore.ll
M llvm/test/CodeGen/RISCV/rvv/vse.ll
M llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-intrinsics.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-regression.ll
M llvm/test/CodeGen/RISCV/rvv/vsm.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsoxei.ll
M llvm/test/CodeGen/RISCV/rvv/vsse.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vsuxei.ll
M llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll
M llvm/test/CodeGen/RISCV/rvv/wrong-stack-offset-for-rvv-object.mir
M llvm/test/CodeGen/RISCV/rvv/zve32-types.ll
M llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/xtheadfmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmemidx.ll
M llvm/test/CodeGen/RISCV/xtheadmempair.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmMemoryOperand.ll
M llvm/test/CodeGen/SPARC/2008-10-10-InlineAsmRegOperand.ll
M llvm/test/CodeGen/SPARC/2009-08-28-PIC.ll
M llvm/test/CodeGen/SPARC/2011-01-11-CC.ll
M llvm/test/CodeGen/SPARC/2011-01-11-FrameAddr.ll
M llvm/test/CodeGen/SPARC/2011-01-19-DelaySlot.ll
M llvm/test/CodeGen/SPARC/2011-01-21-ByValArgs.ll
M llvm/test/CodeGen/SPARC/2011-01-22-SRet.ll
M llvm/test/CodeGen/SPARC/2011-12-03-TailDuplication.ll
M llvm/test/CodeGen/SPARC/2012-05-01-LowerArguments.ll
M llvm/test/CodeGen/SPARC/2013-05-17-CallFrame.ll
M llvm/test/CodeGen/SPARC/32abi.ll
M llvm/test/CodeGen/SPARC/64abi.ll
M llvm/test/CodeGen/SPARC/64atomics.ll
M llvm/test/CodeGen/SPARC/64bit.ll
M llvm/test/CodeGen/SPARC/64cond.ll
M llvm/test/CodeGen/SPARC/LeonCASAInstructionUT.ll
M llvm/test/CodeGen/SPARC/LeonFixAllFDIVSQRTPassUT.ll
M llvm/test/CodeGen/SPARC/LeonInsertNOPLoadPassUT.ll
M llvm/test/CodeGen/SPARC/LeonItinerariesUT.ll
M llvm/test/CodeGen/SPARC/LeonSMACUMACInstructionUT.ll
M llvm/test/CodeGen/SPARC/atomics.ll
M llvm/test/CodeGen/SPARC/basictest.ll
M llvm/test/CodeGen/SPARC/bigreturn.ll
M llvm/test/CodeGen/SPARC/blockaddr.ll
M llvm/test/CodeGen/SPARC/cast-sret-func.ll
M llvm/test/CodeGen/SPARC/constructor.ll
M llvm/test/CodeGen/SPARC/exception.ll
M llvm/test/CodeGen/SPARC/fail-alloca-align.ll
M llvm/test/CodeGen/SPARC/float.ll
M llvm/test/CodeGen/SPARC/fp128.ll
M llvm/test/CodeGen/SPARC/fp16-promote.ll
M llvm/test/CodeGen/SPARC/func-addr.ll
M llvm/test/CodeGen/SPARC/globals.ll
M llvm/test/CodeGen/SPARC/inlineasm-output-template.ll
M llvm/test/CodeGen/SPARC/inlineasm-v9.ll
M llvm/test/CodeGen/SPARC/inlineasm.ll
M llvm/test/CodeGen/SPARC/leafproc.ll
M llvm/test/CodeGen/SPARC/missing-sret.ll
M llvm/test/CodeGen/SPARC/mult-alt-generic-sparc.ll
M llvm/test/CodeGen/SPARC/obj-relocs.ll
M llvm/test/CodeGen/SPARC/overflow-intrinsic-optimizations.ll
M llvm/test/CodeGen/SPARC/pic.ll
M llvm/test/CodeGen/SPARC/private.ll
M llvm/test/CodeGen/SPARC/reserved-regs.ll
M llvm/test/CodeGen/SPARC/select-mask.ll
M llvm/test/CodeGen/SPARC/setjmp.ll
M llvm/test/CodeGen/SPARC/spillsize.ll
M llvm/test/CodeGen/SPARC/sret-secondary.ll
M llvm/test/CodeGen/SPARC/stack-align.ll
M llvm/test/CodeGen/SPARC/stack-protector.ll
M llvm/test/CodeGen/SPARC/tailcall.ll
M llvm/test/CodeGen/SPARC/thread-pointer.ll
M llvm/test/CodeGen/SPARC/tls.ll
M llvm/test/CodeGen/SPARC/varargs-v8.ll
M llvm/test/CodeGen/SPARC/varargs.ll
M llvm/test/CodeGen/SPARC/vector-extract-elt.ll
M llvm/test/CodeGen/SPARC/zerostructcall.ll
M llvm/test/CodeGen/SystemZ/Large/branch-01.ll
M llvm/test/CodeGen/SystemZ/RAbasic-invalid-LR-update.mir
M llvm/test/CodeGen/SystemZ/clear-liverange-spillreg.mir
M llvm/test/CodeGen/SystemZ/cond-move-04.mir
M llvm/test/CodeGen/SystemZ/cond-move-05.mir
M llvm/test/CodeGen/SystemZ/cond-move-08.mir
M llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints-02.mir
M llvm/test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
M llvm/test/CodeGen/SystemZ/dag-combine-02.ll
M llvm/test/CodeGen/SystemZ/debuginstr-00.mir
M llvm/test/CodeGen/SystemZ/debuginstr-01.mir
M llvm/test/CodeGen/SystemZ/debuginstr-cgp.mir
M llvm/test/CodeGen/SystemZ/foldmemop-imm-02.mir
M llvm/test/CodeGen/SystemZ/foldmemop-msc.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-binops.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-cc.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-cmp.mir
M llvm/test/CodeGen/SystemZ/foldmemop-vec-fusedfp.mir
M llvm/test/CodeGen/SystemZ/fp-conv-17.mir
M llvm/test/CodeGen/SystemZ/frame-26.mir
M llvm/test/CodeGen/SystemZ/int-cmp-56.mir
M llvm/test/CodeGen/SystemZ/isel-debug.ll
M llvm/test/CodeGen/SystemZ/load-and-test-RA-hints.mir
M llvm/test/CodeGen/SystemZ/loop-04.ll
M llvm/test/CodeGen/SystemZ/multiselect-02.mir
M llvm/test/CodeGen/SystemZ/postra-sched-expandedops.mir
M llvm/test/CodeGen/SystemZ/regalloc-GR128-02.mir
M llvm/test/CodeGen/SystemZ/selectcc-04.ll
M llvm/test/CodeGen/SystemZ/subregliveness-06.mir
M llvm/test/CodeGen/SystemZ/zos-landingpad.ll
M llvm/test/CodeGen/VE/Scalar/pic_access_data.ll
M llvm/test/CodeGen/VE/Scalar/pic_indirect_func_call.ll
M llvm/test/CodeGen/WebAssembly/cfg-stackify.ll
M llvm/test/CodeGen/WebAssembly/global.ll
M llvm/test/CodeGen/WebAssembly/userstack.ll
M llvm/test/CodeGen/WinCFGuard/cfguard-cast.ll
M llvm/test/CodeGen/WinCFGuard/cfguard-giats.ll
M llvm/test/CodeGen/WinCFGuard/cfguard.ll
M llvm/test/CodeGen/XCore/threads.ll
Log Message:
-----------
[CodeGen] Convert tests to opaque pointers (NFC)
Commit: 4e958abf2f44d08129eafd5b6a4ee2bd3584ed22
https://github.com/llvm/llvm-project/commit/4e958abf2f44d08129eafd5b6a4ee2bd3584ed22
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
Log Message:
-----------
[AMDGPU][PromoteAlloca] Support memsets to ptr allocas (#80678)
Fixes #80366
Commit: a5d206df792b61a0b6c5ac44343a97696fc6071d
https://github.com/llvm/llvm-project/commit/a5d206df792b61a0b6c5ac44343a97696fc6071d
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/div_i128.ll
A llvm/test/CodeGen/AMDGPU/div_v2i128.ll
Log Message:
-----------
AMDGPU: Set max supported div/rem size to 64 (#80669)
This enables IR expansion for i128 divisions. The vector case is still
broken because ExpandLargeDivRem doesn't try to handle them.
Fixes: SWDEV-426193
Commit: a826a0c234c38eab194119bebcab91aabc2e3759
https://github.com/llvm/llvm-project/commit/a826a0c234c38eab194119bebcab91aabc2e3759
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
A llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
Log Message:
-----------
[RISCV] Add tests for reduce.fmaximum/fminimum. NFC (#80553)
This is to add test coverage for crash report in #80340
Commit: 66397435ed83c2247f49d302246ba5a87f4dd85f
https://github.com/llvm/llvm-project/commit/66397435ed83c2247f49d302246ba5a87f4dd85f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Add common getSrcIdx helper to determine source index after AVX512 masked predicates. NFC.
Commit: bc6370abd3f1e6b02100927095a2797472d6ff70
https://github.com/llvm/llvm-project/commit/bc6370abd3f1e6b02100927095a2797472d6ff70
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] addConstantComments - split VPERMILPS/VPERMILPD handling to reduce repeated switch cases etc. NFC.
Commit: 992d8527585817af685bba0d82ed4e808bc613bb
https://github.com/llvm/llvm-project/commit/992d8527585817af685bba0d82ed4e808bc613bb
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Flang.cpp
A flang/test/Driver/aarch64-outline-atomics.f90
M flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
A flang/test/Integration/aarch64-outline-atomics.f90
Log Message:
-----------
[flang]Add support for -moutline-atomics and -mno-outline-atomics (#78755)
This adds the support to add the target-feature to outline atomic operations (calling the
runtime library instead).
Commit: 825658856d94776889399a07a3939610ee1aa299
https://github.com/llvm/llvm-project/commit/825658856d94776889399a07a3939610ee1aa299
Author: Hui <hui.xie1990 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/semaphore
A libcxx/test/std/thread/thread.semaphore/lost_wakeup.pass.cpp
Log Message:
-----------
[libc++] fix `counting_semaphore` lost wakeups (#79265)
Fixes #77659
Fixes #46357
Picked up from https://reviews.llvm.org/D114119
Commit: a40d68b6de30a7fda44a2905e83df3d80fca2abf
https://github.com/llvm/llvm-project/commit/a40d68b6de30a7fda44a2905e83df3d80fca2abf
Author: Schrodinger ZHU Yifan <yifanzhu at rochester.edu>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/docs/index.rst
A libc/docs/libc_search.rst
R libc/docs/search.rst
M libc/docs/stdbit.rst
Log Message:
-----------
[libc] tiny fix for doc (#80512)
Commit: 8e00fc33ebabccf60388288c07201706ca3efd71
https://github.com/llvm/llvm-project/commit/8e00fc33ebabccf60388288c07201706ca3efd71
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
Log Message:
-----------
[mlir][ArmSME][nfc] Fix docs for 2-way ops
The "Refer to" and table shouldn't be in the example code sequence.
Commit: 5f5b3bb22b2e4ffcd14a8fc8a5edc14bc098a47e
https://github.com/llvm/llvm-project/commit/5f5b3bb22b2e4ffcd14a8fc8a5edc14bc098a47e
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/test/Dialect/ArmSME/outer-product-fusion.mlir
Log Message:
-----------
[mlir][ArmSME] Add rewrites to swap extract of extend (#80407)
In mixed matmul lowering (e.g., i8 to i32) we're seeing the following
sequence:
%0 = arith.extsi %src : vector<4x[8]xi8> to vector<4x[8]xi32>
%1 = vector.extract %0[0] : vector<[8]xi32> from vector<4x[8]xi32>
%lhs = vector.scalable.extract %1[0] : vector<[4]xi32> from
vector<[8]xi32>
... (same for rhs)
%2 = vector.outerproduct %lhs, %rhs, %acc vector<[4]xi32>,
vector<[4]xi32>
// x4 chained by accumulator
This chain of 4 outer products can be fused into a single 4-way widening
variant but the pass doesn't match on the IR, as it expects the source
of the inputs to be an extend and it can't look through the extracts.
This patch fixes this with two rewrites that swaps extract(extend) into
extend(extract).
Related to #78975, #79288.
Commit: abea3b27991dd73cad251f623a2a8f25a3e786ff
https://github.com/llvm/llvm-project/commit/abea3b27991dd73cad251f623a2a8f25a3e786ff
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/RDFGraph.cpp
Log Message:
-----------
[RDF] Skip over NoRegister. NFCI. (#80672)
This just avoids useless work of adding NoRegister to BaseSet, for
consistency with other places that iterate over all physical registers.
Commit: daea0820829bf5bbca9ab50fc118012a2508fab3
https://github.com/llvm/llvm-project/commit/daea0820829bf5bbca9ab50fc118012a2508fab3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__support/xlocale/__posix_l_fallback.h
Log Message:
-----------
[libc++] Add missing include of <string.h> in POSIX fallbacks for locale
Commit: 1af05363d6353d7edd0d00e37ae0eb70f54b4b64
https://github.com/llvm/llvm-project/commit/1af05363d6353d7edd0d00e37ae0eb70f54b4b64
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] getShuffleComment - use MI description to determine AVX512 masked predicates instead of src index offsets.
Commit: d15c454bedc05775b5080e1d2130b0554d5e5a81
https://github.com/llvm/llvm-project/commit/d15c454bedc05775b5080e1d2130b0554d5e5a81
Author: Kevin P. Neal <kevin.neal at sas.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
Log Message:
-----------
[FPEnv][AMDGPU] Correct strictfp tests.
Correct AMDGPU strictfp tests to follow the rules documented in the
LangRef:
https://llvm.org/docs/LangRef.html#constrained-floating-point-intrinsics
These tests needed the strictfp attribute added to function calls and
some declarations.
Some of the tests now pass with D146845, others get farther along and
fail with D146845. The tests revealed that further work is required
in mostly AMDGPU atomics to get the tests passing.
Since I was here anyway I removed the strictfp attribute from some
constrained intrinsic declarations. They have this attribute by default.
Test changes verified with D146845.
Commit: 3bf881635c9ca7398ba6a451e30a2156b22d59b5
https://github.com/llvm/llvm-project/commit/3bf881635c9ca7398ba6a451e30a2156b22d59b5
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Frontend/Offloading/Utility.cpp
Log Message:
-----------
[Offload] Fix entry global names on NVPTX target
Summary:
The PTX language rejects globals with `.` in the name. We need to change
the global name if we are targeting NVPTX to prevent the toolchain from
complaining.
Commit: 5249379d742148728f654665e113084c6b93cdf2
https://github.com/llvm/llvm-project/commit/5249379d742148728f654665e113084c6b93cdf2
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave64.cl
Log Message:
-----------
[AMDGPU] Allow w64 ballot to be used on w32 targets (#80183)
Summary:
Currently we cannot compile `__builtin_amdgcn_ballot_w64` on non-wave64
targets even though it is valid. This is relevant for making library
code that can handle both without needing to check the wavefront size.
This patch relaxes the semantic check for w64 so it can be used
normally.
Commit: e4f1ef85fd60c08c9ece4982fccf76e8101011b8
https://github.com/llvm/llvm-project/commit/e4f1ef85fd60c08c9ece4982fccf76e8101011b8
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/PrimType.h
A clang/test/AST/Interp/atomic.c
M clang/test/Sema/atomic-expr.c
Log Message:
-----------
[clang][Interp] Reject bitcasts to atomic types
The current interpreter does this, so follow suit to match its
diagnostics.
Commit: de46dc97b11b06c7efc225cfa08cf3cb68a8a75e
https://github.com/llvm/llvm-project/commit/de46dc97b11b06c7efc225cfa08cf3cb68a8a75e
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/spirv-tests.yml
Log Message:
-----------
[SPIR-V] Include SPIRV-Tools tests in CI (#80479)
Commit: e524ada6cbc6912156a713ffa179cb92e5362ebb
https://github.com/llvm/llvm-project/commit/e524ada6cbc6912156a713ffa179cb92e5362ebb
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp] Support zero init for complex types (#79728)
Initialize both elements to 0.
Commit: d1722868d34a69df8466b72098176f54a7af8823
https://github.com/llvm/llvm-project/commit/d1722868d34a69df8466b72098176f54a7af8823
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave64.cl
Log Message:
-----------
[Clang] Make AMDGPU OpenCL tests require AMD registered target
Summary:
These tests likely always failed but was hidden by the expected return
value. Simply make them require AMDGPU as a registered target so they
don't fail on other machines.
Commit: ae92f6e8aeb97e39b95a40fde8a176f6aff94063
https://github.com/llvm/llvm-project/commit/ae92f6e8aeb97e39b95a40fde8a176f6aff94063
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/docs/use/python-reference.rst
Log Message:
-----------
[lldb][Docs] Remove unnecessary colon in title
Commit: 2614672cc12258d2b07db2657e475ad70e01d5ba
https://github.com/llvm/llvm-project/commit/2614672cc12258d2b07db2657e475ad70e01d5ba
Author: elhewaty <mohamedatef1698 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/and.ll
Log Message:
-----------
[InstCombine] Fold ((cst << x) & 1) --> x == 0 when cst is odd (#79772)
Fold ((cst << x) & 1) to zext(x == 0) when cst is odd.
Fixes: https://github.com/llvm/llvm-project/issues/73384
Alive2: https://alive2.llvm.org/ce/z/5RbaK6
Commit: 41ea02261224446dadb1b1561d70137699255518
https://github.com/llvm/llvm-project/commit/41ea02261224446dadb1b1561d70137699255518
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Type.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
Log Message:
-----------
[Clang] Fix crash when recovering from an invalid pack indexing type. (#80652)
If the pattern of a pack indexing type did not contain a pack, we would
still construct a pack indexing type (to improve error messages) but we
would fail to make the type as dependent, leading to infinite recursion
when trying to extract a canonical type.
Commit: 4881cbd407e73f940a8e9ede501c2eee190ec9dd
https://github.com/llvm/llvm-project/commit/4881cbd407e73f940a8e9ede501c2eee190ec9dd
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/cxx98.cpp
M clang/test/SemaCXX/pr72025.cpp
Log Message:
-----------
[clang][Interp] Fix MemberExpr initializing an existing value (#79973)
This is similar to c1ad363e6eba308fa94c47374ee98b3c79693a35, but with
the additional twist that initializing an existing value from a
`MemberExpr` was not working correctly.
Commit: 8cb2de7faecdd4e053dfc8468b2be84e2d8afb4e
https://github.com/llvm/llvm-project/commit/8cb2de7faecdd4e053dfc8468b2be84e2d8afb4e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
Log Message:
-----------
[VPlan] Implement type inference for ICmp.
This fixes a crash in the attached test case due to missing type
inference for ICmp VPInstructions.
Commit: 0881d0f009427427509e5592b875d3fd702c595a
https://github.com/llvm/llvm-project/commit/0881d0f009427427509e5592b875d3fd702c595a
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/startup/gpu/CMakeLists.txt
M libc/startup/gpu/amdgpu/CMakeLists.txt
M libc/startup/gpu/nvptx/CMakeLists.txt
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/src/CMakeLists.txt
Log Message:
-----------
[libc] Refactor _build_gpu_objects cmake function. (#80631)
Commit: 702664e7870c27f197dfb744a4db54aa259ce452
https://github.com/llvm/llvm-project/commit/702664e7870c27f197dfb744a4db54aa259ce452
Author: Razvan Lupusoru <razvan.lupusoru at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-8.fir
Log Message:
-----------
[flang] Improve alias analysis to be precise for box and box.base_addr (#80335)
After PR#68727 the source for both the fir.box_addr and a box became the
same. Thus the detection that only one of the sources was direct and the
special logic around it was being skipped. As a result, the test
included would show a "MayAlias" result instead of a "NoAlias" result.
Commit: 9a87c5d440ec16a1116e060829df10bc2a6965ce
https://github.com/llvm/llvm-project/commit/9a87c5d440ec16a1116e060829df10bc2a6965ce
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Target/Cpp/func.mlir
Log Message:
-----------
[mlir][EmitC] Add support for external functions (#80547)
This adds a conversion from an externaly defined `func.func`, a
`func.func` without function body, to an `emitc.func` with an `extern`
specifier.
Commit: 0ac44385603ca67ceb969eb271d8c2075a8c14b4
https://github.com/llvm/llvm-project/commit/0ac44385603ca67ceb969eb271d8c2075a8c14b4
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M openmp/libomptarget/include/Shared/PluginAPI.h
M openmp/libomptarget/include/Shared/PluginAPI.inc
M openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/libomptarget/src/omptarget.cpp
Log Message:
-----------
[Libomptarget] Remove unused 'SupportsEmptyImages' API function (#80316)
Summary:
This function is always false in the current implementation and is not
even considered required. Just remove it and if someone needs it in the
future they can add it back in. This is done to simplify the interface
prior to other changes
Commit: ae354c5a45d319b3117c2822b8f6988461f3cb33
https://github.com/llvm/llvm-project/commit/ae354c5a45d319b3117c2822b8f6988461f3cb33
Author: Loïc Joly <loic.joly at sonarsource.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/BuiltinFunctionChecker.cpp
M clang/test/Analysis/builtin-functions.cpp
Log Message:
-----------
[analyzer] Model Microsoft "__assume" in the same way as clang "__builtin_assume"
Commit: f2c84211d2834c73ff874389c6bb47b1c76d391a
https://github.com/llvm/llvm-project/commit/f2c84211d2834c73ff874389c6bb47b1c76d391a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/version
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++] Add missing conditionals for feature-test macros (#80168)
We noticed that some feature-test macros were not conditional on
configuration flags like _LIBCPP_HAS_NO_FILESYSTEM. As a result, code
attempting to use FTMs would not work as intended.
This patch adds conditionals for a few feature-test macros, but more
issues may exist.
rdar://122020466
Commit: fee204f0c9b3b77898c1faa2a7415b0f64f5e7f0
https://github.com/llvm/llvm-project/commit/fee204f0c9b3b77898c1faa2a7415b0f64f5e7f0
Author: NagyDonat <donat.nagy at ericsson.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
M clang/test/Analysis/out-of-bounds-diagnostics.c
A clang/test/Analysis/out-of-bounds-notes.c
Log Message:
-----------
[analyzer] Support interestingness in ArrayBoundV2 (#78315)
This commit improves alpha.security.ArrayBoundV2 in two connected areas:
(1) It calls `markInteresting()` on the symbolic values that are
responsible for the out of bounds access.
(2) Its index-is-in-bounds assumptions are reported in note tags if they
provide information about the value of an interesting symbol.
This commit is limited to "display" changes: it introduces new
diagnostic pieces (potentially to bugs found by other checkers), but
ArrayBoundV2 will make the same assumptions and detect the same bugs
before and after this change.
As a minor unrelated change, this commit also updates/removes some very
old comments which became obsolete due to my previous changes.
Commit: 78a12f94904b69dd8b13f3e3fd258334b77ee7b8
https://github.com/llvm/llvm-project/commit/78a12f94904b69dd8b13f3e3fd258334b77ee7b8
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/libc_search.rst
M libc/spec/posix.td
M libc/src/__support/CMakeLists.txt
A libc/src/__support/intrusive_list.h
M libc/src/search/CMakeLists.txt
A libc/src/search/insque.cpp
A libc/src/search/insque.h
A libc/src/search/remque.cpp
A libc/src/search/remque.h
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/insque_test.cpp
Log Message:
-----------
[libc] implement insque and remque (#80305)
This PR implements the `insque` and `remque` entrypoint functions.
Commit: 30f776f8149dcbda0b6467176488e6551d068e40
https://github.com/llvm/llvm-project/commit/30f776f8149dcbda0b6467176488e6551d068e40
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__thread/support/c11.h
Log Message:
-----------
[libc++] Add missing <errno.h> include in threading support headers (#80311)
This was incorrectly removed when I split up the header.
Commit: c08d972a0043fe67de65ba331a144425c8cea449
https://github.com/llvm/llvm-project/commit/c08d972a0043fe67de65ba331a144425c8cea449
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/Pipelines/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][bufferization][NFC] Pass `DeallocationOptions` instead of flags (#80675)
Pass `DeallocationOptions` instead of `privateFuncDynamicOwnership`.
This will make it easier to add new options in the future.
Commit: 58f3a77efb633d56a48e031240fc8a37ba2b7557
https://github.com/llvm/llvm-project/commit/58f3a77efb633d56a48e031240fc8a37ba2b7557
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxxabi/src/private_typeinfo.cpp
Log Message:
-----------
[libc++abi] Replace usage of raw assert by _LIBCXXABI_ASSERT (#80689)
We strive not to use raw assert(...) anymore in libc++abi in preparation
for using the hardening framework.
Commit: de9a87301aefda9538eab7fcd563cc6ceec44e0a
https://github.com/llvm/llvm-project/commit/de9a87301aefda9538eab7fcd563cc6ceec44e0a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Split up getShuffleComment into printShuffleMask and printDstRegisterName helpers. NFC.
This will allow us to easily use printDstRegisterName for other mask predicate destination registers, and printout shuffle masks from other instruction types.
Commit: f4714204d0527269e037d85ed998a54678e3895f
https://github.com/llvm/llvm-project/commit/f4714204d0527269e037d85ed998a54678e3895f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] printExtend - add support for mask predicated instructions
Remove handling from EmitAnyX86InstComments and handle all VPMOVSX/VPMOVZX comments in addConstantComments now that we can generically handle the destination + mask register and shuffle mask comment
Commit: 47dcf5d5dc54e62c59fedbef1e8ec3a02c77cb83
https://github.com/llvm/llvm-project/commit/47dcf5d5dc54e62c59fedbef1e8ec3a02c77cb83
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/avx512-vec-cmp.ll
Log Message:
-----------
[X86] printBroadcast - add support for mask predicated instructions
Handle masked predicated load/broadcasts in addConstantComments now that we can generically handle the destination + mask register
This will more significantly help improve 'fixup constant' comments from #73509
Commit: f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3
https://github.com/llvm/llvm-project/commit/f958ad3b89c38be84dcf263ef9f9508a5cd3a6e3
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll
Log Message:
-----------
[X86] printZeroUpperMove - add support for mask predicated instructions
Handle masked predicated movss/movsd in addConstantComments now that we can generically handle the destination + mask register
This will more significantly help improve 'fixup constant' comments from #73509
Commit: 66cd768504b349f7bd16d236a3b4f611ffabf78f
https://github.com/llvm/llvm-project/commit/66cd768504b349f7bd16d236a3b4f611ffabf78f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/InterpBuiltin.cpp
M clang/test/AST/Interp/builtins.cpp
Log Message:
-----------
[clang][Interp] Handle __assume like __builtin_assume.
Commit: 29d47513b3ce706b5df66409170e40ba39f3795a
https://github.com/llvm/llvm-project/commit/29d47513b3ce706b5df66409170e40ba39f3795a
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
A flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
A mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
A mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
A mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
[mlir][openacc] Add legalize data pass for compute operation (#80351)
This patch adds a simple pass to replace the uses inside compute
operation. It replaces the `varPtr` values with their corresponding
`accPtr` values gathered through the dataClauseOperands.
private and reductions variables are not included in this pass since
they will normally be replace when they are materialized.
---------
Co-authored-by: Slava Zakharin <szakharin at nvidia.com>
Commit: 1ec252298925de50b27930c557ba9de3cc397afe
https://github.com/llvm/llvm-project/commit/1ec252298925de50b27930c557ba9de3cc397afe
Author: Dimitry Andric <dimitry at andric.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__bit_reference
Log Message:
-----------
[libc++] Rename __bit_reference template parameter to avoid conflict (#80661)
As of 4d20cfcf4eb08217ed37c4d4c38dc395d7a66d26, `__bit_reference`
contains a template `__fill_n` with a bool `_FillValue` parameter.
Unfortunately there is a relatively widely used piece of scientific
software called NetCDF, which exposes a (C) macro `_FillValue` in its
public headers.
When building the NetCDF C++ bindings, this quickly leads to compilation
errors when the macro interferes with the template in `__bit_reference`.
Rename the parameter to `_FillVal` to avoid the conflict.
Commit: 341d3a59999dec56f51804a5356b2e38256ab55c
https://github.com/llvm/llvm-project/commit/341d3a59999dec56f51804a5356b2e38256ab55c
Author: Rajveer Singh Bharadwaj <rajveer.developer at icloud.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/scoped_allocator
M libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.cnstr/allocs.pass.cpp
Log Message:
-----------
[libc++] Fix ambiguity when using std::scoped_allocator constructor (#80261)
Fixes #78754
Commit: e2bb91b25c8740625fecd127c1d908a2fabd0102
https://github.com/llvm/llvm-project/commit/e2bb91b25c8740625fecd127c1d908a2fabd0102
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/InitFIR.h
R flang/test/Fir/OpenACC/legalize-data.fir
M mlir/include/mlir/Dialect/OpenACC/CMakeLists.txt
R mlir/include/mlir/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.h
R mlir/include/mlir/Dialect/OpenACC/Transforms/Passes.td
M mlir/include/mlir/InitAllPasses.h
M mlir/lib/Dialect/OpenACC/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/IR/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/CMakeLists.txt
R mlir/lib/Dialect/OpenACC/Transforms/LegalizeData.cpp
R mlir/test/Dialect/OpenACC/legalize-data.mlir
Log Message:
-----------
Revert "[mlir][openacc] Add legalize data pass for compute operation" (#80710)
Reverts llvm/llvm-project#80351
Breaks some buildbot
Commit: 09531e34eec121e9c2319d58bb9fb7edc304027e
https://github.com/llvm/llvm-project/commit/09531e34eec121e9c2319d58bb9fb7edc304027e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/include/__support/xlocale/__posix_l_fallback.h
Log Message:
-----------
[libc++] Add missing include of <wchar.h> in POSIX locale fallbacks
Commit: 2d416219af5c0091f7887e4d4463e63f5a37d811
https://github.com/llvm/llvm-project/commit/2d416219af5c0091f7887e4d4463e63f5a37d811
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/docs/fstack-arrays.md
Log Message:
-----------
[flang][docs] fix stack arrays docs page name (#80708)
The website renders this `<h1>` as the page title in the index. This
patch updates the title to better fit with the names of the other pages.
See the index here https://flang.llvm.org/docs/
Commit: 04f99bec9af495c2571c9e7dcb14face3cfea4ce
https://github.com/llvm/llvm-project/commit/04f99bec9af495c2571c9e7dcb14face3cfea4ce
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/docs/Status/Cxx20Issues.csv
Log Message:
-----------
[libc++][doc] Updates LWG3346 status. (#80536)
The issue addresses an obvious wording issue. Implementing the
constructors as specified in the synposis, as libc++ did, already
implements the fixed behaviour.
Updates:
- LWG3346 pair and tuple copy and move constructor have backwards
specification
Commit: c5f68a711c62aa1748c03215d95ad9b8c7dff9dd
https://github.com/llvm/llvm-project/commit/c5f68a711c62aa1748c03215d95ad9b8c7dff9dd
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxxabi/src/cxa_exception_storage.cpp
M libcxxabi/src/cxa_guard_impl.h
M libcxxabi/src/cxa_thread_atexit.cpp
M libcxxabi/src/fallback_malloc.cpp
M libcxxabi/test/test_fallback_malloc.pass.cpp
Log Message:
-----------
[libc++abi] Revert temporary workaround to unblock Chrome
This reverts commit 372f7dd48f016, which is not needed by Chrome anymore.
Commit: 5e8626c920a8cffff4e286cd8521528cc80c0a3e
https://github.com/llvm/llvm-project/commit/5e8626c920a8cffff4e286cd8521528cc80c0a3e
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/c.c
M clang/test/AST/Interp/literals.cpp
M clang/test/Sema/objc-bool-constant-conversion.m
Log Message:
-----------
[clang][Interp] Handle ObjCBoolLiteralExprs
Emit them just like the others, but these are integer typed.
Commit: 8f070144e3711ad0e5556eaebc72069c0d869342
https://github.com/llvm/llvm-project/commit/8f070144e3711ad0e5556eaebc72069c0d869342
Author: Billy Laws <blaws05 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
Log Message:
-----------
[AArch64] Fix generated types for ARM64EC variadic entry thunk targets (#80595)
ISel handles filling in x4/x5 when calling variadic functions as they
don't correspond to the 5th/6th X64 arguments but rather to the end of
the shadow space on the stack and the size in bytes of all stack
parameters (ignored and written as 0 for calls from entry thunks).
Will PR a follow up with ISel handling after this is merged.
Commit: 8f4d8945536e9fc45db0e349b91c2f4b3a9cae29
https://github.com/llvm/llvm-project/commit/8f4d8945536e9fc45db0e349b91c2f4b3a9cae29
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[bazel] Port d4ef4b818929732bcb68a536ef2c91891c0ad179
Commit: cb8d83a77c25e529f58eba17bb1ec76069a04e90
https://github.com/llvm/llvm-project/commit/cb8d83a77c25e529f58eba17bb1ec76069a04e90
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
A llvm/test/Transforms/InstCombine/pr80597.ll
Log Message:
-----------
[InstCombine] Fix assertion failure in issue80597 (#80614)
The assertion in #80597 failed when we were trying to compute known bits
of a value in an unreachable BB.
https://github.com/llvm/llvm-project/blob/859b09da08c2a47026ba0a7d2f21b7dca705864d/llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp#L749-L810
In this case, `SignBits` is 30 (deduced from instr info), but `Known` is
`10000101010111010011110101000?0?00000000000000000000000000000000`
(deduced from dom cond). Setting high bits of `lshr Known, 1` will lead
to conflict.
This patch masks out high bits of `Known.Zero` to address this problem.
Fixes #80597.
Commit: b4c7152eb4f7971c111e3e2f60b55892def58d5d
https://github.com/llvm/llvm-project/commit/b4c7152eb4f7971c111e3e2f60b55892def58d5d
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
Log Message:
-----------
Revert "[mlir][vector] Drop inner unit dims for transfer ops on dynamic shapes." (#80712)
Reverts llvm/llvm-project#79752 because it is causing regressions in
downstream projects.
Commit: d0b5d32ce6a6287ddab96b028db534cc1bd9a929
https://github.com/llvm/llvm-project/commit/d0b5d32ce6a6287ddab96b028db534cc1bd9a929
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
[AMDGPU] Fixed byte_sel of v_cvt_f32_bf8/v_cvt_f32_fp8 (#80502)
Opsel bits are swapped. Actual byte select table:
Byte OPSEL
0 0
1 2
2 1
3 3
Commit: ea9276d47efb22e26483bd5ad31c2e249ed9846f
https://github.com/llvm/llvm-project/commit/ea9276d47efb22e26483bd5ad31c2e249ed9846f
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
Log Message:
-----------
[AMDGPU] GlobalISel for f8 conversions (#80503)
Commit: 95fe47ca7e99d999108705640e49075f4c5f39a7
https://github.com/llvm/llvm-project/commit/95fe47ca7e99d999108705640e49075f4c5f39a7
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
A flang/docs/OpenMP-descriptor-management.md
A flang/include/flang/Optimizer/CodeGen/CodeGenOpenMP.h
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
A flang/lib/Optimizer/CodeGen/CodeGenOpenMP.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
A flang/lib/Optimizer/Transforms/OMPDescriptorMapInfoGen.cpp
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
M flang/test/Lower/OpenMP/FIR/array-bounds.f90
M flang/test/Lower/OpenMP/FIR/target.f90
A flang/test/Lower/OpenMP/allocatable-array-bounds.f90
A flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
A flang/test/Transforms/omp-descriptor-map-info-gen.fir
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Target/LLVMIR/omptarget-fortran-allocatable-types-host.mlir
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-array-section-1d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-array-section-3d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-map-scopes.f90
A openmp/libomptarget/test/offloading/fortran/target-map-enter-exit-allocatables.f90
A openmp/libomptarget/test/offloading/fortran/target-map-enter-exit-array.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-scopes-enter-exit.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-target-array-section-3d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-target-scopes.f90
Log Message:
-----------
[Flang][OpenMP] Initial mapping of Fortran pointers and allocatables for target devices (#71766)
This patch seeks to add an initial lowering for pointers and allocatable variables
captured by implicit and explicit map in Flang OpenMP for Target operations that
take map clauses e.g. Target, Target Update. Target Exit/Enter etc.
Currently this is done by treating the type that lowers to a descriptor
(allocatable/pointer/assumed shape) as a map of a record type (e.g. a structure) as that's
effectively what descriptor types lower to in LLVM-IR and what they're represented as
in the Fortran runtime (written in C/C++). The descriptor effectively lowers to a structure
containing scalar and array elements that represent various aspects of the underlying
data being mapped (lower bound, upper bound, extent being the main ones of interest
in most cases) and a pointer to the allocated data. In this current iteration of the mapping
we map the structure in it's entirety and then attach the underlying data pointer and map
the data to the device, this allows most of the required data to be resident on the device
for use. Currently we do not support the addendum (another block of pointer data), but
it shouldn't be too difficult to extend this to support it.
The MapInfoOp generation for descriptor types is primarily handled in an optimization
pass, where it expands BoxType (descriptor types) map captures into two maps, one for
the structure (scalar elements) and the other for the pointer data (base address) and
links them in a Parent <-> Child relationship. The later lowering processes will then treat
them as a conjoined structure with a pointer member map.
Commit: 1a6426067fb33a8a789978f6e229108787a041be
https://github.com/llvm/llvm-project/commit/1a6426067fb33a8a789978f6e229108787a041be
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[workflows] Use /mnt as the build directory on Linux (#80583)
There is more space available on /mnt (~56G) than on / (~30G), and we
are starting to see some of the CI jobs run out of disk space on Linux.
Commit: bdc5a87f158577fd65fde555d956637f3f2b10ac
https://github.com/llvm/llvm-project/commit/bdc5a87f158577fd65fde555d956637f3f2b10ac
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
[GitHub][Workflows] Prevent multiple private email comments (temporarily) (#80648)
Seems the easiest way to quiet this workflow while we figure out the final form of it.
Commit: ee06678a7500d5d8f6aa8d2442389cdb90417c38
https://github.com/llvm/llvm-project/commit/ee06678a7500d5d8f6aa8d2442389cdb90417c38
Author: Anton Korobeynikov <anton at korobeynikov.info>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/email-check.yaml
Log Message:
-----------
Add some clarification to email check message
Commit: 5942868a215ce4dbd927a7f0b06432e1eeaed698
https://github.com/llvm/llvm-project/commit/5942868a215ce4dbd927a7f0b06432e1eeaed698
Author: Mészáros Gergely <gergely at streamhpc.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGGPUBuiltin.cpp
A clang/test/CodeGenCUDA/printf-builtin.cu
A clang/test/CodeGenHIP/printf-builtin.hip
Log Message:
-----------
[clang][AMDGPU][CUDA] Handle __builtin_printf for device printf (#68515)
Previously `__builtin_printf` would result to emitting call to `printf`,
even though directly calling `printf` was translated.
Ref: #68478
Commit: 8fa1e5771bbd080c8a2a11c0579a3082cedbf94a
https://github.com/llvm/llvm-project/commit/8fa1e5771bbd080c8a2a11c0579a3082cedbf94a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/test/CodeGen/X86/avx512-broadcast-unfold.ll
M llvm/test/CodeGen/X86/avx512-bugfix-23634.ll
M llvm/test/CodeGen/X86/avx512-cmp.ll
M llvm/test/CodeGen/X86/avx512-ext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/divrem-by-select.ll
M llvm/test/CodeGen/X86/fp128-cast.ll
M llvm/test/CodeGen/X86/fp128-i128.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vselect-zero.ll
Log Message:
-----------
[X86] Regenerate some vector constant comments missed in recent patches to improve mask predicate handling in addConstantComments
These were missed as filecheck just ignores what's after the end of the check pattern for each line
Commit: 2096e57905a20903f668848ffd11e6130bfa58e2
https://github.com/llvm/llvm-project/commit/2096e57905a20903f668848ffd11e6130bfa58e2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/avx512fp16-fma-intrinsics.ll
M llvm/test/CodeGen/X86/avx512fp16-mov.ll
M llvm/test/CodeGen/X86/stack-folding-fp-avx512fp16.ll
Log Message:
-----------
[X86] addConstantComments - add FP16 MOVSH asm comments support
Commit: dd70aef05a86bb0c1e04c49cc1bd0457ca362ce3
https://github.com/llvm/llvm-project/commit/dd70aef05a86bb0c1e04c49cc1bd0457ca362ce3
Author: Alex Lorenz <arphaman at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/test/CodeGen/X86/swift-async-win64.ll
Log Message:
-----------
[x86_64][windows][swift] do not use Swift async extended frame for wi… (#80468)
…ndows x86_64
targets that use windows 64 prologue
Windows x86_64 stack frame layout is currently not compatible with
Swift's async extended frame, which reserves the slot right below RBP
(RBP-8) for the async context pointer, as it doesn't account for the
fact that a stack object in a win64 frame can be allocated at the same
location. This can cause issues at runtime, for instance, Swift's TCA
test code has functions that fail because of this issue, as they spill a
value to that slack slot, which then gets overwritten by a store into
address returned by the @llvm.swift.async.context.addr() intrinsic (that
ends up being RBP - 8), leading to an incorrect value being used at a
later point when that stack slot is being read from again. This change
drops the use of async extended frame for windows x86_64 subtargets and
instead uses the x32 based approach of allocating a separate stack slot
for the stored async context pointer.
Additionally, LLDB which is the primary consumer of the extended frame
makes assumptions like checking for a saved previous frame pointer at
the current frame pointer address, which is also incompatible with the
windows x86_64 frame layout, as the previous frame pointer is not
guaranteed to be stored at the current frame pointer address. Therefore
the extended frame layout can be turned off to fix the current
miscompile without introducing regression into LLDB for windows x86_64
as it already doesn't work correctly. I am still investigating what
should be made for LLDB to support using an allocated stack slot to
store the async frame context instead of being located at RBP - 8 for
windows.
Commit: 930996e9e442d69a321cd5c945543d37c97f4c0e
https://github.com/llvm/llvm-project/commit/930996e9e442d69a321cd5c945543d37c97f4c0e
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
Log Message:
-----------
[ValueTracking][NFC] Pass `SimplifyQuery` to `computeKnownFPClass` family (#80657)
This patch refactors the interface of the `computeKnownFPClass` family
to pass `SimplifyQuery` directly.
The motivation of this patch is to compute known fpclass with
`DomConditionCache`, which was introduced by
https://github.com/llvm/llvm-project/pull/73662. With
`DomConditionCache`, we can do more optimization with context-sensitive
information.
Example (extracted from
[fmt/format.h](https://github.com/fmtlib/fmt/blob/e17bc67547a66cdd378ca6a90c56b865d30d6168/include/fmt/format.h#L3555-L3566)):
```
define float @test(float %x, i1 %cond) {
%i32 = bitcast float %x to i32
%cmp = icmp slt i32 %i32, 0
br i1 %cmp, label %if.then1, label %if.else
if.then1:
%fneg = fneg float %x
br label %if.end
if.else:
br i1 %cond, label %if.then2, label %if.end
if.then2:
br label %if.end
if.end:
%value = phi float [ %fneg, %if.then1 ], [ %x, %if.then2 ], [ %x, %if.else ]
%ret = call float @llvm.fabs.f32(float %value)
ret float %ret
}
```
We can prove the signbit of `%value` is always zero. Then the fabs can
be eliminated.
Commit: 214536b0d8b68f826589600472e28bbb903d6d7a
https://github.com/llvm/llvm-project/commit/214536b0d8b68f826589600472e28bbb903d6d7a
Author: Mats Petersson <mats.petersson at arm.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/test/Driver/target-cpu-features.f90
Log Message:
-----------
Fix broken ARM processor features test (#80717)
This should fix failed build bots, so pushing before Windows build is done.
Commit: 032a70ee1183dba5b942778f855e1d58244e8077
https://github.com/llvm/llvm-project/commit/032a70ee1183dba5b942778f855e1d58244e8077
Author: stephenpeckham <118857872+stephenpeckham at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
Log Message:
-----------
[NFC] Fix typo (#80703)
Commit: d00e6d07b18dbc80b843e332a66d2777c6564523
https://github.com/llvm/llvm-project/commit/d00e6d07b18dbc80b843e332a66d2777c6564523
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/test/Dialect/SparseTensor/external.mlir
A mlir/test/Dialect/SparseTensor/torch_linalg.mlir
Log Message:
-----------
[mlir][sparse] refine sparse assembler strategy (#80521)
Rewrite *all* public methods, making original internal, private methods,
and exposing wrappers under the original name. This works a bit better
in practice (when combined with c-interface mechanism of torch-mlir for
example).
Commit: ac585ab71470d4f20c96a95b49e852ee1c967003
https://github.com/llvm/llvm-project/commit/ac585ab71470d4f20c96a95b49e852ee1c967003
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
Log Message:
-----------
[lldb] Remove unused private TypeCategoryMap methods (NFC) (#80602)
Commit: 0c02ea05c8414e72339e2521d1fdae54e91569bb
https://github.com/llvm/llvm-project/commit/0c02ea05c8414e72339e2521d1fdae54e91569bb
Author: Dave Lee <davelee.com at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
Log Message:
-----------
[lldb] Cleanup regex in libcxx formatters (NFC) (#80618)
I noticed a number of regex for libcxx formatters use an unnecessary regex grouping.
This change removes those parentheses.
Commit: 0bf165e383ac9c58dcb1764aef9f35334afa0cc7
https://github.com/llvm/llvm-project/commit/0bf165e383ac9c58dcb1764aef9f35334afa0cc7
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add support for RISC-V Pointer Masking (#79929)
This patch implements the v0.8.1 specification. This patch reports
version 0.8 in llvm since `RISCVISAInfo::ExtensionVersion` only has a
`Major` and `Minor` version number. This patch includes includes support
of the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make
up RISC-V pointer masking.
All of these extensions require emitting attribute containing correct
`march` string.
`Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a 2-bit WARL field (PMM).
The extension does not specify how PMM is set, and therefore this patch
does not need to address this. One example of how it *could* be set is
using the Zicsr instructions to update the PMM bits of the described
registers.
The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf
Commit: 9805c051f7d3a09a629c51461b49f8070c01de62
https://github.com/llvm/llvm-project/commit/9805c051f7d3a09a629c51461b49f8070c01de62
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[workflows] Close issues used for backports once the PR has been created (#80394)
This will allow us to track the state of the backport request in the PR,
rather than in the issue. The state updates for PRs can be automated, so
this will save us some triage work.
Commit: 37462944513731af2743d95e5dd40bdbeefd6460
https://github.com/llvm/llvm-project/commit/37462944513731af2743d95e5dd40bdbeefd6460
Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
Date: 2024-02-06 (Tue, 06 Feb 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/cos-1.ll
Log Message:
-----------
[Transforms] Add more cos combinations to SimplifyLibCalls and InstCombine (#79699)
Add cos(fabs(x)) -> cos(x) and cos(copysign(x, y)) -> cos(x).
Commit: 93fd05c0891caa8c68cb37b64217467a0ef60412
https://github.com/llvm/llvm-project/commit/93fd05c0891caa8c68cb37b64217467a0ef60412
Author: Andrew Gozillon <Andrew.Gozillon at amd.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
Log Message:
-----------
[Flang][OpenMP] Attempt to make map-types-and-sizes.f90 test more agnostic to other architectures
This test was updated by me recently, however, the newly
added CHECK-LABEL checks are breaking one of the RHEL
PowerPC buildbots as the functions appear to be generated
slightly different (in this case added attributes I think).
Commit: 64a317ad0765a2b3748d2b74b9a0d4738250787a
https://github.com/llvm/llvm-project/commit/64a317ad0765a2b3748d2b74b9a0d4738250787a
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
Log Message:
-----------
[libc++][NFC] Fix typo in comment
Commit: 22544e2a54370a3c0b12765981c312f9ec04f1cc
https://github.com/llvm/llvm-project/commit/22544e2a54370a3c0b12765981c312f9ec04f1cc
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/test/Driver/func-attr-fast-math.f90
Log Message:
-----------
[flang] Set fast math related function attributes for -Ofast/-ffast-math (#79301)
The implemented logic matches the logic used for Clang in emitting these
attributes. Although it's hoped that function attributes won't be needed
in the future (vs using fast math flags in individual IR instructions),
there are codegen differences currently with/without these attributes,
as can be seen in issues like #79257 or by hacking Clang to avoid
producing these attributes and observing codegen changes.
Commit: b99163fe8feeacba7797d5479bbcd5d8f327dd2d
https://github.com/llvm/llvm-project/commit/b99163fe8feeacba7797d5479bbcd5d8f327dd2d
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVFeatures.td
Log Message:
-----------
[RISCV] Fix description of Ssstrict to have a closing parenthesis.
Commit: dd22140e21f2ef51cf031354966a3d41c191c6e7
https://github.com/llvm/llvm-project/commit/dd22140e21f2ef51cf031354966a3d41c191c6e7
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
Log Message:
-----------
[Profile][Windows] Drop extern for __buildid. (#80700)
Commit: ff46cfe3a387f289d5cac7ed1e8f3f7b5a3c4ad3
https://github.com/llvm/llvm-project/commit/ff46cfe3a387f289d5cac7ed1e8f3f7b5a3c4ad3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-05 (Mon, 05 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
A .github/workflows/email-check.yaml
M .github/workflows/llvm-project-tests.yml
M .github/workflows/pr-code-format.yml
M .github/workflows/spirv-tests.yml
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/test/X86/linux-orc.s
A bolt/test/X86/phdr-out-of-order.test
M clang-tools-extra/clang-apply-replacements/tool/ClangApplyReplacementsMain.cpp
M clang-tools-extra/clang-tidy/add_new_check.py
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/DynamicStaticInitializersCheck.h
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.cpp
M clang-tools-extra/clang-tidy/bugprone/SuspiciousIncludeCheck.h
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/google/GlobalNamesInHeadersCheck.h
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.cpp
M clang-tools-extra/clang-tidy/google/UnnamedNamespaceInHeaderCheck.h
M clang-tools-extra/clang-tidy/llvm/HeaderGuardCheck.h
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.cpp
M clang-tools-extra/clang-tidy/misc/DefinitionsInHeadersCheck.h
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.cpp
M clang-tools-extra/clang-tidy/misc/UseAnonymousNamespaceCheck.h
M clang-tools-extra/clang-tidy/readability/IdentifierNamingCheck.cpp
M clang-tools-extra/clang-tidy/utils/HeaderGuard.cpp
M clang-tools-extra/clang-tidy/utils/HeaderGuard.h
M clang-tools-extra/clangd/SemanticHighlighting.cpp
M clang-tools-extra/clangd/unittests/SemanticHighlightingTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/bugprone/suspicious-include.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/prefer-member-initializer.rst
M clang-tools-extra/docs/clang-tidy/checks/google/build-namespaces.rst
M clang-tools-extra/docs/clang-tidy/checks/google/global-names-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/llvm/header-guard.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/definitions-in-headers.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/unused-using-decls.rst
M clang-tools-extra/docs/clang-tidy/checks/misc/use-anonymous-namespace.rst
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/no.yaml
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/format_header/yes.yaml
A clang-tools-extra/test/clang-apply-replacements/format-header.cpp
M clang-tools-extra/test/clang-tidy/checkers/bugprone/implicit-widening-of-multiplication-result-char.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init.cpp
M clang/docs/ClangFormatStyleOptions.rst
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticDriverKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Basic/riscv_vector.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Format/Format.h
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Support/RISCVVIntrinsicUtils.h
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/Interp/InterpBuiltin.cpp
M clang/lib/AST/Interp/PrimType.h
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Analysis/ReachableCode.cpp
M clang/lib/Basic/Sarif.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Targets/X86.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGGPUBuiltin.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/lib/CodeGen/ItaniumCXXABI.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/CommonArgs.h
M clang/lib/Driver/ToolChains/Flang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/Format.cpp
M clang/lib/Format/TokenAnnotator.cpp
M clang/lib/Frontend/TextDiagnostic.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaRISCVVectorLookup.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Checkers/ArrayBoundCheckerV2.cpp
M clang/lib/StaticAnalyzer/Checkers/BuiltinFunctionChecker.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
A clang/test/AST/Interp/atomic.c
A clang/test/AST/Interp/atomic.cpp
M clang/test/AST/Interp/builtins.cpp
M clang/test/AST/Interp/c.c
M clang/test/AST/Interp/complex.cpp
M clang/test/AST/Interp/cxx98.cpp
M clang/test/AST/Interp/literals.cpp
A clang/test/AST/ast-dump-pack-indexing-crash.cpp
M clang/test/Analysis/builtin-functions.cpp
A clang/test/Analysis/html_diagnostics/counter.c
M clang/test/Analysis/out-of-bounds-diagnostics.c
A clang/test/Analysis/out-of-bounds-notes.c
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.meaning.general/p3.cpp
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/drs/dr7xx.cpp
M clang/test/CXX/temp/temp.decls/temp.class/temp.mem.func/p1.cpp
A clang/test/CXX/temp/temp.names/p5.cpp
M clang/test/CXX/temp/temp.spec/part.spec.cpp
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg6ei8.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vget.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vset.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsoxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg5e64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg6e64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg7e64.c
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M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vssseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsuxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vluxseg8ei8.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfncvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwcvtbf16.c
A clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfwmaccbf16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vloxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg2e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg3e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg4e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg5e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg6e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg7e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e16ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e32ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e64ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlseg8e8ff.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg2e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg3e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg4e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg5e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg6e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg7e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vlsseg8e8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg2ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg3ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg4ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg5ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg6ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg7ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei16.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei32.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei64.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vluxseg8ei8.c
M clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/rvv-tuple-type.c
M clang/test/CodeGen/aarch64-inline-asm.c
M clang/test/CodeGen/fp128_complex.c
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/CodeGenCUDA/amdgpu-code-object-version-linking.cu
M clang/test/CodeGenCUDA/amdgpu-code-object-version.cu
M clang/test/CodeGenCUDA/amdgpu-workgroup-size.cu
A clang/test/CodeGenCUDA/printf-builtin.cu
M clang/test/CodeGenCXX/dynamic-cast-address-space.cpp
A clang/test/CodeGenCXX/dynamic-cast-dead.cpp
M clang/test/CodeGenCXX/dynamic-cast.cpp
A clang/test/CodeGenHIP/printf-builtin.hip
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M clang/test/CoverageMapping/if.cpp
A clang/test/Driver/Inputs/rocm/amdgcn/bitcode/oclc_abi_version_600.bc
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
A clang/test/Driver/basic-block-address-map.c
M clang/test/Driver/hip-code-object-version.hip
M clang/test/Driver/hip-device-libs.hip
M clang/test/Driver/hip-options.hip
M clang/test/Driver/mips-features.c
A clang/test/Driver/sparc64-codemodel.c
M clang/test/Frontend/fixed_point_bit_widths.c
M clang/test/Misc/warning-flags.c
M clang/test/Preprocessor/aarch64-target-features.c
A clang/test/Preprocessor/has_builtin_cpuid.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/aarch64-sme-func-attrs.c
M clang/test/Sema/atomic-expr.c
M clang/test/Sema/attr-aligned.c
M clang/test/Sema/auto-type.c
M clang/test/Sema/inline-asm-validate-aarch64.c
M clang/test/Sema/objc-bool-constant-conversion.m
M clang/test/Sema/rvv-required-features-invalid.c
M clang/test/Sema/warn-cast-qual.c
A clang/test/SemaCXX/coroutine-unreachable-warning.cpp
M clang/test/SemaCXX/cxx2c-pack-indexing.cpp
M clang/test/SemaCXX/function-type-qual.cpp
A clang/test/SemaCXX/libstdcxx_is_nothrow_convertible_hack.cpp
M clang/test/SemaCXX/pr72025.cpp
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave32.cl
M clang/test/SemaOpenCL/builtins-amdgcn-error-wave64.cl
M clang/test/SemaTemplate/class-template-spec.cpp
M clang/test/SemaTemplate/concepts-recovery-expr.cpp
A clang/test/SemaTemplate/default-parm-init.cpp
M clang/unittests/Format/ConfigParseTest.cpp
M clang/unittests/Format/FormatTest.cpp
M clang/utils/TableGen/RISCVVEmitter.cpp
M clang/utils/perf-training/CMakeLists.txt
M clang/utils/perf-training/perf-helper.py
M compiler-rt/lib/builtins/cpu_model/aarch64/fmv/apple.inc
M compiler-rt/lib/builtins/cpu_model/x86.c
M compiler-rt/lib/builtins/i386/chkstk.S
M compiler-rt/lib/builtins/x86_64/chkstk.S
M compiler-rt/lib/profile/InstrProfilingPlatformWindows.c
M flang/docs/AliasingAnalysisFIR.md
M flang/docs/FIRArrayOperations.md
M flang/docs/FlangDriver.md
M flang/docs/HighLevelFIR.md
M flang/docs/OpenACC-descriptor-management.md
A flang/docs/OpenMP-descriptor-management.md
M flang/docs/Overview.md
M flang/docs/ParameterizedDerivedTypes.md
M flang/docs/PolymorphicEntities.md
M flang/docs/ProcedurePointer.md
M flang/docs/conf.py
M flang/docs/fstack-arrays.md
M flang/docs/index.md
M flang/include/flang/Lower/PFTBuilder.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
A flang/include/flang/Optimizer/CodeGen/CodeGenOpenMP.h
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/include/flang/Optimizer/Transforms/Passes.h
M flang/include/flang/Optimizer/Transforms/Passes.td
M flang/include/flang/Tools/CLOptions.inc
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Frontend/CompilerInvocation.cpp
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Lower/PFTBuilder.cpp
M flang/lib/Optimizer/Analysis/AliasAnalysis.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/CMakeLists.txt
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
A flang/lib/Optimizer/CodeGen/CodeGenOpenMP.cpp
M flang/lib/Optimizer/Dialect/FIROps.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/CMakeLists.txt
M flang/lib/Optimizer/Transforms/FunctionAttr.cpp
A flang/lib/Optimizer/Transforms/OMPDescriptorMapInfoGen.cpp
M flang/lib/Parser/preprocessor.cpp
A flang/test/Analysis/AliasAnalysis/alias-analysis-8.fir
A flang/test/Driver/aarch64-outline-atomics.f90
M flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
A flang/test/Driver/func-attr-fast-math.f90
M flang/test/Driver/target-cpu-features.f90
A flang/test/Fir/OpenACC/propagate-attr-folding.fir
M flang/test/Fir/convert-to-llvm-openmp-and-fir.fir
M flang/test/Integration/OpenMP/map-types-and-sizes.f90
A flang/test/Integration/aarch64-outline-atomics.f90
M flang/test/Lower/AMD/code-object-version.f90
M flang/test/Lower/HLFIR/array-ctor-character.f90
A flang/test/Lower/Intrinsics/acosd.f90
A flang/test/Lower/Intrinsics/asind.f90
A flang/test/Lower/Intrinsics/atan2d.f90
A flang/test/Lower/Intrinsics/atan2pi.f90
M flang/test/Lower/Intrinsics/atand.f90
A flang/test/Lower/Intrinsics/atanpi.f90
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/FIR/array-bounds.f90
M flang/test/Lower/OpenMP/FIR/target.f90
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
A flang/test/Lower/OpenMP/allocatable-array-bounds.f90
A flang/test/Lower/OpenMP/allocatable-map.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
M flang/test/Lower/allocatable-polymorphic.f90
M flang/test/Lower/nullify-polymorphic.f90
A flang/test/Transforms/omp-descriptor-map-info-gen.fir
M libc/CMakeLists.txt
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/prepare_libc_gpu_build.cmake
M libc/config/linux/aarch64/entrypoints.txt
M libc/config/linux/api.td
M libc/config/linux/riscv/entrypoints.txt
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/index.rst
A libc/docs/libc_search.rst
M libc/docs/math/index.rst
M libc/docs/stdbit.rst
M libc/include/CMakeLists.txt
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/include/llvm-libc-types/CMakeLists.txt
A libc/include/llvm-libc-types/float128.h
M libc/spec/posix.td
M libc/spec/spec.td
M libc/spec/stdc.td
M libc/src/__support/CMakeLists.txt
M libc/src/__support/CPP/expected.h
M libc/src/__support/FPUtil/CMakeLists.txt
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
A libc/src/__support/intrusive_list.h
M libc/src/__support/macros/properties/CMakeLists.txt
M libc/src/__support/macros/properties/float.h
M libc/src/math/CMakeLists.txt
A libc/src/math/ceilf128.h
A libc/src/math/floorf128.h
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/ceilf128.cpp
A libc/src/math/generic/floorf128.cpp
A libc/src/math/generic/roundf128.cpp
A libc/src/math/generic/truncf128.cpp
A libc/src/math/roundf128.h
A libc/src/math/truncf128.h
M libc/src/search/CMakeLists.txt
A libc/src/search/insque.cpp
A libc/src/search/insque.h
A libc/src/search/remque.cpp
A libc/src/search/remque.h
M libc/src/stdbit/stdc_leading_ones_uc.cpp
M libc/src/stdbit/stdc_leading_ones_uc.h
M libc/src/stdbit/stdc_leading_ones_ul.cpp
M libc/src/stdbit/stdc_leading_ones_ul.h
M libc/src/stdbit/stdc_leading_ones_ull.cpp
M libc/src/stdbit/stdc_leading_ones_ull.h
M libc/src/stdbit/stdc_leading_ones_us.cpp
M libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/src/sys/epoll/linux/epoll_wait.cpp
M libc/startup/gpu/CMakeLists.txt
M libc/startup/gpu/amdgpu/CMakeLists.txt
M libc/startup/gpu/nvptx/CMakeLists.txt
M libc/test/IntegrationTest/CMakeLists.txt
M libc/test/include/stdbit_test.cpp
M libc/test/src/CMakeLists.txt
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/ceilf128_test.cpp
A libc/test/src/math/smoke/floorf128_test.cpp
A libc/test/src/math/smoke/roundf128_test.cpp
A libc/test/src/math/smoke/truncf128_test.cpp
M libc/test/src/search/CMakeLists.txt
A libc/test/src/search/insque_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx20Issues.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__atomic/atomic_sync.h
M libcxx/include/__bit_reference
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__locale
A libcxx/include/__locale_dir/locale_base_api.h
A libcxx/include/__locale_dir/locale_base_api/android.h
A libcxx/include/__locale_dir/locale_base_api/fuchsia.h
A libcxx/include/__locale_dir/locale_base_api/ibm.h
A libcxx/include/__locale_dir/locale_base_api/musl.h
A libcxx/include/__locale_dir/locale_base_api/newlib.h
A libcxx/include/__locale_dir/locale_base_api/openbsd.h
A libcxx/include/__locale_dir/locale_base_api/win32.h
M libcxx/include/__memory/temporary_buffer.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
R libcxx/include/__support/android/locale_bionic.h
R libcxx/include/__support/fuchsia/xlocale.h
R libcxx/include/__support/ibm/xlocale.h
R libcxx/include/__support/musl/xlocale.h
R libcxx/include/__support/newlib/xlocale.h
R libcxx/include/__support/openbsd/xlocale.h
R libcxx/include/__support/win32/locale_win32.h
M libcxx/include/__support/xlocale/__posix_l_fallback.h
M libcxx/include/__thread/support/c11.h
M libcxx/include/__type_traits/is_nothrow_convertible.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/scoped_allocator
M libcxx/include/semaphore
M libcxx/include/string
M libcxx/include/valarray
M libcxx/include/vector
M libcxx/include/version
M libcxx/src/locale.cpp
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.gslice.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.indirect.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.mask.array/get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/assert.get.pass.cpp
A libcxx/test/libcxx/numerics/numarray/class.slice.array/get.pass.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/std/atomics/atomics.types.generic/atomics.types.float/load.pass.cpp
A libcxx/test/std/containers/sequences/vector/vector.modifiers/destory_elements.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/filesystem.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/fstream.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/iomanip.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/mutex.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/and_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/divide_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/minus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/modulo_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/or_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/plus_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_left_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/shift_right_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/times_valarray.pass.cpp
M libcxx/test/std/numerics/numarray/template.valarray/valarray.cassign/xor_valarray.pass.cpp
A libcxx/test/std/thread/thread.semaphore/lost_wakeup.pass.cpp
M libcxx/test/std/utilities/allocator.adaptor/allocator.adaptor.cnstr/allocs.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.signed_integral.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.unsigned_integral.pass.cpp
M libcxx/test/support/count_new.h
M libcxx/utils/generate_feature_test_macro_components.py
M libcxxabi/src/cxa_exception_storage.cpp
M libcxxabi/src/cxa_guard_impl.h
M libcxxabi/src/cxa_thread_atexit.cpp
M libcxxabi/src/fallback_malloc.cpp
M libcxxabi/src/private_typeinfo.cpp
M libcxxabi/test/test_fallback_malloc.pass.cpp
M lld/ELF/Arch/AMDGPU.cpp
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/ELF/amdgpu-tid.s
M lld/test/ELF/linkerscript/insert-before.test
A lld/test/ELF/lto/basic-block-address-map.ll
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
M lld/wasm/InputFiles.cpp
M lldb/docs/use/python-reference.rst
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/include/lldb/DataFormatters/FormatCache.h
M lldb/include/lldb/DataFormatters/TypeCategoryMap.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/source/DataFormatters/FormatCache.cpp
M lldb/source/Plugins/Language/CPlusPlus/CPlusPlusLanguage.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/source/Utility/ConstString.cpp
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
M llvm/docs/AdvancedBuilds.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/SecurityTransparencyReports.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/ADT/StringMap.h
M llvm/include/llvm/Analysis/CGSCCPassManager.h
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/MIRPrinter.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/TargetRegisterInfo.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
A llvm/include/llvm/IR/Analysis.h
M llvm/include/llvm/IR/PassManager.h
M llvm/include/llvm/IR/PassManagerInternal.h
M llvm/include/llvm/MC/MCObjectStreamer.h
M llvm/include/llvm/MC/MCStreamer.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/Object/Wasm.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h
M llvm/include/llvm/ProfileData/InstrProfReader.h
M llvm/include/llvm/Support/AMDGPUMetadata.h
M llvm/include/llvm/Support/ScopedPrinter.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/TextAPI/Utils.h
M llvm/include/llvm/Transforms/Scalar/LoopPassManager.h
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/InstructionSimplify.cpp
M llvm/lib/Analysis/LoopInfo.cpp
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/Bitcode/Writer/BitcodeWriter.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/Utils.cpp
M llvm/lib/CodeGen/MIRParser/MIRParser.cpp
M llvm/lib/CodeGen/MIRPrintingPass.cpp
M llvm/lib/CodeGen/MachineBlockPlacement.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/MachinePipeliner.cpp
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/RDFGraph.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
M llvm/lib/ExecutionEngine/RuntimeDyld/RuntimeDyldELF.cpp
M llvm/lib/FileCheck/FileCheck.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
M llvm/lib/MC/MCAsmStreamer.cpp
M llvm/lib/MC/MCObjectStreamer.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/Object/COFFModuleDefinition.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/StandardInstrumentations.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/lib/ProfileData/InstrProfReader.cpp
M llvm/lib/Support/FormatVariadic.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Support/StringMap.cpp
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
M llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUHSAMetadataStreamer.h
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULibCalls.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPromoteAlloca.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUTargetStreamer.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMLegalizerInfo.cpp
M llvm/lib/Target/ARM/ARMRegisterBankInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmTypeCheck.cpp
M llvm/lib/Target/X86/MCTargetDesc/X86InstComments.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.h
M llvm/lib/Target/X86/X86ISelLoweringCall.cpp
M llvm/lib/Target/X86/X86InstrAVX512.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/TextAPI/Utils.cpp
M llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
M llvm/lib/Transforms/InstCombine/InstCombineSimplifyDemanded.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyIndVar.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlan.h
M llvm/lib/Transforms/Vectorize/VPlanAnalysis.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/test/Analysis/AliasSet/memloc-vscale.ll
M llvm/test/Analysis/BasicAA/assume-index-positive.ll
M llvm/test/Analysis/BasicAA/index-size.ll
M llvm/test/Analysis/BasicAA/noalias-bugs.ll
M llvm/test/Analysis/BasicAA/vscale.ll
M llvm/test/Analysis/BlockFrequencyInfo/basic.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_loop_crash.ll
M llvm/test/Analysis/BlockFrequencyInfo/irreducible_pgo.ll
M llvm/test/Analysis/BlockFrequencyInfo/loop_with_invoke.ll
M llvm/test/Analysis/BlockFrequencyInfo/loops_with_profile_info.ll
M llvm/test/Analysis/CostModel/RISCV/gep.ll
A llvm/test/Analysis/CostModel/RISCV/reduce-fmaximum.ll
A llvm/test/Analysis/CostModel/RISCV/reduce-fminimum.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-f64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i32-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i64-stride-8.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-2.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-3.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-4.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-5.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-6.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-7.ll
M llvm/test/Analysis/CostModel/X86/interleaved-load-i8-stride-8.ll
M llvm/test/Analysis/Dominators/2007-01-14-BreakCritEdges.ll
M llvm/test/Analysis/Dominators/2007-07-12-SplitBlock.ll
M llvm/test/Analysis/Dominators/invoke.ll
M llvm/test/Analysis/FunctionPropertiesAnalysis/matmul.ll
M llvm/test/Analysis/IVUsers/deep_recursion_in_scev.ll
M llvm/test/Analysis/LazyCallGraph/non-leaf-intrinsics.ll
M llvm/test/Analysis/LazyValueAnalysis/invalidation.ll
M llvm/test/Analysis/LoopAccessAnalysis/forked-pointers.ll
M llvm/test/Analysis/LoopAccessAnalysis/underlying-objects-2.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/LoopnestFixedSize.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost-m32.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/compute-cost.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/loads-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/matvecmul.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/single-store.ll
M llvm/test/Analysis/LoopCacheAnalysis/PowerPC/stencil.ll
M llvm/test/Analysis/LoopCacheAnalysis/compute-cost.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-complex.ll
M llvm/test/Analysis/LoopInfo/annotated-parallel-simple.ll
M llvm/test/Analysis/LoopNestAnalysis/duplicate-successors.ll
M llvm/test/Analysis/LoopNestAnalysis/imperfectnest.ll
M llvm/test/Analysis/LoopNestAnalysis/infinite.ll
M llvm/test/Analysis/LoopNestAnalysis/perfectnest.ll
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/always-uniform-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/MIR/hidden-diverge-gmir.mir
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/atomics.ll
M llvm/test/Assembler/incomplete-ir-declarations.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global-pic.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-xclass-copies.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
M llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
M llvm/test/CodeGen/AArch64/PBQP-csr.ll
M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
M llvm/test/CodeGen/AArch64/add-i256.ll
M llvm/test/CodeGen/AArch64/addrsig-macho.ll
M llvm/test/CodeGen/AArch64/align-down.ll
M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-bad-outline.mir
M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
M llvm/test/CodeGen/AArch64/arm64-ldp.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
M llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
M llvm/test/CodeGen/AArch64/arm64-zip.ll
M llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
A llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/compute-call-frame-size-unreachable-pass.ll
M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
M llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
M llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
M llvm/test/CodeGen/AArch64/divrem.ll
M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
M llvm/test/CodeGen/AArch64/fmov-imm-licm.ll
M llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
M llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
M llvm/test/CodeGen/AArch64/irg-nomem.mir
M llvm/test/CodeGen/AArch64/ldradr.ll
M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
M llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
M llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
M llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
M llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
M llvm/test/CodeGen/AArch64/machine-scheduler.mir
M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
M llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
M llvm/test/CodeGen/AArch64/merge-store.ll
M llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
M llvm/test/CodeGen/AArch64/neon-mov.ll
M llvm/test/CodeGen/AArch64/nontemporal-load.ll
M llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
M llvm/test/CodeGen/AArch64/sadd_sat.ll
M llvm/test/CodeGen/AArch64/sadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/sched-movprfx.ll
M llvm/test/CodeGen/AArch64/settag-merge.mir
M llvm/test/CodeGen/AArch64/sign-return-address-tailcall.ll
M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
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M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
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M llvm/test/CodeGen/AArch64/stack-probing-64k.ll
M llvm/test/CodeGen/AArch64/stack-tagging-cfi.ll
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M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
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M llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
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M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
M llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
M llvm/test/CodeGen/AArch64/sve-fp.ll
M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
M llvm/test/CodeGen/AArch64/sve-gep.ll
M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
M llvm/test/CodeGen/AArch64/sve-int-arith.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
M llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
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M llvm/test/CodeGen/AArch64/sve-ld1r.ll
M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
M llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
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M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
M llvm/test/CodeGen/AArch64/sve-setcc.ll
M llvm/test/CodeGen/AArch64/sve-split-load.ll
M llvm/test/CodeGen/AArch64/sve-split-store.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll
M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
M llvm/test/CodeGen/AArch64/sve-trunc.ll
M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
M llvm/test/CodeGen/AArch64/sve-varargs-callee-broken.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-ld1-single.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-loads.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll
M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
M llvm/test/CodeGen/AArch64/taildup-addrtaken.mir
M llvm/test/CodeGen/AArch64/tailmerging_in_mbp.ll
M llvm/test/CodeGen/AArch64/tiny-model-pic.ll
M llvm/test/CodeGen/AArch64/tiny-model-static.ll
M llvm/test/CodeGen/AArch64/uadd_sat.ll
M llvm/test/CodeGen/AArch64/uadd_sat_plus.ll
M llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
M llvm/test/CodeGen/AArch64/usub_sat.ll
M llvm/test/CodeGen/AArch64/usub_sat_plus.ll
M llvm/test/CodeGen/AArch64/usub_sat_vec.ll
M llvm/test/CodeGen/AArch64/v3f-to-int.ll
M llvm/test/CodeGen/AArch64/win-catchpad-nested-cxx.ll
M llvm/test/CodeGen/AArch64/wineh-frame5.mir
M llvm/test/CodeGen/AArch64/wineh-frame6.mir
M llvm/test/CodeGen/AArch64/wineh-frame7.mir
M llvm/test/CodeGen/AArch64/wineh-frame8.mir
M llvm/test/CodeGen/AArch64/wineh5.mir
M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
M llvm/test/CodeGen/AArch64/zero-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/implicit-kernarg-backend-usage-global-isel.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-divrem.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/branch-relaxation-debug-info.mir
M llvm/test/CodeGen/AMDGPU/call-graph-register-usage.ll
M llvm/test/CodeGen/AMDGPU/codegen-internal-only-func.ll
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
M llvm/test/CodeGen/AMDGPU/div_i128.ll
A llvm/test/CodeGen/AMDGPU/div_v2i128.ll
M llvm/test/CodeGen/AMDGPU/elf-header-osabi.ll
M llvm/test/CodeGen/AMDGPU/enable-scratch-only-dynamic-stack.ll
M llvm/test/CodeGen/AMDGPU/fsub-as-fneg-src-modifier.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fadd.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_scan_fsub.ll
M llvm/test/CodeGen/AMDGPU/implicit-kernarg-backend-usage.ll
M llvm/test/CodeGen/AMDGPU/implicitarg-offset-attributes.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2b.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.iglp.opt.single.2c.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rcp.ll
M llvm/test/CodeGen/AMDGPU/llvm.get.fpmode.ll
M llvm/test/CodeGen/AMDGPU/load-global-f32.ll
M llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-flat-with-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-global-load-store.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
M llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf-unsupported.ll
M llvm/test/CodeGen/AMDGPU/opencl-printf.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-array-aggregate.ll
M llvm/test/CodeGen/AMDGPU/promote-alloca-memset.ll
M llvm/test/CodeGen/AMDGPU/recursion.ll
M llvm/test/CodeGen/AMDGPU/resource-usage-dead-function.ll
M llvm/test/CodeGen/AMDGPU/sched-crash-dbg-value.mir
M llvm/test/CodeGen/AMDGPU/sdwa-scalar-ops.mir
A llvm/test/CodeGen/AMDGPU/spill-sgpr-used-for-exec-copy.mir
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-any.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-off.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-all-on.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-off-2.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-1.ll
M llvm/test/CodeGen/AMDGPU/tid-mul-func-xnack-any-on-2.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-not-supported.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-off.ll
M llvm/test/CodeGen/AMDGPU/tid-one-func-xnack-on.ll
M llvm/test/CodeGen/AMDGPU/whole-wave-register-copy.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
M llvm/test/CodeGen/ARM/2008-03-07-RegScavengerAssert.ll
M llvm/test/CodeGen/ARM/2009-07-18-RewriterBug.ll
A llvm/test/CodeGen/ARM/GlobalISel/fpenv.ll
M llvm/test/CodeGen/ARM/Windows/wineh-basic.ll
M llvm/test/CodeGen/ARM/aes-erratum-fix.ll
M llvm/test/CodeGen/ARM/aliases.ll
M llvm/test/CodeGen/ARM/arm-half-promote.ll
M llvm/test/CodeGen/ARM/code-placement.ll
M llvm/test/CodeGen/ARM/constant-island-movwt.mir
M llvm/test/CodeGen/ARM/cortex-a57-misched-basic.ll
M llvm/test/CodeGen/ARM/debug-info-blocks.ll
M llvm/test/CodeGen/ARM/debug-info-d16-reg.ll
M llvm/test/CodeGen/ARM/debug-info-s16-reg.ll
M llvm/test/CodeGen/ARM/dwarf-eh.ll
M llvm/test/CodeGen/ARM/fp16-args.ll
M llvm/test/CodeGen/ARM/fp16-instructions.ll
M llvm/test/CodeGen/ARM/fp16-promote.ll
M llvm/test/CodeGen/ARM/ldrcppic.ll
M llvm/test/CodeGen/ARM/llvm.exp10.ll
M llvm/test/CodeGen/ARM/llvm.frexp.ll
M llvm/test/CodeGen/ARM/misched-copy-arm.ll
M llvm/test/CodeGen/ARM/no-register-coalescing-in-returnsTwice.mir
M llvm/test/CodeGen/ARM/readonly-aliases.ll
M llvm/test/CodeGen/ARM/shift-combine.ll
M llvm/test/CodeGen/ARM/tail-dup-kill-flags.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fadd-legalization-strict.ll
M llvm/test/CodeGen/ARM/vecreduce-fmax-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmin-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-soft-float.ll
M llvm/test/CodeGen/ARM/vecreduce-fmul-legalization-strict.ll
M llvm/test/CodeGen/AVR/PR37143.ll
M llvm/test/CodeGen/AVR/alloca.ll
M llvm/test/CodeGen/AVR/atomics/load-store-16-unexpected-register-bug.ll
M llvm/test/CodeGen/AVR/atomics/load16.ll
M llvm/test/CodeGen/AVR/atomics/load32.ll
M llvm/test/CodeGen/AVR/atomics/load64.ll
M llvm/test/CodeGen/AVR/atomics/load8.ll
M llvm/test/CodeGen/AVR/atomics/store.ll
M llvm/test/CodeGen/AVR/atomics/store16.ll
M llvm/test/CodeGen/AVR/atomics/swap.ll
M llvm/test/CodeGen/AVR/avr-rust-issue-123.ll
M llvm/test/CodeGen/AVR/block-address-is-in-progmem-space.ll
M llvm/test/CodeGen/AVR/brind.ll
M llvm/test/CodeGen/AVR/call.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic.ll
M llvm/test/CodeGen/AVR/calling-conv/c/basic_aggr.ll
M llvm/test/CodeGen/AVR/calling-conv/c/stack.ll
M llvm/test/CodeGen/AVR/ctors.ll
M llvm/test/CodeGen/AVR/directmem.ll
M llvm/test/CodeGen/AVR/dynalloca.ll
M llvm/test/CodeGen/AVR/elpm.ll
M llvm/test/CodeGen/AVR/features/avr-tiny.ll
M llvm/test/CodeGen/AVR/features/xmega_io.ll
M llvm/test/CodeGen/AVR/frmidx-iterator-bug.ll
M llvm/test/CodeGen/AVR/high-pressure-on-ptrregs.ll
M llvm/test/CodeGen/AVR/icall-func-pointer-correct-addr-space.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm-invalid.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm.ll
M llvm/test/CodeGen/AVR/inline-asm/inline-asm3.ll
M llvm/test/CodeGen/AVR/inline-asm/loadstore.ll
M llvm/test/CodeGen/AVR/integration/blink.ll
M llvm/test/CodeGen/AVR/interrupts.ll
M llvm/test/CodeGen/AVR/intrinsics/stacksave-restore.ll
M llvm/test/CodeGen/AVR/io.ll
M llvm/test/CodeGen/AVR/issue-regalloc-stackframe-folding-earlyclobber.ll
M llvm/test/CodeGen/AVR/load.ll
M llvm/test/CodeGen/AVR/lpmx.ll
M llvm/test/CodeGen/AVR/pr43443-ctor-alias.ll
M llvm/test/CodeGen/AVR/progmem-extended.ll
M llvm/test/CodeGen/AVR/progmem.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-112.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-37.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-95.ll
M llvm/test/CodeGen/AVR/rust-avr-bug-99.ll
M llvm/test/CodeGen/AVR/rust-trait-object.ll
M llvm/test/CodeGen/AVR/std-ldd-immediate-overflow.ll
M llvm/test/CodeGen/AVR/store-undef.ll
M llvm/test/CodeGen/AVR/store.ll
M llvm/test/CodeGen/AVR/struct.ll
M llvm/test/CodeGen/AVR/umul.with.overflow.i16-bug.ll
M llvm/test/CodeGen/AVR/unaligned-atomic-ops.ll
M llvm/test/CodeGen/AVR/varargs.ll
M llvm/test/CodeGen/AVR/zeroreg.ll
M llvm/test/CodeGen/BPF/BTF/builtin-btf-type-id.ll
M llvm/test/CodeGen/BPF/BTF/static-var-zerolen-array.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-fwd.ll
M llvm/test/CodeGen/BPF/BTF/type-tag-fixup-resolved.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-array-2.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-struct-3.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-union-1.ll
M llvm/test/CodeGen/BPF/CORE/offset-reloc-cast-union-2.ll
M llvm/test/CodeGen/BPF/ex1.ll
M llvm/test/CodeGen/BPF/reloc.ll
M llvm/test/CodeGen/BPF/remove_truncate_3.ll
M llvm/test/CodeGen/BPF/sockex2.ll
M llvm/test/CodeGen/BPF/xadd.ll
M llvm/test/CodeGen/BPF/xadd_legal.ll
M llvm/test/CodeGen/Generic/DbgValueAggregate.ll
M llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables-x.mir
M llvm/test/CodeGen/Generic/MIRDebugify/check-line-and-variables.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/all.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/dont-strip-real-debug-info.mir
M llvm/test/CodeGen/Generic/MIRStripDebug/multiple-moduleflags.mir
M llvm/test/CodeGen/Hexagon/autohvx/fsplat.ll
M llvm/test/CodeGen/Hexagon/autohvx/hfsplat.ll
M llvm/test/CodeGen/Hexagon/cmpy-round.ll
M llvm/test/CodeGen/Hexagon/const-pool-tf.ll
M llvm/test/CodeGen/Hexagon/debug-prologue-loc.ll
M llvm/test/CodeGen/Hexagon/fixed-spill-mutable.ll
M llvm/test/CodeGen/Hexagon/machine-sink-float-usr.mir
M llvm/test/CodeGen/Hexagon/memcpy-likely-aligned.ll
M llvm/test/CodeGen/Hexagon/swp-carried-dep1.mir
M llvm/test/CodeGen/Hexagon/swp-carried-dep2.mir
M llvm/test/CodeGen/Hexagon/swp-memrefs-epilog.ll
M llvm/test/CodeGen/Hexagon/swp-new-phi.ll
M llvm/test/CodeGen/Hexagon/v5_insns.ll
M llvm/test/CodeGen/Hexagon/v60Vasr.ll
M llvm/test/CodeGen/Hexagon/vdmpy-halide-test.ll
M llvm/test/CodeGen/Hexagon/vect-regpairs.ll
M llvm/test/CodeGen/Hexagon/vect_setcc_v2i16.ll
M llvm/test/CodeGen/Hexagon/vmpa-halide-test.ll
M llvm/test/CodeGen/Lanai/codemodel.ll
M llvm/test/CodeGen/Lanai/inlineasm-output-template.ll
M llvm/test/CodeGen/Lanai/lanai-misched-trivial-disjoint.ll
M llvm/test/CodeGen/Lanai/mem_alu_combiner.ll
M llvm/test/CodeGen/Lanai/peephole-compare.mir
M llvm/test/CodeGen/Lanai/set_and_hi.ll
M llvm/test/CodeGen/Lanai/sub-cmp-peephole.ll
M llvm/test/CodeGen/Lanai/subword.ll
M llvm/test/CodeGen/LoongArch/frame.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-st.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-st.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
M llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
M llvm/test/CodeGen/LoongArch/tail-calls.ll
M llvm/test/CodeGen/MIR/AArch64/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/AArch64/invalid-target-flag-name.mir
M llvm/test/CodeGen/MIR/AArch64/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AArch64/machine-metadata.mir
M llvm/test/CodeGen/MIR/AArch64/stack-object-local-offset.mir
M llvm/test/CodeGen/MIR/AArch64/swp.mir
M llvm/test/CodeGen/MIR/AArch64/target-flags.mir
M llvm/test/CodeGen/MIR/AArch64/unnamed-stack.ll
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata-error.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-metadata.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/syncscopes.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
M llvm/test/CodeGen/MIR/ARM/cfi-same-value.mir
M llvm/test/CodeGen/MIR/ARM/expected-closing-brace.mir
M llvm/test/CodeGen/MIR/ARM/thumb2-sub-sp-t3.mir
M llvm/test/CodeGen/MIR/Generic/frame-info.mir
M llvm/test/CodeGen/MIR/Generic/llvm-ir-error-reported.mir
M llvm/test/CodeGen/MIR/Mips/memory-operands.mir
M llvm/test/CodeGen/MIR/Mips/setRegClassOrRegBank.mir
M llvm/test/CodeGen/MIR/PowerPC/unordered-implicit-registers.mir
M llvm/test/CodeGen/MIR/X86/block-address-operands.mir
M llvm/test/CodeGen/MIR/X86/branch-folder-with-label.mir
M llvm/test/CodeGen/MIR/X86/callee-saved-info.mir
M llvm/test/CodeGen/MIR/X86/diexpr-win32.mir
M llvm/test/CodeGen/MIR/X86/duplicate-memory-operand-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-alignment-after-align-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-block-reference-in-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-comma-after-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-different-implicit-register-flag.mir
M llvm/test/CodeGen/MIR/X86/expected-function-reference-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-global-value-after-blockaddress.mir
M llvm/test/CodeGen/MIR/X86/expected-integer-after-offset-sign.mir
M llvm/test/CodeGen/MIR/X86/expected-load-or-store-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-debug-location.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-after-exclaim.mir
M llvm/test/CodeGen/MIR/X86/expected-metadata-node-in-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-named-register-in-callee-saved-register.mir
M llvm/test/CodeGen/MIR/X86/expected-number-after-bb.mir
M llvm/test/CodeGen/MIR/X86/expected-pointer-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/expected-positive-alignment-after-align.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation.mir
M llvm/test/CodeGen/MIR/X86/expected-size-integer-after-memory-operation2.mir
M llvm/test/CodeGen/MIR/X86/expected-stack-object.mir
M llvm/test/CodeGen/MIR/X86/expected-target-flag-name.mir
M llvm/test/CodeGen/MIR/X86/expected-value-in-memory-operand.mir
M llvm/test/CodeGen/MIR/X86/external-symbol-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-di.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-memory-operands.mir
M llvm/test/CodeGen/MIR/X86/fixed-stack-objects.mir
M llvm/test/CodeGen/MIR/X86/frame-info-save-restore-points.mir
M llvm/test/CodeGen/MIR/X86/frame-info-stack-references.mir
M llvm/test/CodeGen/MIR/X86/global-value-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-heap-alloc-operands.mir
M llvm/test/CodeGen/MIR/X86/instr-pcsections.mir
M llvm/test/CodeGen/MIR/X86/instructions-debug-location.mir
M llvm/test/CodeGen/MIR/X86/invalid-metadata-node-type.mir
M llvm/test/CodeGen/MIR/X86/invalid-target-flag-name.mir
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M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-smax.ll
M llvm/test/CodeGen/X86/vector-reduce-smin.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect-post-combine.ll
M llvm/test/CodeGen/X86/vselect-zero.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/win64-byval.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppCatchDotDotDot.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppCondiTemps.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-CppDtors01.ll
M llvm/test/CodeGen/X86/windows-seh-EHa-TryInFinally.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/XCore/threads.ll
M llvm/test/Instrumentation/AddressSanitizer/global_with_comdat.ll
M llvm/test/MC/AMDGPU/hsa-v5-uses-dynamic-stack.s
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/RISCV/rv32zalasr-invalid.s
A llvm/test/MC/RISCV/rv32zalasr-valid.s
A llvm/test/MC/RISCV/rv64zalasr-invalid.s
A llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
M llvm/test/MC/WebAssembly/type-checker-errors.s
A llvm/test/TableGen/deftype.td
M llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
M llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
M llvm/test/Transforms/ArgumentPromotion/X86/thiscall.ll
M llvm/test/Transforms/ArgumentPromotion/store-into-inself.ll
M llvm/test/Transforms/Attributor/convergent.ll
M llvm/test/Transforms/Attributor/dereferenceable-2-inseltpoison.ll
M llvm/test/Transforms/Attributor/dereferenceable-2.ll
M llvm/test/Transforms/Attributor/value-simplify-pointer-info.ll
M llvm/test/Transforms/CodeGenPrepare/AArch64/combine-address-mode.ll
M llvm/test/Transforms/CodeGenPrepare/X86/sink-addrmode-base.ll
M llvm/test/Transforms/ConstraintElimination/minmax.ll
M llvm/test/Transforms/ConstraintElimination/reproducer-remarks.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-infinite-loop-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-addr-lifetime-start-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-coro-id-async-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-end-bug.ll
M llvm/test/Transforms/Coroutines/coro-async-no-cse-swift-async-context-addr.ll
M llvm/test/Transforms/Coroutines/coro-async-phi.ll
M llvm/test/Transforms/Coroutines/coro-async-unreachable.ll
M llvm/test/Transforms/CorrelatedValuePropagation/basic.ll
M llvm/test/Transforms/CorrelatedValuePropagation/minmaxabs.ll
M llvm/test/Transforms/CorrelatedValuePropagation/range.ll
M llvm/test/Transforms/CorrelatedValuePropagation/select.ll
M llvm/test/Transforms/CorrelatedValuePropagation/sub.ll
M llvm/test/Transforms/DeadArgElim/byref.ll
M llvm/test/Transforms/DeadArgElim/fct_ptr.ll
M llvm/test/Transforms/GVN/condprop-memdep-invalidation.ll
M llvm/test/Transforms/GVN/pr17732.ll
M llvm/test/Transforms/GVNHoist/hoist-recursive-geps.ll
M llvm/test/Transforms/GVNHoist/infinite-loop-direct.ll
M llvm/test/Transforms/GVNHoist/infinite-loop-indirect.ll
M llvm/test/Transforms/GlobalOpt/2007-06-04-PackedStruct.ll
M llvm/test/Transforms/GlobalOpt/2008-07-17-addrspace.ll
M llvm/test/Transforms/GlobalOpt/GSROA-section.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-gep-constexpr.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-other-constexpr.ll
M llvm/test/Transforms/GlobalOpt/cleanup-pointer-root-users-ptrtoint-add-constexpr.ll
M llvm/test/Transforms/GlobalOpt/externally-initialized-aggregate.ll
M llvm/test/Transforms/GlobalOpt/globalsra-partial.ll
M llvm/test/Transforms/GlobalOpt/globalsra.ll
M llvm/test/Transforms/GlobalOpt/invariant.ll
M llvm/test/Transforms/GlobalOpt/malloc-promote-opaque-ptr.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores-initializers.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores-once.ll
M llvm/test/Transforms/GlobalOpt/sra-many-stores.ll
M llvm/test/Transforms/IROutliner/nooutline-attribute.ll
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
M llvm/test/Transforms/IndVarSimplify/pr55925.ll
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/insert-pos-assert.ll
M llvm/test/Transforms/Inline/call-intrinsic-objectsize.ll
M llvm/test/Transforms/Inline/inline-byval-bonus.ll
M llvm/test/Transforms/Inline/inlined-loop-metadata-inseltpoison.ll
M llvm/test/Transforms/Inline/inlined-loop-metadata.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/InstCombine/alloca.ll
M llvm/test/Transforms/InstCombine/and.ll
M llvm/test/Transforms/InstCombine/call.ll
M llvm/test/Transforms/InstCombine/cos-1.ll
M llvm/test/Transforms/InstCombine/fmul.ll
A llvm/test/Transforms/InstCombine/fpclass-check-idioms.ll
M llvm/test/Transforms/InstCombine/memchr-8.ll
A llvm/test/Transforms/InstCombine/pr80597.ll
M llvm/test/Transforms/InstCombine/scalable-vector-struct.ll
M llvm/test/Transforms/LoadStoreVectorizer/AMDGPU/opaque_ptr.ll
M llvm/test/Transforms/LoopDistribute/symbolic-stride.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-negative.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-version.ll
M llvm/test/Transforms/LoopFlatten/widen-iv.ll
M llvm/test/Transforms/LoopIdiom/lir-heurs-multi-block-loop.ll
M llvm/test/Transforms/LoopInterchange/profitability.ll
M llvm/test/Transforms/LoopLoadElim/type-mismatch-opaque-ptr.ll
M llvm/test/Transforms/LoopSimplify/do-preheader-dbg-inseltpoison.ll
M llvm/test/Transforms/LoopSimplify/do-preheader-dbg.ll
M llvm/test/Transforms/LoopStrengthReduce/Power/memory-intrinsic.ll
M llvm/test/Transforms/LoopStrengthReduce/X86/2012-01-13-phielim.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold-negative-testcase.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
M llvm/test/Transforms/LoopUnroll/ARM/mve-nounroll.ll
M llvm/test/Transforms/LoopUnroll/peel-loop-conditions.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/LoopVectorize/cast-induction.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/lcssa-crashes.ll
M llvm/test/Transforms/LoopVectorize/pr45679-fold-tail-by-masking.ll
M llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
M llvm/test/Transforms/LoopVectorize/tail-folding-vectorization-factor-1.ll
M llvm/test/Transforms/MemCpyOpt/vscale-crashes.ll
M llvm/test/Transforms/MoveAutoInit/clobber.ll
M llvm/test/Transforms/NewGVN/flags-simplify.ll
M llvm/test/Transforms/NewGVN/no_speculative_loads_with_asan.ll
M llvm/test/Transforms/NewGVN/pr17732.ll
M llvm/test/Transforms/NewGVN/unreachable_block_infinite_loop.ll
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
M llvm/test/Transforms/PGOProfile/coverage.ll
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/slp-abs.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/reductions.ll
M llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshl.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr-rot.ll
M llvm/test/Transforms/SLPVectorizer/X86/arith-fshr.ll
M llvm/test/Transforms/SLPVectorizer/X86/horizontal.ll
M llvm/test/Transforms/SLPVectorizer/X86/opaque-ptr.ll
M llvm/test/Transforms/SLPVectorizer/X86/stackrestore-dependence.ll
M llvm/test/Transforms/SROA/invariant-group.ll
M llvm/test/Transforms/SROA/phi-gep.ll
M llvm/test/Transforms/SROA/scalable-vector-struct.ll
M llvm/test/Transforms/SROA/sroa-common-type-fail-promotion.ll
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/test/Transforms/ScalarizeMaskedMemIntrin/AArch64/streaming-compatible-expand-masked-gather-scatter.ll
M llvm/test/Transforms/SimplifyCFG/X86/pr39187-g.ll
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll
M llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
M llvm/test/Transforms/Util/pr49185.ll
M llvm/test/Transforms/VectorCombine/AArch64/select-shuffle.ll
M llvm/test/Transforms/VectorCombine/X86/load-widening.ll
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-const-folding.proftext
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-const.proftext
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.cpp
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.o
M llvm/test/tools/llvm-cov/Inputs/mcdc-general.proftext
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
M llvm/test/tools/llvm-cov/mcdc-const.test
M llvm/test/tools/llvm-cov/mcdc-general-none.test
M llvm/test/tools/llvm-cov/mcdc-general.test
A llvm/test/tools/llvm-cov/mcdc-macro.test
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/elf-headers.test
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.s
A llvm/test/tools/llvm-readobj/ELF/AMDGPU/generic_versions.test
R llvm/test/tools/llvm-readobj/ELF/amdgpu-elf-headers.test
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
A llvm/test/tools/llvm-readtapi/Inputs/libSystem.1.yaml
A llvm/test/tools/llvm-readtapi/stubify-delete.test
A llvm/test/tools/llvm-readtapi/stubify-simple.test
A llvm/test/tools/llvm-readtapi/stubify-symlink-darwin.test
R llvm/test/tools/llvm-readtapi/stubify.test
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llc/NewPMDriver.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/llvm-readtapi/TapiOpts.td
M llvm/tools/llvm-readtapi/llvm-readtapi.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
M llvm/unittests/ADT/StringMapTest.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
M llvm/unittests/Support/RISCVISAInfoTest.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
A llvm/utils/gn/secondary/llvm/unittests/Target/SPIRV/BUILD.gn
M mlir/docs/Bufferization.md
M mlir/include/mlir/Conversion/SCFToEmitC/SCFToEmitC.h
M mlir/include/mlir/Dialect/ArmSME/IR/ArmSMEOps.td
M mlir/include/mlir/Dialect/Bufferization/Pipelines/Passes.h
M mlir/include/mlir/Dialect/Bufferization/Transforms/Passes.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/NVGPU/IR/NVGPUDialect.h
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/AffineMap.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Conversion/SCFToEmitC/SCFToEmitC.cpp
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/BufferizationPipelines.cpp
M mlir/lib/Dialect/Bufferization/Pipelines/CMakeLists.txt
M mlir/lib/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation.cpp
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/NVGPU/IR/NVGPUDialect.cpp
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
M mlir/test/Dialect/Arith/canonicalize.mlir
M mlir/test/Dialect/ArmSME/outer-product-fusion.mlir
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-callop-interface.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-function-boundaries.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/NVGPU/invalid.mlir
M mlir/test/Dialect/NVGPU/tmaload-transform.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
A mlir/test/Dialect/SparseTensor/external.mlir
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
A mlir/test/Dialect/SparseTensor/torch_linalg.mlir
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
A mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_dilated_conv_2d_nhwc_hwcf.mlir
M mlir/test/Target/Cpp/func.mlir
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
A mlir/test/Target/LLVMIR/omptarget-fortran-allocatable-types-host.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
M mlir/test/Target/LLVMIR/openmp-llvm.mlir
M mlir/test/Target/LLVMIR/openmp-teams.mlir
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/python/dialects/memref.py
M openmp/libomptarget/include/Shared/PluginAPI.h
M openmp/libomptarget/include/Shared/PluginAPI.inc
M openmp/libomptarget/include/device.h
M openmp/libomptarget/plugins-nextgen/CMakeLists.txt
M openmp/libomptarget/plugins-nextgen/common/include/PluginInterface.h
M openmp/libomptarget/plugins-nextgen/common/src/PluginInterface.cpp
M openmp/libomptarget/src/omptarget.cpp
M openmp/libomptarget/test/offloading/dynamic_module_load.c
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-array-section-1d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-array-section-3d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-allocatable-map-scopes.f90
A openmp/libomptarget/test/offloading/fortran/target-map-enter-exit-allocatables.f90
A openmp/libomptarget/test/offloading/fortran/target-map-enter-exit-array.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-scopes-enter-exit.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-target-array-section-3d-bounds.f90
A openmp/libomptarget/test/offloading/fortran/target-map-pointer-target-scopes.f90
M openmp/runtime/src/CMakeLists.txt
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase, ping!
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/00dff040216a...ff46cfe3a387
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