[all-commits] [llvm/llvm-project] 0bf165: [RISCV] Add support for RISC-V Pointer Masking (#7...

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0bf165e383ac9c58dcb1764aef9f35334afa0cc7
      https://github.com/llvm/llvm-project/commit/0bf165e383ac9c58dcb1764aef9f35334afa0cc7
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-02-05 (Mon, 05 Feb 2024)

  Changed paths:
    M clang/test/Preprocessor/riscv-target-features.c
    M llvm/docs/RISCVUsage.rst
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/lib/Target/RISCV/RISCVFeatures.td
    M llvm/test/CodeGen/RISCV/attributes.ll
    M llvm/unittests/Support/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Add support for RISC-V Pointer Masking (#79929)

This patch implements the v0.8.1 specification. This patch reports
version 0.8 in llvm since `RISCVISAInfo::ExtensionVersion` only has a
`Major` and `Minor` version number. This patch includes includes support
of the `Ssnpm`, `Smnpm`, `Smmpm`, `Sspm` and `Supm` extensions that make
up RISC-V pointer masking.

All of these extensions require emitting attribute containing correct
`march` string.

`Ssnpm`, `Smnpm`, `Smmpm` extensions introduce a 2-bit WARL field (PMM).
The extension does not specify how PMM is set, and therefore this patch
does not need to address this. One example of how it *could* be set is
using the Zicsr instructions to update the PMM bits of the described
registers.

The full specification can be found at
https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf