[all-commits] [llvm/llvm-project] 1ee315: [AArch64] Convert tests to opaque pointers (NFC)

Nikita Popov via All-commits all-commits at lists.llvm.org
Mon Feb 5 03:40:10 PST 2024 

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1ee315ae7964c8433b772e0b5d667834994ba753
      https://github.com/llvm/llvm-project/commit/1ee315ae7964c8433b772e0b5d667834994ba753
  Author: Nikita Popov <npopov at redhat.com>
  Date:   2024-02-05 (Mon, 05 Feb 2024)

  Changed paths:
    M llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext-debugloc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/combine-sext-debugloc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fp128-legalize-crash-pr35690.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/fp16-copy-gpr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy-forced.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memmove.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-memset.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/inline-small-memcpy.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-blockaddress.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-with-success.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-dyn-alloca.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global-pic.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-global.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store-vector-of-ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-memlib-debug-loc.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-s128-div.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/load-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/localizer.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/non-pow-2-extload-combine.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/postselectopt-xclass-copies.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-icmp-to-true-false-known-bits.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-copy-prop-disabled.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-cornercases.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/prelegalizercombiner-extending-loads-s1.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-add-low.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-atomic-load-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-atomicrmw.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-blockaddress.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-cmpxchg.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-constant.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-extload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ldaxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-ldxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load-store-vector-of-ptr.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-load.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-phi.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddress-liveins.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-sextload.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-static.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-stlxr-intrin.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store-truncating-float.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-store.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-stx.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/sext-inreg-ldrow-16b.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-addressing-modes.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/store-merging.mir
    M llvm/test/CodeGen/AArch64/PBQP-csr.ll
    M llvm/test/CodeGen/AArch64/a55-fuse-address.mir
    M llvm/test/CodeGen/AArch64/aarch64-dup-ext-crash.ll
    M llvm/test/CodeGen/AArch64/aarch64-ldst-no-premature-sp-pop.mir
    M llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
    M llvm/test/CodeGen/AArch64/aarch64-mov-debug-locs.mir
    M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes-neoverse.ll
    M llvm/test/CodeGen/AArch64/aarch64-p2align-max-bytes.ll
    M llvm/test/CodeGen/AArch64/add-i256.ll
    M llvm/test/CodeGen/AArch64/addrsig-macho.ll
    M llvm/test/CodeGen/AArch64/align-down.ll
    M llvm/test/CodeGen/AArch64/arm64-collect-loh.ll
    M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog-bad-outline.mir
    M llvm/test/CodeGen/AArch64/arm64-homogeneous-prolog-epilog.ll
    M llvm/test/CodeGen/AArch64/arm64-ldp.ll
    M llvm/test/CodeGen/AArch64/arm64-misched-basic-A53.ll
    M llvm/test/CodeGen/AArch64/arm64-misched-basic-A57.ll
    M llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
    M llvm/test/CodeGen/AArch64/arm64-preserve-all.ll
    M llvm/test/CodeGen/AArch64/arm64-zip.ll
    M llvm/test/CodeGen/AArch64/branch-relax-block-size.mir
    M llvm/test/CodeGen/AArch64/compute-call-frame-size-unreachable-pass.ll
    M llvm/test/CodeGen/AArch64/concat_vector-truncate-combine.ll
    M llvm/test/CodeGen/AArch64/dag-combine-lifetime-end-store-typesize.ll
    M llvm/test/CodeGen/AArch64/dag-combine-trunc-build-vec.ll
    M llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir
    M llvm/test/CodeGen/AArch64/divrem.ll
    M llvm/test/CodeGen/AArch64/dont-shrink-wrap-stack-mayloadorstore.mir
    M llvm/test/CodeGen/AArch64/early-ifcvt-regclass-mismatch.mir
    M llvm/test/CodeGen/AArch64/elim-dead-mi.mir
    M llvm/test/CodeGen/AArch64/expand-blr-rvmarker-pseudo.mir
    M llvm/test/CodeGen/AArch64/fmov-imm-licm.ll
    M llvm/test/CodeGen/AArch64/inline-asm-constraints-bad-sve.ll
    M llvm/test/CodeGen/AArch64/insert-subvector-res-legalization.ll
    M llvm/test/CodeGen/AArch64/irg-nomem.mir
    M llvm/test/CodeGen/AArch64/ldradr.ll
    M llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir
    M llvm/test/CodeGen/AArch64/ldst-opt-aa.mir
    M llvm/test/CodeGen/AArch64/ldst-opt-non-imm-offset.mir
    M llvm/test/CodeGen/AArch64/ldst-opt-zr-clobber.mir
    M llvm/test/CodeGen/AArch64/machine-combiner-fmul-dup.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-bti.mir
    M llvm/test/CodeGen/AArch64/machine-outliner-retaddr-sign-sp-mod.mir
    M llvm/test/CodeGen/AArch64/machine-scheduler.mir
    M llvm/test/CodeGen/AArch64/memcpy-scoped-aa.ll
    M llvm/test/CodeGen/AArch64/merge-scoped-aa-store.ll
    M llvm/test/CodeGen/AArch64/merge-store.ll
    M llvm/test/CodeGen/AArch64/multi-vector-load-size.ll
    M llvm/test/CodeGen/AArch64/nontemporal-load.ll
    M llvm/test/CodeGen/AArch64/pre-indexed-addrmode-with-constant-offset.ll
    M llvm/test/CodeGen/AArch64/ragreedy-local-interval-cost.ll
    M llvm/test/CodeGen/AArch64/rvmarker-pseudo-expansion-and-outlining.mir
    M llvm/test/CodeGen/AArch64/sched-movprfx.ll
    M llvm/test/CodeGen/AArch64/settag-merge.mir
    M llvm/test/CodeGen/AArch64/sme-intrinsics-mova-extract.ll
    M llvm/test/CodeGen/AArch64/speculation-hardening-sls.mir
    M llvm/test/CodeGen/AArch64/speculation-hardening.mir
    M llvm/test/CodeGen/AArch64/spillfill-sve.ll
    M llvm/test/CodeGen/AArch64/stack-guard-reassign-sve.mir
    M llvm/test/CodeGen/AArch64/stack-guard-reassign.mir
    M llvm/test/CodeGen/AArch64/stack-guard-sve.ll
    M llvm/test/CodeGen/AArch64/stack-probing-64k.ll
    M llvm/test/CodeGen/AArch64/stack-tagging-cfi.ll
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
    M llvm/test/CodeGen/AArch64/stp-opt-with-renaming-undef-assert.mir
    M llvm/test/CodeGen/AArch64/sub-of-bias.ll
    M llvm/test/CodeGen/AArch64/sve-alloca-stackid.ll
    M llvm/test/CodeGen/AArch64/sve-alloca.ll
    M llvm/test/CodeGen/AArch64/sve-calling-convention-mixed.ll
    M llvm/test/CodeGen/AArch64/sve-dead-masked-store.ll
    M llvm/test/CodeGen/AArch64/sve-extract-fixed-vector.ll
    M llvm/test/CodeGen/AArch64/sve-fold-vscale.ll
    M llvm/test/CodeGen/AArch64/sve-forward-st-to-ld.ll
    M llvm/test/CodeGen/AArch64/sve-fp.ll
    M llvm/test/CodeGen/AArch64/sve-fpext-load.ll
    M llvm/test/CodeGen/AArch64/sve-fptrunc-store.ll
    M llvm/test/CodeGen/AArch64/sve-gather-scatter-dag-combine.ll
    M llvm/test/CodeGen/AArch64/sve-gep.ll
    M llvm/test/CodeGen/AArch64/sve-insert-vector.ll
    M llvm/test/CodeGen/AArch64/sve-int-arith.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-contiguous-prefetches.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ldN-sret-reg+imm-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-ldst-ext.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-loads-nf.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-mask-ldst-ext.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-ld1-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-ld1r.ll
    M llvm/test/CodeGen/AArch64/sve-masked-gather.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-nonext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-sext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-masked-ldst-zext.ll
    M llvm/test/CodeGen/AArch64/sve-masked-scatter.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-pred-contiguous-ldst-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-pred-non-temporal-ldst-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-redundant-store.ll
    M llvm/test/CodeGen/AArch64/sve-setcc.ll
    M llvm/test/CodeGen/AArch64/sve-split-load.ll
    M llvm/test/CodeGen/AArch64/sve-split-store.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-imm.ll
    M llvm/test/CodeGen/AArch64/sve-st1-addressing-mode-reg-reg.ll
    M llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
    M llvm/test/CodeGen/AArch64/sve-trunc.ll
    M llvm/test/CodeGen/AArch64/sve-uunpklo-load-uzp1-store-combine.ll
    M llvm/test/CodeGen/AArch64/sve-varargs-callee-broken.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-ld1-single.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-loads.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-multivec-stores.ll
    M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-st1-single.ll
    M llvm/test/CodeGen/AArch64/swift-error-unreachable-use.ll
    M llvm/test/CodeGen/AArch64/taildup-addrtaken.mir
    M llvm/test/CodeGen/AArch64/tailmerging_in_mbp.ll
    M llvm/test/CodeGen/AArch64/tiny-model-pic.ll
    M llvm/test/CodeGen/AArch64/tiny-model-static.ll
    M llvm/test/CodeGen/AArch64/unwind-preserved-from-mir.mir
    M llvm/test/CodeGen/AArch64/v3f-to-int.ll
    M llvm/test/CodeGen/AArch64/win-catchpad-nested-cxx.ll
    M llvm/test/CodeGen/AArch64/wineh-frame5.mir
    M llvm/test/CodeGen/AArch64/wineh-frame6.mir
    M llvm/test/CodeGen/AArch64/wineh-frame7.mir
    M llvm/test/CodeGen/AArch64/wineh-frame8.mir
    M llvm/test/CodeGen/AArch64/wineh5.mir
    M llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir
    M llvm/test/CodeGen/AArch64/wrong-callee-save-size-after-livedebugvariables.mir
    M llvm/test/CodeGen/AArch64/zero-reg.ll

  Log Message:
  -----------
  [AArch64] Convert tests to opaque pointers (NFC)

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