[all-commits] [llvm/llvm-project] 6590d0: [DAGCombiner][ARM] Teach reduceLoadWidth to handle...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6590d0fed5180a403c32c991baed56f9d39e045a
      https://github.com/llvm/llvm-project/commit/6590d0fed5180a403c32c991baed56f9d39e045a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-04 (Sun, 04 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
    M llvm/test/CodeGen/ARM/shift-combine.ll
    M llvm/test/CodeGen/X86/h-registers-2.ll

  Log Message:
  -----------
  [DAGCombiner][ARM] Teach reduceLoadWidth to handle (and (srl (load), C, ShiftedMask)) (#80342)

If we have a shifted mask, we may be able to reduce the load width
to the width of the non-zero part of the mask and use an offset
to the base address to remove the srl. The offset is given by
C+trailingzeros(ShiftedMask).
    
Then we add a final shl to restore the trailing zero bits.
    
I've use the ARM test because that's where the existing (and (srl
(load))) tests were.
    
The X86 test was modified to keep the H register.