[all-commits] [llvm/llvm-project] 3bcb1f: [RISCV] Rework isSignExtendingOpW to store Registe...
Craig Topper via All-commits
all-commits at lists.llvm.org
Sat Feb 3 23:47:39 PST 2024
Branch: refs/heads/main
Home: https://github.com/llvm/llvm-project
Commit: 3bcb1f2bdd5c70b2ac4aff3290996486d9ae0236
https://github.com/llvm/llvm-project/commit/3bcb1f2bdd5c70b2ac4aff3290996486d9ae0236
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-03 (Sat, 03 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/opt-w-instrs.mir
Log Message:
-----------
[RISCV] Rework isSignExtendingOpW to store Register in the worklist.
Previously we stored MachineInstr which restricted the implementation
to only handle operand 0.
The TH_LWD instruction has two sign extended destinations.
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