[all-commits] [llvm/llvm-project] 7a7d54: [libc] add bazel support for most of unistd (#80078)
Alexey Bataev via All-commits
all-commits at lists.llvm.org
Fri Feb 2 11:32:06 PST 2024
Branch: refs/heads/users/alexey-bataev/spr/ttiriscvimprove-costs-for-fixed-vector-whole-reg-extractinsert
Home: https://github.com/llvm/llvm-project
Commit: 7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
https://github.com/llvm/llvm-project/commit/7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc] add bazel support for most of unistd (#80078)
Much of unistd involves modifying files. The tests for these functions
need to use libc_make_test_file_path which didn't exist when they were
first implemented. This patch adds most of unistd to the bazel along
with the corresponding tests. Tests that modify directories had to be
disabled since bazel doesn't seem to handle them properly.
Commit: aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
https://github.com/llvm/llvm-project/commit/aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
Author: Micah Weston <micahsweston at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP][llvm-readobj] Implements llvm-readobj handling for PGOAnalysisMap. (#79520)
Adds raw printing of PGOAnalysisMap in llvm-readobj.
I'm leaving the fixme's for a later patch that will provide a 'pretty'
printing for BBFreq and BrProb (i.e. relative frequencies and
probabilities) that will apply to both llvm-readobj and llvm-objdump.
Commit: 08fccf80949c649e2c4c81bf9149fd77206002c4
https://github.com/llvm/llvm-project/commit/08fccf80949c649e2c4c81bf9149fd77206002c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
Log Message:
-----------
[AArch64][PAC] Expand blend(reg, imm) operation in aarch64-pauth pass (#74729)
In preparation for implementing code generation for more @llvm.ptrauth.* intrinsics, move the expansion of blend(register, small integer) variant of @llvm.ptrauth.blend to the AArch64PointerAuth pass, where most other PAuth-related code generation takes place.
Commit: fe408eb5845737f8d6bf5eeed0aca8651991e687
https://github.com/llvm/llvm-project/commit/fe408eb5845737f8d6bf5eeed0aca8651991e687
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
Log Message:
-----------
[flang][openacc][openmp] Use #0 from hlfir.declare value when generating bound ops (#80317)
`getDataOperandBaseAddr` retrieve the address of a value when we need to
generate bound operations. When switching to HLFIR, we did not really
handle the fact that this value was then pointing to the result of a
hlfir.declare. Because of that the `#1` value was being used. `#0` value
is carrying the correct information about lowerbounds and should be
used. This patch updates the `getDataOperandBaseAddr` function to use
the correct result value from hlfir.declare.
Commit: 243bfed68367263cfc3fb3f396660acf60051fbf
https://github.com/llvm/llvm-project/commit/243bfed68367263cfc3fb3f396660acf60051fbf
Author: Artem Dergachev <adergachev at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
A clang/test/Analysis/html_diagnostics/counter.c
Log Message:
-----------
[analyzer][HTMLRewriter] Cache partial rewrite results. (#80220)
This is a follow-up for 721dd3bc2 [analyzer] NFC: Don't regenerate
duplicate HTML reports.
Because HTMLRewriter re-runs the Lexer for syntax highlighting and macro
expansion purposes, it may get fairly expensive when the rewriter is
invoked multiple times on the same file. In the static analyzer (which
uses HTMLRewriter for HTML output mode) we only get away with this
because there are usually very few reports emitted per file. But if loud
checkers are enabled, such as `webkit.*`, this may explode in complexity
and even cause the compiler to run over the 32-bit SourceLocation
addressing limit.
This patch caches intermediate results so that re-lexing only needed to
happen once.
As the clever __COUNTER__ test demonstrates, "once" is still too many.
Ideally we shouldn't re-lex anything at all, which remains a TODO.
Commit: 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
https://github.com/llvm/llvm-project/commit/8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
Author: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI]Add support for strided loads/stores.
Added basic legality check and cost estimation functions for strided loads and stores.
These interfaces will be built upon in https://github.com/llvm/llvm-project/pull/80310.
Reviewers: preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/80329
Commit: 59e559067b1e47b72f3c631483c1f71919d5358e
https://github.com/llvm/llvm-project/commit/59e559067b1e47b72f3c631483c1f71919d5358e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
Log Message:
-----------
Revert "[RISCV] Refine cost on Min/Max reduction" (#80340)
Reverts llvm/llvm-project#79402. Crash reported. On closer inspection,
this patch does not handle Intrinsic::maximum and Intrinsic::minimum.
Commit: edbd93d3706b806e7c91dfd2c359476488dfcc96
https://github.com/llvm/llvm-project/commit/edbd93d3706b806e7c91dfd2c359476488dfcc96
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/stdc_leading_ones_uc.cpp
M libc/src/stdbit/stdc_leading_ones_uc.h
M libc/src/stdbit/stdc_leading_ones_ul.cpp
M libc/src/stdbit/stdc_leading_ones_ul.h
M libc/src/stdbit/stdc_leading_ones_ull.cpp
M libc/src/stdbit/stdc_leading_ones_ull.h
M libc/src/stdbit/stdc_leading_ones_us.cpp
M libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
Log Message:
-----------
[libc][stdbit] fix return types (#80337)
All of the functions I've previously implemented return an unsigned int; not
the parameter type.
Commit: 5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
https://github.com/llvm/llvm-project/commit/5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/StackSlotColoring.cpp
A llvm/test/CodeGen/RISCV/pr80052.mir
M llvm/test/CodeGen/X86/pr30821.mir
Log Message:
-----------
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
The stack slot coloring pass is concerned with optimizing spill
slots. If any change is a pass is made over the function to remove
stack stores that use the same register and stack slot as an
immediately preceding load.
The register check is too simple for constant registers like AArch64
and RISC-V's zero register. This register can be used as the result
of a load if we want to discard the result, but still have the memory
access performed. Like for a volatile or atomic load.
If the code sees a load from the zero register followed by a store
of the zero register at the same stack slot, the pass mistakenly
believes the store isn't needed.
Since the main stack coloring optimization is only concerned with
spill slots, it seems reasonable that RemoveDeadStores should
only be concerned with spills. Since we never generate a reload of
x0, this avoids the issue seen by RISC-V.
Test case concept is adapted from pr30821.mir from X86. That test
had to be updated to mark the stack slot as a spill slot.
Fixes #80052.
Commit: 33b463ad9976fa7a27c1a22419297fcccd79f99f
https://github.com/llvm/llvm-project/commit/33b463ad9976fa7a27c1a22419297fcccd79f99f
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
A mlir/test/Dialect/SparseTensor/external.mlir
Log Message:
-----------
[mlir][sparse] external entry method wrapper for sparse tensors (#80326)
Similar to the emit_c_interface, this pull request adds a pass that
converts public entry methods that use sparse tensors as input
parameters and/or output return values into wrapper functions that
[dis]assemble the individual tensors that constitute the actual storage
used externally into MLIR sparse tensors. This pass can be used to
prepare the public entry methods of a program that is compiled by the
MLIR sparsifier to interface with an external runtime, e.g., when
passing sparse tensors as numpy arrays from and to Python. Note that
eventual bufferization decisions (e.g. who [de]allocates the underlying
memory) should be resolved in agreement with the external runtime
(Python, PyTorch, JAX, etc.)
Commit: 5d228eaf0f5d9c873ba12fc439609148f3f88733
https://github.com/llvm/llvm-project/commit/5d228eaf0f5d9c873ba12fc439609148f3f88733
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add beginner-focused office hours (#80308)
These are initially being hosted by a rotating cast of: @danakj
@gburgessiv @nickdesaulniers @sudonatalie
Commit: 9258f3e692493a69e0f4755bb129a5391ef10b50
https://github.com/llvm/llvm-project/commit/9258f3e692493a69e0f4755bb129a5391ef10b50
Author: Greg Clayton <gclayton at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
Log Message:
-----------
[lldb] Fix a crash when using .dwp files and make type lookup reliable with the index cache (#79544)
When using split DWARF with .dwp files we had an issue where sometimes
the DWO file within the .dwp file would be parsed _before_ the skeleton
compile unit. The DWO file expects to be able to always be able to get a
link back to the skeleton compile unit. Prior to this fix, the only time
the skeleton compile unit backlink would get set, was if the unit
headers for the main executable have been parsed _and_ if the unit DIE
was parsed in that DWARFUnit. This patch ensures that we can always get
the skeleton compile unit for a DWO file by adding a function:
```
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
```
Prior to this fix DWARFUnit had some unsafe accessors that were used to
store two different things:
```
void *DWARFUnit::GetUserData() const;
void DWARFUnit::SetUserData(void *d);
```
This was used by SymbolFileDWARF to cache the `lldb_private::CompileUnit
*` for a SymbolFileDWARF and was also used to store the `DWARFUnit *`
for SymbolFileDWARFDwo. This patch clears up this unsafe usage by adding
two separate accessors and ivars for this:
```
lldb_private::CompileUnit *DWARFUnit::GetLLDBCompUnit() const { return m_lldb_cu; }
void DWARFUnit::SetLLDBCompUnit(lldb_private::CompileUnit *cu) { m_lldb_cu = cu; }
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
void DWARFUnit::SetSkeletonUnit(DWARFUnit *skeleton_unit);
```
This will stop anyone from calling `void *DWARFUnit::GetUserData()
const;` and casting the value to an incorrect value.
A crash could occur in `SymbolFileDWARF::GetCompUnitForDWARFCompUnit()`
when the `non_dwo_cu`, which is a backlink to the skeleton compile unit,
was not set and was NULL. There is an assert() in the code, and then the
code just will kill the program if the assert isn't enabled because the
code looked like:
```
if (dwarf_cu.IsDWOUnit()) {
DWARFCompileUnit *non_dwo_cu =
static_cast<DWARFCompileUnit *>(dwarf_cu.GetUserData());
assert(non_dwo_cu);
return non_dwo_cu->GetSymbolFileDWARF().GetCompUnitForDWARFCompUnit(
*non_dwo_cu);
}
```
This is now fixed by calling the `DWARFUnit::GetSkeletonUnit()` which
will correctly always get the skeleton compile uint for a DWO file
regardless of if the skeleton unit headers have been parse or if the
skeleton unit DIE wasn't parsed yet.
To implement the ability to get the skeleton compile units, I added code
the DWARFDebugInfo.cpp/.h that make a map of DWO ID -> skeleton
DWARFUnit * that gets filled in for DWARF5 when the unit headers are
parsed. The `DWARFUnit::GetSkeletonUnit()` will end up parsing the unit
headers of the main executable to fill in this map if it already hasn't
been done. For DWARF4 and earlier we maintain a separate map that gets
filled in only for any DWARF4 compile units that have a DW_AT_dwo_id or
DW_AT_gnu_dwo_id attributes. This is more expensive, so this is done
lazily and in a thread safe manor. This allows us to be as efficient as
possible when using DWARF5 and also be backward compatible with DWARF4 +
split DWARF.
There was also an issue that stopped type lookups from succeeding in
`DWARFDIE SymbolFileDWARF::GetDIE(const DIERef &die_ref)` where it
directly was accessing the `m_dwp_symfile` ivar without calling the
accessor function that could end up needing to locate and load the .dwp
file. This was fixed by calling the
`SymbolFileDWARF::GetDwpSymbolFile()` accessor to ensure we always get a
valid value back if we can find the .dwp file. Prior to this fix it was
down which APIs were called and if any APIs were called that loaded the
.dwp file, it worked fine, but it might not if no APIs were called that
did cause it to get loaded.
When we have valid debug info indexes and when the lldb index cache was
enabled, this would cause this issue to show up more often.
I modified an existing test case to test that all of this works
correctly and doesn't crash.
Commit: 1bc7be6bce861acfe477f0c9abd349c1dc6ea160
https://github.com/llvm/llvm-project/commit/1bc7be6bce861acfe477f0c9abd349c1dc6ea160
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost model coverage for vp.strided.load and vp.strided.store
Commit: 391393179a6e316909add3b8455eb6d7c7c38ddb
https://github.com/llvm/llvm-project/commit/391393179a6e316909add3b8455eb6d7c7c38ddb
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
Log Message:
-----------
[lld-macho] icf objc stubs (#79730)
This supports icf for objc stubs.
Commit: ecdbffe59e80666c9cadf3f80bd20bb34828fb47
https://github.com/llvm/llvm-project/commit/ecdbffe59e80666c9cadf3f80bd20bb34828fb47
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/src/sys/epoll/linux/epoll_wait.cpp
Log Message:
-----------
[libc] Support epoll_wait using epoll_pwait (#80224)
The epoll_wait syscall is equivalent to calling epoll_pwait with a null
sigset. This is useful to support systems that have epoll_pwait but not
epoll_wait.
Commit: bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
https://github.com/llvm/llvm-project/commit/bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
Author: Hana Dusíková <hanicka at hanicka.net>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/test/CoverageMapping/if.cpp
Log Message:
-----------
[coverage] fix crash in code coverage and `if constexpr` with `ExprWithCleanups` (#80292)
Fixes https://github.com/llvm/llvm-project/issues/80285
Commit: 375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
https://github.com/llvm/llvm-project/commit/375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add aligned/unaligned tests for vp.strided.load and vp.strided.store
Commit: 07bf1ddb4eb0abfff20542fd4459bace1f72107f
https://github.com/llvm/llvm-project/commit/07bf1ddb4eb0abfff20542fd4459bace1f72107f
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
Log Message:
-----------
[mlir][sparse] support non-id map for [Dis]assembleOp (#80355)
Commit: 4eac14683855e040adaf507ed6b14e28a09f983e
https://github.com/llvm/llvm-project/commit/4eac14683855e040adaf507ed6b14e28a09f983e
Author: Greg Clayton <clayborg at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
Log Message:
-----------
Fix buildbots after #79544
https://github.com/llvm/llvm-project/pull/79544
Commit: 4a653b4df5d84c4d2df8f6d4040ef46413ac3816
https://github.com/llvm/llvm-project/commit/4a653b4df5d84c4d2df8f6d4040ef46413ac3816
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
Log Message:
-----------
[mlir][sparse] Support pretty print to debug sparse iteration. (#80207)
Commit: 8fd0bce43c4c8334bcb31d214a32260914f59515
https://github.com/llvm/llvm-project/commit/8fd0bce43c4c8334bcb31d214a32260914f59515
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
Log Message:
-----------
[mlir][spirv][memref] Calculate alignment for `PhysicalStorageBuffer`s (#80243)
The SPIR-V spec requires that memory accesses to
`PhysicalStorageBuffer`s are annotated with appropriate alignment
attributes [1]. Calculate these based on memref alignment attributes or
scalar type sizes.
[1] Otherwise spirv-val complains:
```
[VULKAN] ! Validation Error: [ VUID-VkShaderModuleCreateInfo-pCode-01379 ] | MessageID = 0x2a1bf17f | SPIR-V module not valid: [VUID-StandaloneSpirv-PhysicalStorageBuffer64-04708] Memory accesses with PhysicalStorageBuffer must use Aligned.
%48 = OpLoad %float %47
```
Commit: 4d89356fef1a568de790ad8b3f53dc494b461e5b
https://github.com/llvm/llvm-project/commit/4d89356fef1a568de790ad8b3f53dc494b461e5b
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
Log Message:
-----------
[libc][bazel] disable epoll_pwait2 (#80362)
Similar to #80051. The epoll_pwait2 syscall isn't available on all
target platforms, and this is causing downstream test failures. This
patch disables it until it can be detected whether or not it is
available.
Commit: ff3194037071e7f5fe859ad2173a5b67eed08b3b
https://github.com/llvm/llvm-project/commit/ff3194037071e7f5fe859ad2173a5b67eed08b3b
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port ecb5a1b0e236
Commit: 59eadcd28f787a98a2fd5f057beb3df7950654ee
https://github.com/llvm/llvm-project/commit/59eadcd28f787a98a2fd5f057beb3df7950654ee
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/test/python/dialects/memref.py
Log Message:
-----------
[mlir][py] Reduce size of allocation memrefs in test.
Commit: cc0d752f345f0e8995bec8807e3f365f38864fb6
https://github.com/llvm/llvm-project/commit/cc0d752f345f0e8995bec8807e3f365f38864fb6
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add git to actions container image (#80341)
Commit: 70eab122bceb94b15218c86db7045ff2448ea979
https://github.com/llvm/llvm-project/commit/70eab122bceb94b15218c86db7045ff2448ea979
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[AArch64][MachinePipeliner] Add pipeliner support for AArch64 (#79589)
Add AArch64 implementations for the interfaces of MachinePipeliner pass.
The pass is disabled by default for AArch64. It is enabled by specifying
--aarch64-enable-pipeliner.
5 tests in llvm-test-suites show performance improvement by more than 5%
on a Neoverse V1 processor.
| test | improvement |
| ---------------------------------------------------------------- |
-----------:|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl.test | 16%
|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-flt.test | 16%
|
| SingleSource/Benchmarks/Adobe-C++/loop_unroll.test | 14% |
| SingleSource/Benchmarks/Misc/flops-5.test | 13% |
| SingleSource/Benchmarks/BenchmarkGame/spectral-norm.test | 6% |
(base flags: -mcpu=neoverse-v1 -O3 -mrecip, flags for pipelining: -mllvm
-aarch64-enable-pipeliner -mllvm
-pipeliner-max-stages=100 -mllvm -pipeliner-max-mii=100 -mllvm
-pipeliner-enable-copytophi=0)
On the other hand, there are cases of significant performance
degradation. Algorithm improvements and adding the option/pragma will be
needed in the future.
Commit: acec6419e811a46050b0603dfa72fc6a169aa0f7
https://github.com/llvm/llvm-project/commit/acec6419e811a46050b0603dfa72fc6a169aa0f7
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/basic-block-address-map.c
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
A lld/test/ELF/lto/basic-block-address-map.ll
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
A llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
A llvm/test/CodeGen/X86/basic-block-address-map.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels.ll
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP] Allow basic-block-sections and labels be used together by decoupling the handling of the two features. (#74128)
Today `-split-machine-functions` and `-fbasic-block-sections={all,list}`
cannot be combined with `-basic-block-sections=labels` (the labels
option will be ignored).
The inconsistency comes from the way basic block address map -- the
underlying mechanism for basic block labels -- encodes basic block
addresses
(https://lists.llvm.org/pipermail/llvm-dev/2020-July/143512.html).
Specifically, basic block offsets are computed relative to the function
begin symbol. This relies on functions being contiguous which is not the
case for MFS and basic block section binaries. This means Propeller
cannot use binary profiles collected from these binaries, which limits
the applicability of Propeller for iterative optimization.
To make the `SHT_LLVM_BB_ADDR_MAP` feature work with basic block section
binaries, we propose modifying the encoding of this section as follows.
First let us review the current encoding which emits the address of each
function and its number of basic blocks, followed by basic block entries
for each basic block.
| | |
|--|--|
| Address of the function | Function Address |
| Number of basic blocks in this function | NumBlocks |
| BB entry 1
| BB entry 2
| ...
| BB entry #NumBlocks
To make this work for basic block sections, we treat each basic block
section similar to a function, except that basic block sections of the
same function must be encapsulated in the same structure so we can map
all of them to their single function.
We modify the encoding to first emit the number of basic block sections
(BB ranges) in the function. Then we emit the address map of each basic
block section section as before: the base address of the section, its
number of blocks, and BB entries for its basic block. The first section
in the BB address map is always the function entry section.
| | |
|--|--|
| Number of sections for this function | NumBBRanges |
| Section 1 begin address | BaseAddress[1] |
| Number of basic blocks in section 1 | NumBlocks[1] |
| BB entries for Section 1
|..................|
| Section #NumBBRanges begin address | BaseAddress[NumBBRanges] |
| Number of basic blocks in section #NumBBRanges |
NumBlocks[NumBBRanges] |
| BB entries for Section #NumBBRanges
The encoding of basic block entries remains as before with the minor
change that each basic block offset is now computed relative to the
begin symbol of its containing BB section.
This patch adds a new boolean codegen option `-basic-block-address-map`.
Correspondingly, the front-end flag `-fbasic-block-address-map` and LLD
flag `--lto-basic-block-address-map` are introduced.
Analogously, we add a new TargetOption field `BBAddrMap`. This means BB
address maps are either generated for all functions in the compiling
unit, or for none (depending on `TargetOptions::BBAddrMap`).
This patch keeps the functionality of the old
`-fbasic-block-sections=labels` option but does not remove it. A
subsequent patch will remove the obsolete option.
We refactor the `BasicBlockSections` pass by separating the BB address
map and BB sections handing to their own functions (named
`handleBBAddrMap` and `handleBBSections`). `handleBBSections` renumbers
basic blocks and places them in their assigned sections.
`handleBBAddrMap` is invoked after `handleBBSections` (if requested) and
only renumbers the blocks.
- New tests added:
- Two tests basic-block-address-map-with-basic-block-sections.ll and
basic-block-address-map-with-mfs.ll to exercise the combination of
`-basic-block-address-map` with `-basic-block-sections=list` and
'-split-machine-functions`.
- A driver sanity test for the `-fbasic-block-address-map` option
(basic-block-address-map.c).
- An LLD test for testing the `--lto-basic-block-address-map` option.
This reuses the LLVM IR from `lld/test/ELF/lto/basic-block-sections.ll`.
- Renamed and modified the two existing codegen tests for basic block
address map (`basic-block-sections-labels-functions-sections.ll` and
`basic-block-sections-labels.ll`)
- Removed `SHT_LLVM_BB_ADDR_MAP_V0` tests. Full deprecation of
`SHT_LLVM_BB_ADDR_MAP_V0` and `SHT_LLVM_BB_ADDR_MAP` version less than 2
will happen in a separate PR in a few months.
Commit: 3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
https://github.com/llvm/llvm-project/commit/3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
Log Message:
-----------
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)
Commit: 58c494f47cf56a30bf50024d22661c75003db809
https://github.com/llvm/llvm-project/commit/58c494f47cf56a30bf50024d22661c75003db809
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (#79399)
This is a good portion of the extensions mentioned in the RVA23 profile
here
https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc
I don't believe these add any new CSRs. Sstc does add new CSRs, but we
already added them without the extension name a while back.
I tried to keep the descriptions in RISCVFeatures.td fairly short since
the strings show up in `-print-supported-extensions`.
Commit: 082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
https://github.com/llvm/llvm-project/commit/082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Remove duplicate expression (#80380)
Reported by cpp check static analyzer in #80111.
Fixes #80111.
Commit: e270ec47cda26a8f0a3cdd195aa60992f109df8a
https://github.com/llvm/llvm-project/commit/e270ec47cda26a8f0a3cdd195aa60992f109df8a
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
Log Message:
-----------
[X86] X86InstrInfo.cpp - Remove dead code for memory folding, NFCI
`commuteInstruction(MI, false, OpNum, CommuteOpIdx2)` should never create
any new instruction, so we don't need to check and erase it.
Commit: 7dd790db8b77c4a833c06632e903dc4f13877a64
https://github.com/llvm/llvm-project/commit/7dd790db8b77c4a833c06632e903dc4f13877a64
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
[lldb] NFC fixes addressing David's feedback
David Spickett had several suggestions for
https://github.com/llvm/llvm-project/pull/79962 after I'd
already merged it. Address those.
Commit: dee8786f70a3d62b639113343fa36ef55bdbad63
https://github.com/llvm/llvm-project/commit/dee8786f70a3d62b639113343fa36ef55bdbad63
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/insert-before.test
Log Message:
-----------
[ELF] Fix compareSections assertion failure when OutputDescs in sectionCommands are non-contiguous
In a `--defsym y0=0 -T a.lds` link where a.lds contains only INSERT
commands, the `script->sectionCommands` layout may be:
```
orphan sections
SymbolAssignment due to --defsym
sections created by INSERT commands
```
The `OutputDesc` objects are not contiguous in sortInputSections, and
`compareSections` will be called with a SymbolAssignment argument,
leading to an assertion failure.
Commit: 374a600df7207fbe2002e754a799c7595a0e4833
https://github.com/llvm/llvm-project/commit/374a600df7207fbe2002e754a799c7595a0e4833
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[MachinePipeliner] Fix missing requirements for tests (#80386)
Add asserts requirements for tests that verify debug output.
Commit: 2147a2a4f3ef344a561677b55444ce4d028ec59f
https://github.com/llvm/llvm-project/commit/2147a2a4f3ef344a561677b55444ce4d028ec59f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/auto-type.c
Log Message:
-----------
[clang][Interp] Not all TypeTraitExprs are of bool type
In C, they return an integer, so emit their value as such.
Commit: 58ceefe09cd992c3692bb3af7c2807ac8949ba67
https://github.com/llvm/llvm-project/commit/58ceefe09cd992c3692bb3af7c2807ac8949ba67
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Support ChooseExprs
Commit: a2da7d06c7e1ec75812ff8ced29541d4af3668c9
https://github.com/llvm/llvm-project/commit/a2da7d06c7e1ec75812ff8ced29541d4af3668c9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Ignore LValueToRValue casts before doing the load
If the SubExpr results in an invalid pointer, we will otherwise
reject the constant expression.
Commit: 65ac8c16e028b23b49fd6b03817faa1ab6c0229d
https://github.com/llvm/llvm-project/commit/65ac8c16e028b23b49fd6b03817faa1ab6c0229d
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir] Skip invalid test on big endian platform (s390x) (#80246)
The buildbot test running on s390x platform keeps failing since [this
time](https://lab.llvm.org/buildbot/#/builders/199/builds/31136). This
is because of the dependency on the endianness of the platform. It
expects the format invalid in the big endian platform (s390x). We can
simply skip it.
See: https://discourse.llvm.org/t/mlir-s390x-linux-failure/76695
Commit: a8b5994b337cf1d461202a65204a4ee6c5eae341
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp][NFC] Add a broken test case
The LHS of the subtraction returns 16 right now, but should
return 0.
Commit: d9c20e437fe110fb79b5ca73a52762e5b930b361
https://github.com/llvm/llvm-project/commit/d9c20e437fe110fb79b5ca73a52762e5b930b361
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aarch64-inline-asm.c
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
Log Message:
-----------
[AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276)
This enables specifing "za" or "zt0" to the clobber list for inline asm.
This complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276
Commit: 0be39155bd22258b3e90468b6184bfd87a948bec
https://github.com/llvm/llvm-project/commit/0be39155bd22258b3e90468b6184bfd87a948bec
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/Sema/warn-cast-qual.c
Log Message:
-----------
[clang][Interp] Protect stores against dummy pointers
Commit: 3be79790ede30762f73b95218be8877c3b2c3774
https://github.com/llvm/llvm-project/commit/3be79790ede30762f73b95218be8877c3b2c3774
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang] Update documentation for `#pragma diagnostic` (#78095)
GCC has changed over the past decade, and we're not implementing
everything they do.
Fixes #51472
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 75c4339ef31922bf8c883a7a5dfe638ec6818ab2
https://github.com/llvm/llvm-project/commit/75c4339ef31922bf8c883a7a5dfe638ec6818ab2
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/EvaluationResult.cpp
Log Message:
-----------
[clang][Interp][NFC] Implement dumping Invalid/Valid results
This was just an omission from an earlier commit, clearly
we can print them.
Commit: 0f26441cb83c1dea9aef12c748a79e3f38e3230a
https://github.com/llvm/llvm-project/commit/0f26441cb83c1dea9aef12c748a79e3f38e3230a
Author: Maciej Gabka <maciej.gabka at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[TLI][AArch64] Adjust TLI mappings to vector functions taking linear pointers (#80296)
The masked symbols in SLEEF are incorrectly implemented as calls to non
masked variants, what only works fine for functions which do not modify
memory.
For vector variants which modify memory we can only use a non masked
symbols for now.
The SVE ArmPL mappings need to be removed for now as well.
Commit: 237a799e938aca86dc7e62def792b26974bbae5d
https://github.com/llvm/llvm-project/commit/237a799e938aca86dc7e62def792b26974bbae5d
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/IR/Builders.cpp
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Notify about block insertion when cloning an op (#80262)
`OpBuilder::clone(Operation &)` should trigger not only
`notifyOperationInserted` but also `notifyBlockInserted` (for all block
contained in `op`).
Commit: a792cb6e3e03aff22dabb6cc94db68d15d953a55
https://github.com/llvm/llvm-project/commit/a792cb6e3e03aff22dabb6cc94db68d15d953a55
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/IR/Builders.cpp
Log Message:
-----------
[mlir][IR] Do not trigger `notifyOperationInserted` for unlinked ops (#80278)
This commit changes `OpBuilder::create` and `OpBuilder::createOrFold`
such that `notifyOperationInserted` is no longer triggered if no
insertion point is set. In such a case, an unlinked operation is created
but not inserted, so `notifyOperationInserted` should not be triggered.
Note: Inserting another op into a block that belongs to an unlinked op
(e.g., by the builder of the unlinked op) will trigger a notification.
Commit: c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
https://github.com/llvm/llvm-project/commit/c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
Author: ManuelvOK <info at manuel-thieme.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
Log Message:
-----------
[Coverage] Map regions from system headers (#76950)
In 2155195131a57f2f01e7cfabb85bb027518c2dc6, the
"system-headers-coverage" option has been added but not used in all
necessary places.
This is the recommit since it has been reverted in
faef68bca852d08511ea0311d8a0d221cb202e73
Potential reviewers: @gulfemsavrun @petrhosek
Co-authored-by: Manuel Kalettka <manuel.kalettka at kernkonzept.com>
Commit: b840d2968391dd610b792a65133a1edc1bcc397c
https://github.com/llvm/llvm-project/commit/b840d2968391dd610b792a65133a1edc1bcc397c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Send notifications for `cloneRegionBefore` (#66871)
Similar to `OpBuilder::clone`, operation/block insertion notifications
should be sent when cloning the contents of a region. E.g., this is to
ensure that the newly created operations are put on the worklist of the
greedy pattern rewriter driver.
Also move `cloneRegionBefore` from `RewriterBase` to `OpBuilder`. It
only creates new IR, so it should be part of the builder API (like
`clone(Operation &)`). The function does not have to be virtual. Now
that notifications are properly sent, the override in the dialect
conversion is no longer needed.
Commit: 73e546625d6567e5a33454741d257b6929c89635
https://github.com/llvm/llvm-project/commit/73e546625d6567e5a33454741d257b6929c89635
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix up broken test case
This was not working right on armv8:
https://lab.llvm.org/buildbot/#/builders/245/builds/20020
Commit: 9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
https://github.com/llvm/llvm-project/commit/9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[mlir][memref] `memref.subview`: Verify result strides with rank reductions (#80158)
This is a follow-up on #79865. Result strides are now also verified if
the `memref.subview` op has rank reductions.
Commit: 9e649518e6038a5b9ea38cfa424468657d3be59e
https://github.com/llvm/llvm-project/commit/9e649518e6038a5b9ea38cfa424468657d3be59e
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/init-aarch64.c
Log Message:
-----------
[Clang][AArch64] Add missing SME macros (#80293)
__ARM_STATE_ZA and __ARM_STATE_ZT0 are set when the compiler can parse
the "za" and "zt0" strings in the SME attributes.
__ARM_FEATURE_SME and __ARM_FEATURE_SME2 are set when the compiler can
generate code for attributes with "za" and "zt0" state, respectively.
__ARM_FEATURE_LOCALLY_STREAMING is set when the compiler supports the
__arm_locally_streaming attribute.
Commit: 438fe1db09b0c20708ea1020519d8073c37feae8
https://github.com/llvm/llvm-project/commit/438fe1db09b0c20708ea1020519d8073c37feae8
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
Log Message:
-----------
CoverageMappingWriter: Emit `Decision` before `Expansion` (#78966)
To relax scanning record, tweak order by `Decision < Expansion`, or
`Expansion` could not be distinguished whether it belonged to `Decision`
or not.
Relevant to #77871
Commit: acf6811d0f2b6b453be46ddf7e046e1346991c98
https://github.com/llvm/llvm-project/commit/acf6811d0f2b6b453be46ddf7e046e1346991c98
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
A llvm/test/TableGen/deftype.td
Log Message:
-----------
[TableGen] Support type aliases via new keyword deftype
We can use `deftype` (not using `typedef` here to be consistent
with `def`, `defm`, `defset`, `defvar`, etc) to define type aliases.
Currently, only primitive types and type aliases are supported to be
the source type and `deftype` statements can only appear at the top
level.
Reviewers: fpetrogalli, Artem-B, nhaehnle, jroelofs
Reviewed By: jroelofs, nhaehnle, Artem-B
Pull Request: https://github.com/llvm/llvm-project/pull/79570
Commit: a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
https://github.com/llvm/llvm-project/commit/a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Lex/PPMacroExpansion.cpp
A clang/test/Preprocessor/has_builtin_cpuid.c
Log Message:
-----------
[Preprocessor] Fix __has_builtin for CPU ID functions (#80058)
My recent commit (67c1c1d) made the CPU ID builtins target-independent
so they can be used on PPC as well. However, that had the unintended
consequence of changing the behaviour of __has_builtin in that it
reports these as supported at the pre-processor level. This makes it
impossible to guard the use of these with this feature test macro which
is clearly not ideal.
This patch restores the behaviour of __has_builtin for __builtin_cpu_is,
__builtin_cpu_init,
__builtin_cpu_supports. Now the preprocessor queries the target to
determine whether the target supports the builtin.
Commit: 42ec9934e1079742e0b5d839e420bc3f746fc73b
https://github.com/llvm/llvm-project/commit/42ec9934e1079742e0b5d839e420bc3f746fc73b
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Fix gcc -Wparentheses warning [NFC]
Without this gcc warns like
../lib/Target/PowerPC/PPCAsmPrinter.cpp:1650:33: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
1650 | (InstDisp >= -32768) &&
| ~~~~~~~~~~~~~~~~~~~~~^~
1651 | "Expecting the instruction displacement for local-exec TLS "
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1652 | "variables to be between [-32768, 32768)!");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
https://github.com/llvm/llvm-project/commit/5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[SCEVExpander] Do not reuse disjoint or (#80281)
SCEV treats "or disjoint" the same as "add nsw nuw". However, when
expanding, we cannot generally replace an add SCEV node with an "or
disjoint" instruction. Just dropping the poison flag is insufficient in
this case, we would have to actually convert the or into an add.
This is a partial fix for #79861.
Commit: 84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
https://github.com/llvm/llvm-project/commit/84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
Log Message:
-----------
[MLIR][Vector] Implement memory effect for print (#80400)
Add write memory effect for the print operation. The exact memory
behavior is implemented in other print-like operations such as
`transform::PrintOp` or `gpu::printf`.
Providing memory behavior allows using the operation in passes like
buffer deallocation instead of emitting an error.
Commit: c2dea7122cd9f559f64cd0b34431d21e61f5bf15
https://github.com/llvm/llvm-project/commit/c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
Log Message:
-----------
[mlir][ArmSME] Fold extracts from 3D create_masks of SME-like masks (#80148)
When unrolling the reduction dimension of something like a matmul for
SME, it is possible to get 3D masks, which are vectors of SME-like
masks. The 2D masks for individual operations are then extracted from
the 3D masks.
i.e.:
```mlir
%mask = vector.create_mask %nonConstantDim, %a, %b : vector<4x[4]x[4]xi1>
%subMask = vector.extract %mask[2]
: vector<[4]x[4]xi1> from vector<4x[4]x[4]xi1>
```
ArmSME only supports lowering 2D create_masks, so we must fold the
extract into the create_mask. This can be done by checking if the
extraction index is within the true region, then using that select the
first dimension of the 2D mask. This is shown below.
```mlir
%extractionInTrueRegion = arith.cmpi slt, %c2, %nonConstantDim : index
%newMaskFrontDim = arith.select %extractionInTrueRegion, %a, %c0 : index
%subMask = vector.create_mask %newMaskFrontDim, %b : vector<[4]x[4]xi1>
```
Commit: 6d1d2c67e7597dc417c097d5027558b0159ed2e2
https://github.com/llvm/llvm-project/commit/6d1d2c67e7597dc417c097d5027558b0159ed2e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
[clang] Fix a possible out-of-bounds read (#80023)
Fixes #79964
Commit: 4b8e514334786e1aa6f86d7d777385aa9702d835
https://github.com/llvm/llvm-project/commit/4b8e514334786e1aa6f86d7d777385aa9702d835
Author: Tuan Chuong Goh <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Pre-Commit tests for Legalize BSWAP Vectors
Commit: 2cf415f2a03433fd3661938fb2f4af0754ad2274
https://github.com/llvm/llvm-project/commit/2cf415f2a03433fd3661938fb2f4af0754ad2274
Author: Peter Smith <peter.smith at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/SecurityTransparencyReports.rst
Log Message:
-----------
Add security group 2023 transparency report. (#80320)
Commit: ffb3589b8cb3468713d25ff2a4378918eafa7044
https://github.com/llvm/llvm-project/commit/ffb3589b8cb3468713d25ff2a4378918eafa7044
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Remove transitive <locale> include from <vector> (#80282)
This reduces the time to include `<vector>` from 468ms to 367ms.
Commit: 9410019ac977141bc73aee19690b5896ded59219
https://github.com/llvm/llvm-project/commit/9410019ac977141bc73aee19690b5896ded59219
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-combine.ll
M llvm/test/CodeGen/X86/popcnt.ll
Log Message:
-----------
[X86] Add i8 CTPOP lowering using i32 MUL (#79989)
This is the first basic proposal in #79823 - we can investigate improving support for other widths if we can find further use cases.
Commit: 10943695f76f513503162026669e84cb72275e84
https://github.com/llvm/llvm-project/commit/10943695f76f513503162026669e84cb72275e84
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)
Add support of i16 vector operation for BSWAP and change to TableGen to
select instructions
Handle vector types that are smaller/larger than legal for BSWAP
Commit: cca9f9b78fc657c280f7e4024a552af43a315bdb
https://github.com/llvm/llvm-project/commit/cca9f9b78fc657c280f7e4024a552af43a315bdb
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Commit: 2d1f5af8b0b07a4ac19eae699aa660debb1a5613
https://github.com/llvm/llvm-project/commit/2d1f5af8b0b07a4ac19eae699aa660debb1a5613
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
Use !tolower instead of repeating the name when defining a renamed Real
instruction.
Commit: 589b21f38932ed1150906fc30307f030c62f6e8f
https://github.com/llvm/llvm-project/commit/589b21f38932ed1150906fc30307f030c62f6e8f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__memory/temporary_buffer.h
Log Message:
-----------
[libc++][NFC] Remove <__type_traits/alignment_of.h> include
Commit: 2e669ff59ebb096d67d02ec51dbb7050dc5e2235
https://github.com/llvm/llvm-project/commit/2e669ff59ebb096d67d02ec51dbb7050dc5e2235
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerBuildVector* - share the same SDLoc argument instead of recreating it over and over again.
Commit: b5d35feacb7246573c6a4ab2bddc4919a4228ed5
https://github.com/llvm/llvm-project/commit/b5d35feacb7246573c6a4ab2bddc4919a4228ed5
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/avx512-arith.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/combine-addo.ll
M llvm/test/CodeGen/X86/combine-and.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-pavg.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/combine-sub.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/combine-urem.ll
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/extract-concat.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-shuffle.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/packus.ll
M llvm/test/CodeGen/X86/paddus.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/pr48215.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr61964.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/pr63507.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-512.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-512.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - load+sign-extend vector constants that can be stored in a truncated form (#79815)
Reduce the size of the vector constant by storing it in the constant pool in a truncated form, and sign-extend it as part of the load.
I've extended the existing FixupConstant functionality to support these sext constant rebuilds - we still select the smallest stored constant entry and prefer vzload/broadcast/vextload for same bitwidth to avoid domain flips.
I intend to add the matching load+zero-extend handling in a future PR, but that requires some alterations to the existing MC shuffle comments handling first.
Commit: ffd84a6a9afc43968fe24c9057bd4f86e148e283
https://github.com/llvm/llvm-project/commit/ffd84a6a9afc43968fe24c9057bd4f86e148e283
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in MemRefOps.cpp (NFC)
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2763:23:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() == droppedDims.size() && "incorrect number of bits");
~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2764:38:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() - t2.getRank() == droppedDims.count() &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~
Commit: d912f1f0cb49465b08f82fae89ece222404e5640
https://github.com/llvm/llvm-project/commit/d912f1f0cb49465b08f82fae89ece222404e5640
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
A llvm/test/tools/llvm-cov/mcdc-macro.test
Log Message:
-----------
[Coverage] Let `Decision` take account of expansions (#78969)
The current implementation (D138849) assumes `Branch`(es) would follow
after the corresponding `Decision`. It is not true if `Branch`(es) are
forwarded to expanded file ID. As a result, consecutive `Decision`(s)
would be confused with insufficient number of `Branch`(es).
`Expansion` will point `Branch`(es) in other file IDs if `Expansion` is
included in the range of `Decision`.
Fixes #77871
---------
Co-authored-by: Alan Phipps <a-phipps at ti.com>
Commit: 4cf2ed4396ddeda1487d6c5151a7dfdf14573920
https://github.com/llvm/llvm-project/commit/4cf2ed4396ddeda1487d6c5151a7dfdf14573920
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Fix -Wsign-compare in X86MCInstLower.cpp (NFC)
llvm-project/llvm/lib/Target/X86/X86MCInstLower.cpp:1588:48:
error: comparison of integers of different signs: 'unsigned int' and 'int' [-Werror,-Wsign-compare]
if (C && C->getType()->getScalarSizeInBits() == SrcEltBits) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~
1 error generated.
Commit: 319f4c03ba2909c7240ac157cc46216bf1518c10
https://github.com/llvm/llvm-project/commit/319f4c03ba2909c7240ac157cc46216bf1518c10
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/aarch64-sme-func-attrs.c
Log Message:
-----------
[Clang][AArch64] Emit 'unimplemented' diagnostic for SME (#80295)
When a function F has ZA and ZT0 state, calls another function G that
only shares ZT0 state with its caller, F will have to save ZA before
the call to G, and restore it afterwards (rather than setting up a
lazy-sve).
This is not yet implemented in LLVM and does not result in a
compile-time error either. So instead of silently generating incorrect
code, it's better to emit an error saying this is not yet implemented.
Commit: b8025d1482a9664463cfc727a0e51cad86fdf2fe
https://github.com/llvm/llvm-project/commit/b8025d1482a9664463cfc727a0e51cad86fdf2fe
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
Reapply "[AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode." (#80303)
Reapply #71556 with added lit test constraint: `REQUIRES: amdgpu-registered-target`.
This reverts commit 9791e5414960f92396582b9e9ee503ac15799312.
Commit: c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
https://github.com/llvm/llvm-project/commit/c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
Log Message:
-----------
[SCEV] Add SCEV analysis tests with congruent IVs.
This patch adds a set of tests taken
from/llvm/test/Transforms/IndVarSimplify/iv-poison.ll with multiple
congruent IVs but different set of flags on the increments.
Extra tests for https://github.com/llvm/llvm-project/pull/80430.
Commit: 7a4570acdb1a32935d96831142748ba3298a2b7f
https://github.com/llvm/llvm-project/commit/7a4570acdb1a32935d96831142748ba3298a2b7f
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/HLFIR/array-ctor-character.f90
Log Message:
-----------
[flang] sanitize set_length in lowering (#80412)
In fortran, it is possible to give a negative "i" in "character(i)" in
which case the standard says the length is zero. So the length must be
sanitized as max(0, user_input) in lowering.
This is already done when lowering specification parts, but was not done
when "character(i)" appears in array constructors. Sanitize the length
when lowering SetLength in lowering.
Fixes https://github.com/llvm/llvm-project/issues/80270
Commit: 92bbf615f50c67030ed536f08cc5bb266e0718db
https://github.com/llvm/llvm-project/commit/92bbf615f50c67030ed536f08cc5bb266e0718db
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Use function-attached target attributes for OpenMP lowering (#78291)
This patch removes the omp.target module attribute, since the
information it held on the target CPU and features is available through
the fir.target_cpu and fir.target_features module attributes. Target
outlining during the MLIR to LLVM IR translation stage is updated, so
that these attributes, at that point available as llvm.func attributes,
are passed along to the newly created function.
Commit: 3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
https://github.com/llvm/llvm-project/commit/3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] FP<->INT helpers - share the same SDLoc argument instead of recreating it over and over again.
Commit: a1df10da59e8eb0c1d90df81bf9000d2f7869328
https://github.com/llvm/llvm-project/commit/a1df10da59e8eb0c1d90df81bf9000d2f7869328
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
AMDGPU/NFC: Add predicate for supporting ds_add_f64 (#80379)
Commit: 1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
https://github.com/llvm/llvm-project/commit/1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix broken test case again
Instead of asserting that it's wrong, assert the correct
value.
See the discussion in
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Commit: 274d1b000cae57acf2dc988fcb65cfe7383ed2b0
https://github.com/llvm/llvm-project/commit/274d1b000cae57acf2dc988fcb65cfe7383ed2b0
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[NFC] Add useFPRegsForHalfType(). (#74147)
Currently, half operations can be promoted in one of two ways.
* If softPromoteHalfType() returns false, fp16 values are passed around
in fp32 registers, and whole chains of fp16 operations are promoted to
fp32 in one go.
* If softPromoteHalfType() returns true, fp16 values are passed around
in i16 registers, and individual fp16 operations are promoted to fp32
and the result truncated to fp16 right away.
The softPromoteHalfType behavior is necessary for correctness, but
changing this for an existing target breaks the ABI. Therefore, this
commit adds a third option:
* If softPromoteHalfType() returns true and useFPRegsForHalfType()
returns true as well, fp16 values are passed around in fp32 registers,
but individual fp16 operations are promoted to fp32 and the result
truncated to fp16 right away.
This change does not yet update any target to make use of it.
Commit: 1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
https://github.com/llvm/llvm-project/commit/1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
Author: lifengxiang1025 <lifengxiang.1025 at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
Log Message:
-----------
[MemProf] Fix when CallStackTrie has a single chain to leaf with multi alloc type (#79433)
Fix one corner case when `CallStackTrie` has a single chain to leaf with
multi alloc type. This will cause stackIds in function summary is empty.
Commit: 275729ae06d568e9589392c142a416fb8c2bb1a8
https://github.com/llvm/llvm-project/commit/275729ae06d568e9589392c142a416fb8c2bb1a8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
Log Message:
-----------
[X86] Generalize i8 CTPOP expansion to work with any input with 8 or less active bits
Extend #79989 slightly to use KnownBits on the CTPOP input - this should make it easier to add additional cases identified in #79823
Commit: 66b339aa6ba3ee63806c87630aec1dc6a45e63c5
https://github.com/llvm/llvm-project/commit/66b339aa6ba3ee63806c87630aec1dc6a45e63c5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
Log Message:
-----------
[IndVars] Regenerate test checks (NFC)
Commit: a986f5e218ab8a68097fcc1fd3234b8743839ef8
https://github.com/llvm/llvm-project/commit/a986f5e218ab8a68097fcc1fd3234b8743839ef8
Author: alexfh <alexfh at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
Fix clang crash when printing highlighted code in diagnostic (after #66514) (#80442)
Implements the fix proposed by Evgeny Eltsin on
https://github.com/llvm/llvm-project/pull/66514#issuecomment-1924039038.
No test case provided, since the bug is extremely sensitive to the
preprocessor
state (headers, macros, including the ones defined on command line), and
it
turned out to be non-trivial to create an isolated test.
Commit: fbf9356be07408efc05621a7a8d0472a61c66228
https://github.com/llvm/llvm-project/commit/fbf9356be07408efc05621a7a8d0472a61c66228
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Add ctpop-mask.ll - test coverage based off #79823
Commit: 46b6756255029f442165148115bad99d04057622
https://github.com/llvm/llvm-project/commit/46b6756255029f442165148115bad99d04057622
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
M clang/test/Driver/hip-options.hip
Log Message:
-----------
[AMDGPU] Diagnose unaligned atomic (#80322)
AMDGPU does not support unaligned atomics, therefore make the warning an
error.
This patch is transferred from
https://reviews.llvm.org/D99201
Commit: 43dd1e84df1ecdad872e1004af47b489e08fc228
https://github.com/llvm/llvm-project/commit/43dd1e84df1ecdad872e1004af47b489e08fc228
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[SCEV] Move canReuseInstruction() helper into SCEV (NFC)
To allow reusing it in IndVars.
Commit: 7524b037257cdeb67e3ed80364da94eab8e98122
https://github.com/llvm/llvm-project/commit/7524b037257cdeb67e3ed80364da94eab8e98122
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add note about calendar timezones (#80346)
Commit: 67eee4a029797c09129889c3655416d1be487cfe
https://github.com/llvm/llvm-project/commit/67eee4a029797c09129889c3655416d1be487cfe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
[libc++] Optimize vector growing of trivially relocatable types (#76657)
This patch introduces a new trait to represent whether a type is
trivially
relocatable, and uses that trait to optimize the growth of a std::vector
of trivially relocatable objects.
```
--------------------------------------------------
Benchmark old new
--------------------------------------------------
bm_grow<int> 1354 ns 1301 ns
bm_grow<std::string> 5584 ns 3370 ns
bm_grow<std::unique_ptr<int>> 3506 ns 1994 ns
bm_grow<std::deque<int>> 27114 ns 27209 ns
```
This also changes to order of moving and destroying the objects when
growing the vector. This should not affect our conformance.
Commit: 30503116550c2bffe706366e93dbaee15850014c
https://github.com/llvm/llvm-project/commit/30503116550c2bffe706366e93dbaee15850014c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 67eee4a02979
Commit: b629414ae13d6dcd641e92d0389c5d4b7638a644
https://github.com/llvm/llvm-project/commit/b629414ae13d6dcd641e92d0389c5d4b7638a644
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
Log Message:
-----------
[libc][NFC] Simplify logic in `sqrt` (#80426)
Commit: 28865da37451904c4654f20cdaddee815fdeff1d
https://github.com/llvm/llvm-project/commit/28865da37451904c4654f20cdaddee815fdeff1d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Log Message:
-----------
[LSR][term-fold] Adjust expansion budget based on trip count (#80304)
Follow up to https://github.com/llvm/llvm-project/pull/74747
This change extends the previously added fixed expansion threshold by
scaling down the cost allowed for an expansion for a loop with either a
small known trip count or a profile which indicates the trip count is
likely small. The goal here is to improve code generation for a loop
nest where the outer loop has a high trip count, and the inner loop runs
only a handful of iterations.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 1437a83491cbe4af1b452a3f862a6b609057c26d
https://github.com/llvm/llvm-project/commit/1437a83491cbe4af1b452a3f862a6b609057c26d
Author: Rushi Bhamani <99245918+rushiraj7677 at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
Log Message:
-----------
Add --abort-on-invalid-reduction to more lit tests (#80263)
Commit: b78b264518e0f341d99a4291cbf24134c7536f6d
https://github.com/llvm/llvm-project/commit/b78b264518e0f341d99a4291cbf24134c7536f6d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/RISCV/gep.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[TTI] Add costing for vp.strided.load and vp.strided.store (#80360)
The primary motivation of this patch is to add testing infrastructure
atop the recently landed 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7, so
that we can separate the costing aspects of strided memory operations
from the SLP implementation details.
I want to be clear that I am *not* proposing that we use the
vp.strided.* forms as our canonical IR representation. I'm merely using
them as a testing vehicle to exercise the costing machinery. The
canonical IR form remains a masked.gather or masked.scatter. I do want
to explore adding a non-vp strided load/store intrinsic, but that's a
separate line of work.
There is one costing change included in this. As I wrote my test, I
discovered that the default implementation was scalarized (if invoked
via generic routines such as getInstructionCost), and when adding the
call into the strided specific costing discovered that we hadn't modeled
the fallback to scalarization properly in the initial patch. After
fixing that, there is a minor difference in scalarization cost reported
for the unaligned case but I believe that to be uninteresting.
For the record, I did confirm that vp.strided.store is lowered to a
strided store on RISCV. :)
Commit: a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
https://github.com/llvm/llvm-project/commit/a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
Author: Manish Kausik H <46352931+Nirhar at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
A llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
Log Message:
-----------
[SelectionDAG] Use unaligned store to move AVX registers onto stack for `extractelement` (#78422)
Prior to this patch, SelectionDAG generated aligned move onto stacks for
AVX registers when the function was marked as a no-realign-stack
function. This lead to misalignment between the stack and the
instruction generated. This patch fixes the issue.
Fixes #77730
Commit: 7b08b4360b488b35428c97132b3f9d2a777bd770
https://github.com/llvm/llvm-project/commit/7b08b4360b488b35428c97132b3f9d2a777bd770
Author: Nathan Gauër <brioche at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
Log Message:
-----------
[SPIR-V] add convergence region analysis (#78456)
This new analysis returns a hierarchical view of the convergence regions
in the given function.
This will allow our passes to query which basic block belongs to which
convergence region, and structurize the code in consequence.
Definition
----------
A convergence region is a CFG with:
- a single entry node.
- one or multiple exit nodes (different from LLVM's regions).
- one back-edge
- zero or more subregions.
Excluding sub-regions nodes, the nodes of a region can only reference a
single convergence token. A subregion uses a different convergence
token.
Algorithm
---------
This algorithm assumes all loops are in the Simplify form.
Create an initial convergence region for the whole function.
- the convergence token is the function entry token.
- the entry is the function entrypoint.
- Exits are all the basic blocks terminating with a return instruction.
Take the function CFG, and process it in DAG order (ignoring
back-edges). If a basic block is a loop header:
- Create a new region.
- The parent region is the parent's loop region if any, otherwise, the
top level region.
- The region blocks are all the blocks belonging to this loop.
- For each loop exit: - visit the rest of the CFG in DAG order (ignore
back-edges). - if the region's convergence token is found, add all the
blocks dominated by the exit from which the token is reachable to the
region.
- continue the algorithm with the loop headers successors.
Commit: 7ecfb66c77ad77dabbb705cbb1f3b17a3d1391a4
https://github.com/llvm/llvm-project/commit/7ecfb66c77ad77dabbb705cbb1f3b17a3d1391a4
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaTemplate.cpp
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.meaning.general/p3.cpp
Log Message:
-----------
[Clang][Sema] Correctly look up primary template for variable template specializations (#80359)
Consider the following:
```
namespace N0 {
namespace N1 {
template<typename T>
int x1 = 0;
}
using namespace N1;
}
template<>
int N0::x1<int>;
```
According to [dcl.meaning.general] p3.3:
> - If the _declarator_ declares an explicit instantiation or a partial
or explicit specialization, the _declarator_ does not bind a name. If it
declares a class member, the terminal name of the _declarator-id_ is not
looked up; otherwise, **only those lookup results that are nominable in
`S` are considered when identifying any function template specialization
being declared**.
In particular, the requirement for lookup results to be nominal in the
lookup context of the terminal name of the _declarator-id_ only applies
to function template specializations -- not variable template
specializations. We currently reject the above declaration, but we do
(correctly) accept it if the using-directive is replaced with a `using`
declaration naming `N0::N1::x1`. This patch makes it so the above
specialization is (correctly) accepted.
Commit: 3a758076f54d521d20e32856a62c7d24803ee9e8
https://github.com/llvm/llvm-project/commit/3a758076f54d521d20e32856a62c7d24803ee9e8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Allow i8 CTPOP expansion to work with a 'shifted' active bits value of 8 bits or less
Shift down the value so the active bits are at the lsb
Commit: faeb3d1f106d607f51babe3770e899bc9bda7f3a
https://github.com/llvm/llvm-project/commit/faeb3d1f106d607f51babe3770e899bc9bda7f3a
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
Log Message:
-----------
[AMDGPU] Regenerate ctpop64.ll test checks
Commit: 1156bbc5b1837e688b0e5d6952f1a900aca29062
https://github.com/llvm/llvm-project/commit/1156bbc5b1837e688b0e5d6952f1a900aca29062
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/TypeLoc.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/drs/dr7xx.cpp
M clang/test/CXX/temp/temp.decls/temp.class/temp.mem.func/p1.cpp
A clang/test/CXX/temp/temp.names/p5.cpp
M clang/test/CXX/temp/temp.spec/part.spec.cpp
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaTemplate/class-template-spec.cpp
Log Message:
-----------
[Clang][Sema] Diagnose use of template keyword after declarative nested-name-specifiers (#78595)
According to [temp.names] p5:
> The keyword template shall not appear immediately after a declarative nested-name-specifier.
[expr.prim.id.qual] p2 defines a declarative nested-name-specifier as follows:
> A nested-name-specifier is declarative if it is part of
> - a class-head-name,
> - an enum-head-name,
> - a qualified-id that is the id-expression of a declarator-id, or
> - a declarative nested-name-specifier.
Note: I believe this definition is defective as it doesn't include _nested-name-specifiers_ appearing in _elaborated-type-specifiers_ that declare partial/explicit specializations and explicit instantiations. See my post to the core reflector. Minus a few bugs that are addressed by this PR, this is how we implement it.
This means that declarations like:
```
template<typename>
struct A
{
template<typename>
struct B
{
void f();
};
};
template<typename T>
template<typename U>
void A<T>::template B<U>::f() { } // error: 'template' cannot be used after a declarative nested name specifier
```
are ill-formed. This PR add diagnostics for such declarations. The name of the diagnostic group is `template-in-declaration-name`.
Regarding the aforementioned "few bugs that are addressed by this PR" in order to correctly implement this:
- `CheckClassTemplate` did not call `diagnoseQualifiedDeclaration` when the semantic context was dependent. This allowed for constructs like:
```
struct A
{
template<typename T>
struct B
{
template<typename U>
struct C;
};
};
template<typename T>
template<typename U>
struct decltype(A())::B<T>::C { };
```
- `ActOnClassTemplateSpecialization` did not call `diagnoseQualifiedDeclaration` at all, allowing for qualified partial/explicit specializations at class scope and other related nonsense
- `TreeTransform::TransformNestedNameSpecifierLoc` would rebuild a `NestedNameSpecifier::TypeSpecWithTemplate` as a `NestedNameSpecifier::TypeSpec`
- `TemplateSpecializationTypeLoc::initializeLocal` would set the `template` keyword `SourceLocation` to the provided `Loc` parameter, which would result in a `TemplateSpecializationTypeLoc` obtained via `ASTContext::getTrivialTypeSourceInfo` being displayed as always having a `template` prefix (since the presence of the keyword is not stored anywhere else).
Commit: 9cc2122bf5a81f7063c2a32b2cb78c8d615578a1
https://github.com/llvm/llvm-project/commit/9cc2122bf5a81f7063c2a32b2cb78c8d615578a1
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/LanguageExtensions.rst
M clang/include/clang/Basic/TokenKinds.def
M clang/lib/Sema/SemaExprCXX.cpp
M clang/test/SemaCXX/type-traits.cpp
M libcxx/include/__type_traits/is_nothrow_convertible.h
Log Message:
-----------
[Clang][libc++] Implement __is_nothrow_convertible and use it in libc++ (#80436)
GCC 13 has implemented this builtin.
Commit: d4de4c3eafa9b70c255a4d6d5a14dccff79d10e9
https://github.com/llvm/llvm-project/commit/d4de4c3eafa9b70c255a4d6d5a14dccff79d10e9
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/Sema/inline-asm-validate-aarch64.c
M llvm/docs/LangRef.rst
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
Log Message:
-----------
[AArch64] Support optional constant offset for constraint "S" (#80255)
Modify the initial implementation (https://reviews.llvm.org/D46745) to
support a constant offset so that the following code will compile:
```
int a[2][2];
void foo() { asm("// %0" :: "S"(&a[1][1])); }
```
We use the generic code path for "s". In GCC's aarch64 port, "S" is
supported for PIC while "s" isn't, making "s" less useful. We implement
"S" but not "s".
Similar to #80201 for RISC-V.
Commit: ef1f999e13bd58394bc1099c87a470d91682153d
https://github.com/llvm/llvm-project/commit/ef1f999e13bd58394bc1099c87a470d91682153d
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M lld/wasm/InputFiles.cpp
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/Object/Wasm.h
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
Log Message:
-----------
[Object][Wasm] Move WasmSymbolInfo directly into WasmSymbol (NFC) (#80219)
Move the WasmSymbolInfos from their own vector on the WasmLinkingData
directly into the WasmSymbol object. Removing the const-ref to an
external object allows the vector of WasmSymbols to be safely
expanded/reallocated; generating symbol info from the name section will
require this, as the numbers of function and data segment names are
stored separately.
This is a step toward generating symbol information from name sections
for #76107
Commit: 74fb205876be681d2ca9d8bdd23e171e671df5e1
https://github.com/llvm/llvm-project/commit/74fb205876be681d2ca9d8bdd23e171e671df5e1
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.signed_integral.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.unsigned_integral.pass.cpp
Log Message:
-----------
[libc++][format] Improves tests. (#76291)
Tests the returned type. This was first done for the vector<bool>
formatters. This adds it to the other formatters where it wasn't done
yet.
Commit: 2dd7afa43b9587cce00aa2df6e494fb81c57820a
https://github.com/llvm/llvm-project/commit/2dd7afa43b9587cce00aa2df6e494fb81c57820a
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M clang/docs/LanguageExtensions.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang/AST/TypeLoc.h
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/TokenKinds.def
M clang/include/clang/Driver/Options.td
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/TypeLoc.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Frontend/TextDiagnostic.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
M clang/test/AST/Interp/c.c
A clang/test/Analysis/html_diagnostics/counter.c
A clang/test/CXX/dcl.decl/dcl.meaning/dcl.meaning.general/p3.cpp
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/drs/dr7xx.cpp
M clang/test/CXX/temp/temp.decls/temp.class/temp.mem.func/p1.cpp
A clang/test/CXX/temp/temp.names/p5.cpp
M clang/test/CXX/temp/temp.spec/part.spec.cpp
M clang/test/CodeGen/aarch64-inline-asm.c
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M clang/test/CoverageMapping/if.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
A clang/test/Driver/basic-block-address-map.c
M clang/test/Driver/hip-options.hip
M clang/test/Preprocessor/aarch64-target-features.c
A clang/test/Preprocessor/has_builtin_cpuid.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/aarch64-sme-func-attrs.c
M clang/test/Sema/auto-type.c
M clang/test/Sema/inline-asm-validate-aarch64.c
M clang/test/Sema/warn-cast-qual.c
M clang/test/SemaCXX/static-assert.cpp
M clang/test/SemaCXX/type-traits.cpp
M clang/test/SemaTemplate/class-template-spec.cpp
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/test/Lower/HLFIR/array-ctor-character.f90
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
M libc/src/stdbit/stdc_leading_ones_uc.cpp
M libc/src/stdbit/stdc_leading_ones_uc.h
M libc/src/stdbit/stdc_leading_ones_ul.cpp
M libc/src/stdbit/stdc_leading_ones_ul.h
M libc/src/stdbit/stdc_leading_ones_ull.cpp
M libc/src/stdbit/stdc_leading_ones_ull.h
M libc/src/stdbit/stdc_leading_ones_us.cpp
M libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/src/sys/epoll/linux/epoll_wait.cpp
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__memory/temporary_buffer.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
M libcxx/include/__type_traits/is_nothrow_convertible.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.bool.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.c_string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.char_array.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.floating_point.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.handle.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.pointer.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.signed_integral.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.string.pass.cpp
M libcxx/test/std/utilities/format/format.formatter/format.formatter.spec/formatter.unsigned_integral.pass.cpp
M libcxx/test/support/count_new.h
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/ELF/linkerscript/insert-before.test
A lld/test/ELF/lto/basic-block-address-map.ll
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
M lld/wasm/InputFiles.cpp
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
M llvm/docs/GettingInvolved.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/SecurityTransparencyReports.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/Object/Wasm.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Analysis/CostModel/RISCV/gep.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
A llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/inlineasm-S-constraint.ll
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
M llvm/test/CodeGen/AMDGPU/ctpop64.ll
M llvm/test/CodeGen/RISCV/attributes.ll
A llvm/test/CodeGen/RISCV/pr80052.mir
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/avx512-arith.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
A llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
A llvm/test/CodeGen/X86/basic-block-address-map.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/combine-addo.ll
M llvm/test/CodeGen/X86/combine-and.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-pavg.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/combine-sub.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/combine-urem.ll
M llvm/test/CodeGen/X86/ctpop-combine.ll
A llvm/test/CodeGen/X86/ctpop-mask.ll
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/extract-concat.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-shuffle.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/packus.ll
M llvm/test/CodeGen/X86/paddus.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/CodeGen/X86/pr30821.mir
M llvm/test/CodeGen/X86/pr48215.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr61964.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/pr63507.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
A llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-512.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-512.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/TableGen/deftype.td
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
A llvm/test/tools/llvm-cov/mcdc-macro.test
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
M llvm/unittests/Support/RISCVISAInfoTest.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
A mlir/test/Dialect/SparseTensor/external.mlir
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/python/dialects/memref.py
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
Rebase
Created using spr 1.3.5
Compare: https://github.com/llvm/llvm-project/compare/e909200705f9...2dd7afa43b95
More information about the All-commits
mailing list