[all-commits] [llvm/llvm-project] 021a2b: Uncomment the 2GB max tests and see if that works ...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Fri Feb 2 09:37:13 PST 2024
Branch: refs/heads/users/MaskRay/spr/aarch64-support-optional-constant-offset-for-constraint-s
Home: https://github.com/llvm/llvm-project
Commit: 021a2b4ba254eb9e06fece5c18e5596cbb4896e6
https://github.com/llvm/llvm-project/commit/021a2b4ba254eb9e06fece5c18e5596cbb4896e6
Author: Jason Molenda <jason at molenda.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
Uncomment the 2GB max tests and see if that works on arm-ubuntu
Commit: a9e830910bc07733b7a9d4b935cd12a9041623b3
https://github.com/llvm/llvm-project/commit/a9e830910bc07733b7a9d4b935cd12a9041623b3
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.h
M clang/test/AST/Interp/c.c
M clang/test/Sema/check-increment.c
Log Message:
-----------
[clang][Interp] Protect Inc/Dec ops against dummy pointers
We create them more often in C, so it's more likely to happen there.
Commit: fa98e2861dadaf436b0eb4b38e96a2ccf7c41072
https://github.com/llvm/llvm-project/commit/fa98e2861dadaf436b0eb4b38e96a2ccf7c41072
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.h
Log Message:
-----------
[clang][Interp][NFC] Remove unused RecordScope
Commit: 48f8b74c35991fd3842e135481960449b1e25363
https://github.com/llvm/llvm-project/commit/48f8b74c35991fd3842e135481960449b1e25363
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/Sema/c2x-auto.c
M clang/test/Sema/c2x-bool.c
Log Message:
-----------
[clang][Interp] Support GenericSelectionExprs
Just delegate to the resulting expression.
Commit: 54f324f377a92a64fcc5c1d401da9b07bf50a2f1
https://github.com/llvm/llvm-project/commit/54f324f377a92a64fcc5c1d401da9b07bf50a2f1
Author: Jason Molenda <jason at molenda.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
Trying to refine which test is crashing on arm-ubuntu.
Commit: 65066c02770cc3da3b5154fbb7ed9df78ab94b93
https://github.com/llvm/llvm-project/commit/65066c02770cc3da3b5154fbb7ed9df78ab94b93
Author: Hugo Trachino <32955781+nujaa at users.noreply.github.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Dialect/Tensor/Transforms/ConcatOpPatterns.cpp
Log Message:
-----------
[mlir] Use `create` instead of `createOrFold` for ConstantOp as folding has no effect (NFC) (#80129)
This aims to clean-up confusing uses of
builder.createOrFold<ConstantOp> since folding of constants fails.
Commit: 7ec996d4c5c30083b070be4898140440094e6b97
https://github.com/llvm/llvm-project/commit/7ec996d4c5c30083b070be4898140440094e6b97
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/GlobalISel/MIRPatterns.rst
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
A llvm/test/TableGen/GlobalISelCombinerEmitter/Inputs/test-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/builtin-pattern-errors.td
A llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/pattern-errors.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/pattern-parsing.td
M llvm/test/TableGen/lit.local.cfg
M llvm/utils/TableGen/GlobalISel/Patterns.cpp
M llvm/utils/TableGen/GlobalISel/Patterns.h
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
Log Message:
-----------
[GlobalISel][TableGen] Support Intrinsics in MIR Patterns (#79278)
Commit: e8512786fedbfa6ddba70ceddc29d7122173ba5e
https://github.com/llvm/llvm-project/commit/e8512786fedbfa6ddba70ceddc29d7122173ba5e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[IR] Use range-based for loops (NFC)
Commit: 39fa304866e16f1408a0cab9437e47e4ebacf206
https://github.com/llvm/llvm-project/commit/39fa304866e16f1408a0cab9437e47e4ebacf206
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/utils/TableGen/CodeGenInstruction.cpp
Log Message:
-----------
[llvm] Use StringRef::starts_with (NFC)
Commit: b67ce7e34948d4d954d3cfedb29ffc94861ca0b2
https://github.com/llvm/llvm-project/commit/b67ce7e34948d4d954d3cfedb29ffc94861ca0b2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Frontend/FrontendActions.cpp
Log Message:
-----------
[clang] Use StringRef::starts_with (NFC)
Commit: eaa3d5e26665ca85d488e9194b9fbe304db6fa21
https://github.com/llvm/llvm-project/commit/eaa3d5e26665ca85d488e9194b9fbe304db6fa21
Author: Jason Molenda <jason at molenda.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
Done iterating with arm-ubuntu bot, I see the problem test.
Go back to the original form of this file before I add temp
workaround.
Commit: 90e68086d8fdbfb32dfc7e7e3498f44365274ce8
https://github.com/llvm/llvm-project/commit/90e68086d8fdbfb32dfc7e7e3498f44365274ce8
Author: Jason Molenda <jason at molenda.com>
Date: 2024-01-31 (Wed, 31 Jan 2024)
Changed paths:
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
Skip two WatchpointAlgorithm tests for 32-bit lldb's
After iterating with the arm-ubuntu CI bot, I found the crash (a
std::bad_alloc exception being thrown) was caused by these two
entries when built on a 32-bit machine. I probably have an assumption
about size_t being 64-bits in WatchpointAlgorithms and we have a
problem when it's actually 32-bits and we're dealing with a real
64-bit address. All of the cases where the address can be represented
in the low 32-bits of the addr_t work correctly, so for now I'm
skipping these two unit tests when building lldb on a 32-bit host
until I can review that method and possibly switch to explicit
uin64_t's.
.
Commit: 5fdf8c6faaa572d6c5e58d5c16d3b1e62782f7c4
https://github.com/llvm/llvm-project/commit/5fdf8c6faaa572d6c5e58d5c16d3b1e62782f7c4
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/OperationSupport.h
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Log Message:
-----------
[mlir][Transforms] `GreedyPatternRewriteDriver`: Hash ops separately (#78312)
The greedy pattern rewrite driver has multiple "expensive checks" to
detect invalid rewrite pattern API usage. As part of these checks, it
computes fingerprints for every op that is in scope, and compares the
fingerprints before and after an attempted pattern application.
Until now, each computed fingerprint took into account all nested
operations. That is quite expensive because it walks the entire IR
subtree. It is also redundant in the expensive checks because we already
compute a fingerprint for every op.
This commit significantly improves the running time of the "expensive
checks" in the greedy pattern rewrite driver.
Commit: 84564e1040be8df037d2e9cdbb494aef067e77a7
https://github.com/llvm/llvm-project/commit/84564e1040be8df037d2e9cdbb494aef067e77a7
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/include/flang/Lower/AbstractConverter.h
M flang/lib/Lower/ConvertType.cpp
A flang/test/Lower/derived-types-kind-params-2.f90
Log Message:
-----------
[flang][NFC] Cache derived type translation in lowering (#80179)
Derived type translation is proving expensive in modern fortran apps
with many big derived types with dozens of components and parents.
Extending the cache that prevent recursion is proving to have little
cost on apps with small derived types and significant gain (can divide
compile time by 2) on modern fortran apps.
It is legal since the cache lifetime is less than the MLIRContext
lifetime that owns the cached mlir::Type.
Doing so also exposed that the current caching was incorrect, the type
symbol is the same for kind parametrized derived types regardless of the
kind parameters. Instances with different kinds should lower to
different MLIR types. See added test.
Using the type scopes fixes the problem.
Commit: ae931b470319ade31fcc0797b6051eb8b96f9a8a
https://github.com/llvm/llvm-project/commit/ae931b470319ade31fcc0797b6051eb8b96f9a8a
Author: Wei Wang <apollo.mobility at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Interpreter/cxx20-modules.cppm
Log Message:
-----------
[Clang][test] Limit library search when linking shared lib (#80253)
Don't search for unnecessary libs when linking the shared lib. This
allows the test to run in chroot environment.
Commit: e7d40a87ff230528131541f6ac17a2e1a7dc78e1
https://github.com/llvm/llvm-project/commit/e7d40a87ff230528131541f6ac17a2e1a7dc78e1
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitC.h
A mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitCPass.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/FuncToEmitC/CMakeLists.txt
A mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
A mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Dialect/EmitC/IR/CMakeLists.txt
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
A mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
A mlir/test/Target/Cpp/func.mlir
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][EmitC] Add func, call and return operations and conversions (#79612)
This adds a `func`, `call` and `return` operation to the EmitC dialect,
closely related to the corresponding operations of the Func dialect. In
contrast to the operations of the Func dialect, the EmitC operations do
not support multiple results. The `emitc.func` op features a
`specifiers` argument that for example allows, with corresponding
support in the emitter, to emit `inline static` functions.
Furthermore, this adds patterns and a pass to convert the Func dialect
to EmitC. A `func.func` op that is `private` is converted to
`emitc.func` with a `"static"` specifier.
Commit: d0dbd50cf0dc85834842380235f445e80516cb59
https://github.com/llvm/llvm-project/commit/d0dbd50cf0dc85834842380235f445e80516cb59
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Add missing header for 7ec996d4c5c30083b070be4898140440094e6b97
Commit: 468b23935a56d2be75c1f86fea97e5620b230a93
https://github.com/llvm/llvm-project/commit/468b23935a56d2be75c1f86fea97e5620b230a93
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Merge TableGenGlobalISel into the tablegen target
These two are intertwined enough so it doesn't really make sense to have
it standalone and hack around it by putting headers into both.
Commit: 395c8175e37248c11ddbffe47294033834b0ec51
https://github.com/llvm/llvm-project/commit/395c8175e37248c11ddbffe47294033834b0ec51
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Put back the pieces of TableGenGlobalISel that unittests depend on
This is a mess and needs to be cleaned up some day.
Commit: 415bf200a725055a3a38e96269f4b752ea6fc330
https://github.com/llvm/llvm-project/commit/415bf200a725055a3a38e96269f4b752ea6fc330
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/lib/ResultAggregator.cpp
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
M llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
M llvm/unittests/tools/llvm-exegesis/ResultAggregatorTest.cpp
M llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp
Log Message:
-----------
[llvm-exegesis] Replace --num-repetitions with --min-instructions (#77153)
This patch replaces --num-repetitions with --min-instructions to make it
more clear that the value refers to the minimum number of instructions
in the final assembled snippet rather than the number of repetitions of
the snippet. This patch also refactors some llvm-exegesis internal
variable names to reflect the name change.
Fixes #76890.
Commit: ca7fd25492388003fab4e19d7e95517bdee2d210
https://github.com/llvm/llvm-project/commit/ca7fd25492388003fab4e19d7e95517bdee2d210
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Fix a typo from e7d40a87ff230528131541f6ac17a2e1a7dc78e1
Commit: e9e01675a31969d5ae7c250caa6efcc8dcdb80bc
https://github.com/llvm/llvm-project/commit/e9e01675a31969d5ae7c250caa6efcc8dcdb80bc
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/HLFIR/invalid.fir
M flang/test/Lower/HLFIR/minval.f90
Log Message:
-----------
[flang][HLFIR] Relax verifiers of intrinsic operations (#80132)
The verifiers are currently very strict: requiring intrinsic operations
to be used only in cases where the Fortran standard permits the
intrinsic to be used.
There have now been a lot of cases where these verifiers have caused
bugs in corner cases. In a recent ticket, @jeanPerier pointed out that
it could be useful for future optimizations if somewhat invalid uses of
these operations could be allowed in dead code. See this comment:
https://github.com/llvm/llvm-project/issues/79995#issuecomment-1918118234
In response to all of this, I have decided to relax the intrinsic
operation verifiers. The intention is now to only disallow operation
uses that are likely to crash the compiler. Other checks are still
available under `-strict-intrinsic-verifier`.
The disadvantage of this approach is that IR can now represent intrinsic
invocations which are incorrect. The lowering and implementation of
these intrinsic functions is unlikely to do the right thing in all of
these cases, and as they should mostly be impossible to generate using
normal Fortran code, these edge cases will see very little testing,
before some new optimization causes them to become more common.
Fixes #79995
Commit: 1bbb797e9c7f37aa814b9bbaba2961f730a26891
https://github.com/llvm/llvm-project/commit/1bbb797e9c7f37aa814b9bbaba2961f730a26891
Author: Lucas Duarte Prates <lucas.prates at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/aarch64-target-features.c
Log Message:
-----------
[Clang][AArch64] Add ACLE macros for FEAT_PAuth_LR (#80163)
This updates clang's target defines to include the ACLE changes covering
the FEAT_PAuth_LR architecture extension.
The changes include:
* The new `__ARM_FEATURE_PAUTH_LR` feature macro, which is set to 1 when
FEAT_PAuth_LR is available in the target.
* A new bit field for the existing `__ARM_FEATURE_PAC_DEFAULT` macro,
indicating the use of PC as a diversifier for Pointer Authentication
(from -mbranch-protection=pac-ret+pc).
The approved changes to the ACLE spec can be found here:
https://github.com/ARM-software/acle/pull/292
Commit: f34418c73b718abb24cd5b921b5a2846011e7d0c
https://github.com/llvm/llvm-project/commit/f34418c73b718abb24cd5b921b5a2846011e7d0c
Author: Orlando Cazalet-Hyams <orlando.hyams at sony.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/IR/DebugInfoMetadata.cpp
Log Message:
-----------
[HWASAN] Remove DW_OP_LLVM_tag_offset from DIExpression::isImplicit (#79816)
According to its doc-comment `isImplicit` is meant to return true if the
expression is an implicit location description (describes an object or part of
an object which has no location by computing the value from available program
state).
There's a brief entry for `DW_OP_LLVM_tag_offset` in the LangRef and there's
some info in the original commit fb9ce100d19be130d004d03088ccd4af295f3435.
>From what I can tell it doesn't look like `DW_OP_LLVM_tag_offset` affects
whether or not the location is implicit; the opcode doesn't get included in the
final location description but instead is added as an attribute to the variable.
This was tripping an assertion in the latest application of the fix to #76545,
#78606, where an expression containing a `DW_OP_LLVM_tag_offset` is split into
a fragment (i.e., describe a part of the whole variable).
Commit: 96a3d05ed923d2abd51acb52984b83b9e8044924
https://github.com/llvm/llvm-project/commit/96a3d05ed923d2abd51acb52984b83b9e8044924
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
[GitHub][workflows] Reflow some text in buildbot info PR comment
When the markdown link renders the line gets a lot shorter.
Commit: b5c0b67bc270936c8fa254dc42d920e867adef54
https://github.com/llvm/llvm-project/commit/b5c0b67bc270936c8fa254dc42d920e867adef54
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64.cl
Log Message:
-----------
[AMDGPU] Check wavefrontsize for GFX11 WMMA builtins (#79980)
Commit: da437330beca0411912ca46f2d5ef1e46403acbd
https://github.com/llvm/llvm-project/commit/da437330beca0411912ca46f2d5ef1e46403acbd
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/IndVarSimplify/iv-poison.ll
Log Message:
-----------
[SCEVExp] Keep NUW/NSW if both original inc and isomporphic inc agree. (#79512)
We are replacing with a wider increment. If both OrigInc and
IsomorphicInc are NUW/NSW, then we can preserve them on the wider
increment; the narrower IsomorphicInc would wrap before the wider
OrigInc, so the replacement won't make IsomorphicInc's uses more
poisonous.
PR: https://github.com/llvm/llvm-project/pull/79512
Commit: 7d78ccf7d5a9861839126d5899b443f55236cab9
https://github.com/llvm/llvm-project/commit/7d78ccf7d5a9861839126d5899b443f55236cab9
Author: Hristo Hristov <hghristov.rmm at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/__memory/allocate_at_least.h
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/memory
M libcxx/include/version
M libcxx/modules/std/memory.inc
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
R libcxx/test/std/utilities/memory/allocator.traits/allocate_at_least.pass.cpp
A libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_at_least.pass.cpp
M libcxx/utils/generate_feature_test_macro_components.py
Log Message:
-----------
[libc++][memory] P2652R2: Disallow Specialization of `allocator_traits` (#79978)
Implements P2652R2 <https://wg21.link/P2652R2>:
- https://eel.is/c++draft/allocator.requirements.general
- https://eel.is/c++draft/memory.syn
- https://eel.is/c++draft/allocator.traits.general
- https://eel.is/c++draft/allocator.traits.members
- https://eel.is/c++draft/diff.cpp20.concepts
- https://eel.is/c++draft/diff.cpp20.utilities
---------
Co-authored-by: Zingam <zingam at outlook.com>
Commit: ea2984287d91b96f5e2cc0aa66d146d6dbd1d1bb
https://github.com/llvm/llvm-project/commit/ea2984287d91b96f5e2cc0aa66d146d6dbd1d1bb
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/CodeGen/ARM/popcnt.ll
Log Message:
-----------
[ARM] Add ctpop codegen tests
Commit: c105848fd29d3b46eeb794bb6b10dad04f903b09
https://github.com/llvm/llvm-project/commit/c105848fd29d3b46eeb794bb6b10dad04f903b09
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[IndVars] Add tests for #79861 (NFC)
Commit: 178719e86043c1e830a7e24de027a84f6f8ea28f
https://github.com/llvm/llvm-project/commit/178719e86043c1e830a7e24de027a84f6f8ea28f
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/tail-calls.ll
Log Message:
-----------
[RISCV][NFC] Simplify calls.ll and autogenerate checks for tail-calls.ll
Split out from #78417.
Reviewers: topperc, asb, kito-cheng
Reviewed By: asb
Pull Request: https://github.com/llvm/llvm-project/pull/79248
Commit: d2565bb11308f6cf98d838e828d9bcbe2d51e0e4
https://github.com/llvm/llvm-project/commit/d2565bb11308f6cf98d838e828d9bcbe2d51e0e4
Author: Alexandre Ganea <37383324+aganea at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/cmake/HandleOpenMPOptions.cmake
Log Message:
-----------
[openmp] On Windows, fix standalone cmake build (#80174)
This fixes: https://github.com/llvm/llvm-project/issues/80117
Commit: f956e7fbf161447b9236f7c4448a9d02d3564261
https://github.com/llvm/llvm-project/commit/f956e7fbf161447b9236f7c4448a9d02d3564261
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
Log Message:
-----------
[AMDGPU] Prefer `s_memtime` for `readcyclecounter` on GFX10 (#80211)
Summary:
The old `s_memtime` instruction was supported until the GFX10
architecture. Although this instruction has a higher latency than the
new shader counter, it's much more usable as a processor clock as it is
a full 64-bit counter. The new shader counter is only a 20-bit counter,
which makes it difficult to use as a standard cycle counter as it will
overflow in a few milliseconds. This patch suggests preferring
`s_memtime` for this instrinsic if it is still available.
Commit: d313614b60ff1194f48e5f0b1bb8d63d2b7eb52d
https://github.com/llvm/llvm-project/commit/d313614b60ff1194f48e5f0b1bb8d63d2b7eb52d
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
M clang/test/Modules/aarch64-sme-keywords.cppm
M llvm/docs/AArch64SME.rst
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
M llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call-remarks.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
M llvm/test/CodeGen/AArch64/sme-new-za-function.ll
M llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
M llvm/test/Transforms/Inline/AArch64/sme-pstateza-attrs.ll
M llvm/test/Verifier/sme-attributes.ll
M llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
M mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Dialect/ArmSME/enable-arm-za.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[AArch64] Replace LLVM IR function attributes for PSTATE.ZA. (#79166)
Since https://github.com/ARM-software/acle/pull/276 the ACLE
defines attributes to better describe the use of a given SME state.
Previously the attributes merely described the possibility of it being
'shared' or 'preserved', whereas the new attributes have more semantics
and also describe how the data flows through the program.
For ZT0 we already had to add new LLVM IR attributes:
* aarch64_new_zt0
* aarch64_in_zt0
* aarch64_out_zt0
* aarch64_inout_zt0
* aarch64_preserves_zt0
We have now done the same for ZA, such that we add:
* aarch64_new_za (previously `aarch64_pstate_za_new`)
* aarch64_in_za (more specific variation of `aarch64_pstate_za_shared`)
* aarch64_out_za (more specific variation of `aarch64_pstate_za_shared`)
* aarch64_inout_za (more specific variation of
`aarch64_pstate_za_shared`)
* aarch64_preserves_za (previously `aarch64_pstate_za_shared,
aarch64_pstate_za_preserved`)
This explicitly removes 'pstate' from the name, because with SME2 and
the new ACLE attributes there is a difference between "sharing ZA"
(sharing
the ZA matrix register with the caller) and "sharing PSTATE.ZA" (sharing
either the ZA or ZT0 register, both part of PSTATE.ZA with the caller).
Commit: 5d41788f3798da5ea91dc6cac86e3d9eebdee3ce
https://github.com/llvm/llvm-project/commit/5d41788f3798da5ea91dc6cac86e3d9eebdee3ce
Author: David Green <david.green at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/test/CodeGen/AArch64/select_fmf.ll
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
Log Message:
-----------
[AArch64] Alter latency of FCSEL under Cortex-A510 (#80178)
As per the Cortex-A510 software optimization guide, the latency of a
fcsel should be 3 not 4. It would previously get the latency from
WriteF.
Commit: c3eb2978a60b4e2e0cf9c8a8f9c51b48bd49477a
https://github.com/llvm/llvm-project/commit/c3eb2978a60b4e2e0cf9c8a8f9c51b48bd49477a
Author: Hsiangkai Wang <hsiangkai.wang at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
Log Message:
-----------
[mlir][scf] Considering defining operators of indices when fusing scf::ParallelOp (#80145)
When checking the load indices of the second loop coincide with the
store indices of the first loop, it only considers the index values are
the same or not. However, there are some cases the index values defined
by other operators. In these cases, it will treat them as different even
the results of defining operators are the same.
We already check if the iteration space is the same in isFusionLegal().
When checking operands of defining operators, we only need to consider
the operands come from the same induction variables. If so, we know the
results of defining operators are the same.
Commit: 112fba974ce42a6e552f7391d20a858a128283a1
https://github.com/llvm/llvm-project/commit/112fba974ce42a6e552f7391d20a858a128283a1
Author: Quentin Dian <dianqk at dianqk.net>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/ARM/cmpxchg.mir
M llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
M llvm/test/CodeGen/MIR/X86/unreachable-block-print.mir
M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
M llvm/test/CodeGen/PowerPC/branch_coalescing.mir
M llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
M llvm/test/CodeGen/PowerPC/nofpexcept.ll
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir
M llvm/test/CodeGen/RISCV/float-select-verify.ll
M llvm/test/CodeGen/Thumb2/cmpxchg.mir
M llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
M llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir
M llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
M llvm/test/CodeGen/X86/cse-two-preds.mir
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
Log Message:
-----------
[MIRPrinter] Don't print line break when there is no instructions (NFC) (#80147)
Per #80143, we can remove the extra line break when there is no
instruction.
Commit: 15295d01352c922f1dfe564d801d556cf5fe01b3
https://github.com/llvm/llvm-project/commit/15295d01352c922f1dfe564d801d556cf5fe01b3
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Introduce and use computeCommonAlignment function, NFC.
Commit: 2a50921553798d2db52ca6330c89f0f8a5bc2215
https://github.com/llvm/llvm-project/commit/2a50921553798d2db52ca6330c89f0f8a5bc2215
Author: Amy Kwan <amy.kwan1 at ibm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-char.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-double.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-float.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-int.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll
A llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-short.ll
Log Message:
-----------
[AIX][TLS] Optimize the small local-exec access sequence for non-zero offsets (#71485)
This patch utilizes the -maix-small-local-exec-tls option to produce a
faster,
non-TOC-based access sequence for the local-exec TLS model.
Specifically, for
when the offsets from the TLS variable are non-zero.
In particular, this patch produces either a single:
- addi/la with a displacement off of R13 plus a non-zero offset for when
an address is calculated, or
- load or store off of R13 plus a non-zero offset for when an address is
calculated and used for further
access where R13 is the thread pointer, respectively.
In order to produce a single addi or load/store off of the thread
pointer with a non-zero offset,
this patch also adds the necessary support in the assembly printer when
printing these instructions.
Specifically:
- The non-zero offset is added to the TLS variable address when the
address of the
TLS variable + it's offset is less than 32KB.
- Otherwise, when the address of the TLS variable + its offset is
greater than 32KB, the
non-zero offset (and a multiple of 64KB) is subtracted from the TLS
address.
This handling in the assembly printer is necessary to ensure that the
TLS address + the non-zero offset
is between [-32768, 32768), so that the total displacement can fit
within the addi/load/store instructions.
This patch is meant to be a follow-up to
3f46e5453d9310b15d974e876f6132e3cf50c4b1 (where the
optimization occurs for when the offset is zero).
Commit: 40f6b7d4761657cebd383b102ff3e6e612337f01
https://github.com/llvm/llvm-project/commit/40f6b7d4761657cebd383b102ff3e6e612337f01
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
Log Message:
-----------
[PowerPC] Fix -Wunused-variable in PPCAsmPrinter.cpp and PPCISelDAGToDAG.cpp (NFC)
llvm-project/llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp:1648:15:
error: unused variable 'InstDisp' [-Werror,-Wunused-variable]
ptrdiff_t InstDisp = TLSVarAddress + Offset - Delta;
^
llvm-project/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:7624:19:
error: unused variable 'TPReg' [-Werror,-Wunused-variable]
RegisterSDNode *TPReg = dyn_cast<RegisterSDNode>(TPRegNode.getNode());
^
llvm-project/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp:7625:23:
error: unused variable 'Subtarget' [-Werror,-Wunused-variable]
const PPCSubtarget &Subtarget =
^
Commit: f7b05e055fa63e1c4b5ae5e391b654b57161a0e4
https://github.com/llvm/llvm-project/commit/f7b05e055fa63e1c4b5ae5e391b654b57161a0e4
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/Transforms/LoopUnroll/runtime-i128.ll
Log Message:
-----------
[LoopUnroll] Add test for #80289 (NFC)
Commit: 62ae7d976f494f3dbd297331b19cd1204750de6f
https://github.com/llvm/llvm-project/commit/62ae7d976f494f3dbd297331b19cd1204750de6f
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/test/Transforms/LoopUnroll/runtime-i128.ll
Log Message:
-----------
[LoopUnroll] Fix missing sign extension
For integers larger than 64-bit, this would zero-extend a -1
value, instead of sign-extending it.
Fixes https://github.com/llvm/llvm-project/issues/80289.
Commit: 3c64b24ed35fe6bb4a7a1fe304089e6069fcd14d
https://github.com/llvm/llvm-project/commit/3c64b24ed35fe6bb4a7a1fe304089e6069fcd14d
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/include/bolt/Core/BinaryContext.h
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Profile/StaleProfileMatching.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
Log Message:
-----------
[BOLT] Add extra staleness logging (#80225)
Report two extra metrics:
- # of stale functions with matching block count,
- # of stale blocks with matching instruction count.
Commit: fcd3752342ebd193d4eef39b9c0730599eca4486
https://github.com/llvm/llvm-project/commit/fcd3752342ebd193d4eef39b9c0730599eca4486
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/test/Driver/rocm-detect.hip
Log Message:
-----------
[HIP] fix HIP detection for /usr (#80190)
Skip checking HIP version file under parent directory for /usr/local
since /usr will be checked after /usr/local.
Fixes: https://github.com/llvm/llvm-project/issues/78344
Commit: 6050cf28846e5be2c162108f1a024d5ff25d5637
https://github.com/llvm/llvm-project/commit/6050cf28846e5be2c162108f1a024d5ff25d5637
Author: Ivan Butygin <ivan.butygin at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
Log Message:
-----------
[mlir][scf] Add reductions support to `scf.parallel` fusion (#75955)
Properly handle fusion of loops with reductions:
* Check there are no first loop results users between loops
* Create new loop op with merged reduction init values
* Update `scf.reduce` op to contain reductions from both loops
* Update loops users with new loop results
Commit: 390d66b03b5a5e352b7d696aaed679a2deb25c6c
https://github.com/llvm/llvm-project/commit/390d66b03b5a5e352b7d696aaed679a2deb25c6c
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Log Message:
-----------
[LSR] Add tests for restricting term-fold budget based on exact trip count
Commit: 6ac4fe8de014336ce66d02ddd07e85db3b8e77a2
https://github.com/llvm/llvm-project/commit/6ac4fe8de014336ce66d02ddd07e85db3b8e77a2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] X86FixupVectorConstants.cpp - refactor constant search loop to take array of sorted candidates
Pulled out of #79815 - refactors the internal FixupConstant logic to just accept an array of vzload/broadcast candidates that are pre-sorted in ascending constant pool size
Commit: 9acd61ec1999ac3a54371d0a8b9d922ef5ca2b50
https://github.com/llvm/llvm-project/commit/9acd61ec1999ac3a54371d0a8b9d922ef5ca2b50
Author: Ilya Biryukov <ibiryukov at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/AST/ASTContext.cpp
M clang/test/SemaCXX/datasizeof.cpp
Log Message:
-----------
[Sema] Fix crash in __datasizeof with unknown types (#80300)
Fixes #80284.
Calling `getASTRecordLayout` on invalid types may crash and results of
`__datasizeof` on invalid types can be arbitrary, so just use whatever
`sizeof` returns.
Commit: c5f461918cece4362fb70c7b16de4e95c1af8e5f
https://github.com/llvm/llvm-project/commit/c5f461918cece4362fb70c7b16de4e95c1af8e5f
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Parse/Parser.cpp
M clang/test/CXX/temp/p3.cpp
M clang/test/OpenMP/declare_simd_messages.cpp
Log Message:
-----------
[Clang][Parse] Diagnose member template declarations with multiple declarators (#78243)
According to [temp.pre] p5:
> In a template-declaration, explicit specialization, or explicit instantiation the init-declarator-list in the declaration shall contain at most one declarator.
A member-declaration that is a template-declaration or explicit-specialization contains a declaration, even though it declares a member. This means it _will_ contain an init-declarator-list (not a member-declarator-list), so [temp.pre] p5 applies.
This diagnoses declarations such as:
```
struct A
{
template<typename T>
static const int x = 0, f(); // error: a template declaration can only declare a single entity
template<typename T>
static const int g(), y = 0; // error: a template declaration can only declare a single entity
};
```
The diagnostic messages are the same as those of the equivalent namespace scope declarations.
Note: since we currently do not diagnose declarations with multiple abbreviated function template declarators at namespace scope e.g., `void f(auto), g(auto);`, so this patch does not add diagnostics for the equivalent member declarations.
This patch also refactors `ParseSingleDeclarationAfterTemplate` (now named `ParseDeclarationAfterTemplate`) to call `ParseDeclGroup` and return the resultant `DeclGroup`.
Commit: a52eea66795018550e95c4b060165a7250899298
https://github.com/llvm/llvm-project/commit/a52eea66795018550e95c4b060165a7250899298
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aarch64-targetattr.c
M clang/test/Preprocessor/aarch64-target-features.c
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64] Make +pauth enabled in Armv8.3-a by default (#78027)
Add AEK_PAUTH to ARMV8_3A in TargetParser and let it propagate to
ARMV8R, as it aligns with GCC defaults.
After adding AEK_PAUTH, several tests from TargetParserTest.cpp crashed
when trying to format an error message, thus update a format string in
AssertSameExtensionFlags to account for bitmask being pre-formatted as
std::string.
The CHECK-PAUTH* lines in aarch64-target-features.c are updated to
account for the fact that FEAT_PAUTH support and pac-ret can be enabled
independently and all four combinations are possible.
Commit: bed3608c22fbd3afbdbc782f04e8c9c6e6e8fa18
https://github.com/llvm/llvm-project/commit/bed3608c22fbd3afbdbc782f04e8c9c6e6e8fa18
Author: Amir Ayupov <aaupov at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Rewrite/RewriteInstance.cpp
Log Message:
-----------
[BOLT][NFC] Factor out RI::disassemblePLTInstruction (#80302)
Commit: 4eb0810922a8d6ad9a32fbf09326166317dc5c08
https://github.com/llvm/llvm-project/commit/4eb0810922a8d6ad9a32fbf09326166317dc5c08
Author: Emma Pilkington <emma.pilkington95 at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/tools/llvm-objdump/llvm-objdump.cpp
Log Message:
-----------
[llvm-objdump][AMDGPU] Pass ELF ABIVersion through disassembler (#78907)
Admittedly, its a bit ugly to pass the ABIVersion through onSymbolStart
but I'm not sure what a better place for it would be.
Commit: 09b4649ea5cefc4f93d9c936d38863df5c6568ed
https://github.com/llvm/llvm-project/commit/09b4649ea5cefc4f93d9c936d38863df5c6568ed
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertCall.cpp
M flang/test/Lower/HLFIR/procedure-pointer.f90
Log Message:
-----------
[flang] Fix passing NULL to OPTIONAL procedure pointers (#80267)
Procedure pointer lowering used `prepareUserCallActualArgument` because
it was convenient, but this helper was not meant for POINTERs when
originally written and it did not handled passing NULL to an OPTIONAL
procedure pointer correctly.
The resulting argument should be a disassociated pointer, not an absent
pointer (Fortran 15.5.2.12 point 1.).
Move the logic for procedure pointer argument "cooking" in its own
helper to avoid triggering the logic that created an absent argument in
this case.
Commit: bfdd78233fba4623366bbef5631ff0ebab29c42e
https://github.com/llvm/llvm-project/commit/bfdd78233fba4623366bbef5631ff0ebab29c42e
Author: Kevin Frei <kevinfrei at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DIContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/test/DebugInfo/X86/skeleton-unit-verify.s
M llvm/test/DebugInfo/dwarfdump-accel.test
M llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes_no_files.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_file_encoding.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_overlapping_cu_ranges.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_parent_zero_length.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_split_cu.s
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
Log Message:
-----------
Aggregate errors from llvm-dwarfdump --verify (#79648)
The amount and format of output from `llvm-dwarfdump --verify` makes it
quite difficult to know if a change to a tool that produces or modifies
DWARF is causing new problems, or is fixing existing problems. This diff
adds a categorized summary of issues found by the DWARF verifier, on by
default, at the bottom of the error output.
The change includes a new `--error-display` option with 4 settings:
* `--error-display=quiet`: Only display if errors occurred, but no
details or summary are printed.
* `--error-display=summary`: Only display the aggregated summary of
errors with no error detail.
* `--error-display=details`: Only display the detailed error messages
with no summary (previous behavior)
* `--error-display=full`: Display both the detailed error messages and
the aggregated summary of errors (the default)
I changed a handful of tests that were failing due to new output, adding
the flag to use the old behavior for all but a couple. For those two I
added the new aggregated output to the expected output of the test.
The `OutputCategoryAggregator` is a pretty simple little class that
@clayborg suggested to allow code to only be run to dump detail if it's
enabled, while still collating counts of the category. Knowing that the
lambda passed in is only conditionally executed is pretty important
(handling errors has to be done *outside* the lambda). I'm happy to move
this somewhere else (and change/improve it) to be more broadly useful if
folks would like.
---------
Co-authored-by: Kevin Frei <freik at meta.com>
Commit: 4739a97faedf766541245e6a5b48595d4a3deaae
https://github.com/llvm/llvm-project/commit/4739a97faedf766541245e6a5b48595d4a3deaae
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
Log Message:
-----------
[Clang][NFC] Remove TemplateArgumentList::OnStack (#79760)
This patch removes on-stack `TemplateArgumentList`'s. They were primary used
to pass an `ArrayRef<TemplateArgument>` to
`Sema::getTemplateInstantiationArgs`, which had a `const
TemplateArgumentList*` parameter for the innermost template argument
list. Changing this parameter to an
`std::optional<ArrayRef<TemplateArgument>>` eliminates the need for
on-stack `TemplateArgumentList`'s, which in turn eliminates the need for
`TemplateArgumentList` to store a pointer to its template argument
storage (which is redundant in almost all cases, as it is an AST
allocated type).
Commit: 548d132b9457aa5223ee87d2306a7bec30da93d2
https://github.com/llvm/llvm-project/commit/548d132b9457aa5223ee87d2306a7bec30da93d2
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/cmake/modules/LLVMLibCLibraryRules.cmake
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
Log Message:
-----------
[libc][NFC] Refactor FLAGS expansion using cmake_language(CALL ...). (#80156)
Commit: 46068f5e8d318c67d0b9088ed751e09473776a0d
https://github.com/llvm/llvm-project/commit/46068f5e8d318c67d0b9088ed751e09473776a0d
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
Log Message:
-----------
[NFC] Reorder test lines in arith-fp-frem.ll (#79991)
Run lines appear in a more natural order:
- no veclib (neon, sve)
- neon + veclib
- sve + veclib
- sve + tailfold + veclib
Commit: 7b9bf80ab51b9b09d9f07fb636f4b64581a3c3e0
https://github.com/llvm/llvm-project/commit/7b9bf80ab51b9b09d9f07fb636f4b64581a3c3e0
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
Log Message:
-----------
[SLP][NFC]Add tests with strided loads, NFC.
Commit: 7e7f118404cdfbee9eaf7c05ab8ea54a25b52aa4
https://github.com/llvm/llvm-project/commit/7e7f118404cdfbee9eaf7c05ab8ea54a25b52aa4
Author: XDeme <tagawafernando at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] Handles Elaborated type specifier for enum in trailing return (#80085)
Fixes llvm/llvm-project#80062
Commit: e0e6236fd61f906f8529dcaa8ecd0beec1f5a18a
https://github.com/llvm/llvm-project/commit/e0e6236fd61f906f8529dcaa8ecd0beec1f5a18a
Author: jeffreytan81 <jeffreytan at meta.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
A lldb/test/API/commands/target/debuginfo/TestDebugInfoSize.py
A lldb/test/API/commands/target/debuginfo/a.out-foo.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out-main.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out.yaml
Log Message:
-----------
Fix debug info size statistics for split dwarf (#80218)
`statistics dump` command relies on `SymbolFile::GetDebugInfoSize()` to
get total debug info size.
The current implementation is missing debug info for split dwarf
scenarios which requires getting debug info from separate dwo/dwp files.
This patch fixes this issue for split dwarf by parsing debug info from
dwp/dwo.
New yaml tests are added.
---------
Co-authored-by: jeffreytan81 <jeffreytan at fb.com>
Commit: 28699e385681e7f0aeefc208b7b59d6f1d484800
https://github.com/llvm/llvm-project/commit/28699e385681e7f0aeefc208b7b59d6f1d484800
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/include/errno.h.def
M libc/src/errno/CMakeLists.txt
M libc/src/errno/libc_errno.cpp
M libc/src/errno/libc_errno.h
M libc/test/integration/startup/linux/tls_test.cpp
M libc/test/src/errno/errno_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/sys/mman/linux/madvise_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mmap_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
Log Message:
-----------
[libc] Update libc_errno to work correctly in both overlay and full build modes. (#80177)
Commit: 1f3c30911cc5eee4b42bdc9c6358c689b2f2f223
https://github.com/llvm/llvm-project/commit/1f3c30911cc5eee4b42bdc9c6358c689b2f2f223
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
Log Message:
-----------
[AMDGPU] Mark PC_ADD_REL_OFFSET rematerializable (#79674)
Currently machine LICM hoist PC_ADD_REL_OFFSET out of loops, causes
register pressure when function calls are deep in loops. This is a main
cause of sgpr spill for programs containing large number of function
calls in loops.
This patch marks PC_ADD_REL_OFFSET as rematerializable, which eliminates
sgpr spills due to function calls in loops.
Commit: 94166c6ea1574372521f54d72522b81cc85cdbb6
https://github.com/llvm/llvm-project/commit/94166c6ea1574372521f54d72522b81cc85cdbb6
Author: lntue <35648136+lntue at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/integration/startup/linux/tls_test.cpp
Log Message:
-----------
[libc] Fix wrong errno number in tls_test. (#80312)
Commit: 87e04b471e8c52991c4100a270d4b59a84b7c48d
https://github.com/llvm/llvm-project/commit/87e04b471e8c52991c4100a270d4b59a84b7c48d
Author: Matin Raayai <30674652+matinraayai at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
Log Message:
-----------
Fix Passing TargetOptions by Value in TargetMachines for AMDGPU (#79866)
`TargetOptions` is currently passed by value in AMDGPU targets, which
makes unnecessary copies. This PR fixes this issue.
Commit: de1ea787ed70ff376a1ff3b4262d0e25e4d135f2
https://github.com/llvm/llvm-project/commit/de1ea787ed70ff376a1ff3b4262d0e25e4d135f2
Author: Mike Rice <michael.p.rice at intel.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Sema/SemaExpr.cpp
M clang/test/SemaCXX/decomposition-openmp.cpp
Log Message:
-----------
[OpenMP] Move unsupported structured bindings diagnostic (#80216)
Move the diagnostic so it fires only when doing an OpenMP capture, not
for non-OpenMP captures. This allows non-OpenMP code to work when using
OpenMP elsewhere, such as the code reported in
https://github.com/llvm/llvm-project/issues/66999.
Commit: ecb5a1b0e236a98f59863793b4cfef1f13ea225c
https://github.com/llvm/llvm-project/commit/ecb5a1b0e236a98f59863793b4cfef1f13ea225c
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libcxx/include/CMakeLists.txt
R libcxx/include/experimental/__memory
M libcxx/include/module.modulemap.in
Log Message:
-----------
[libc++][NFC] Remove <experimental/__memory> (#80194)
The header is unused now, so we can remove it.
Commit: 6a3fde6d600cccd2ffbede6dd54519036cc4089c
https://github.com/llvm/llvm-project/commit/6a3fde6d600cccd2ffbede6dd54519036cc4089c
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/stdbit.rst
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/CMakeLists.txt
A libc/src/stdbit/stdc_leading_ones_uc.cpp
A libc/src/stdbit/stdc_leading_ones_uc.h
A libc/src/stdbit/stdc_leading_ones_ui.cpp
A libc/src/stdbit/stdc_leading_ones_ui.h
A libc/src/stdbit/stdc_leading_ones_ul.cpp
A libc/src/stdbit/stdc_leading_ones_ul.h
A libc/src/stdbit/stdc_leading_ones_ull.cpp
A libc/src/stdbit/stdc_leading_ones_ull.h
A libc/src/stdbit/stdc_leading_ones_us.cpp
A libc/src/stdbit/stdc_leading_ones_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/CMakeLists.txt
A libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
Log Message:
-----------
[libc] implement stdc_leading_ones (C23) (#80082)
Commit: 10a55caccf4e2d397f94c1455b93d774591be45f
https://github.com/llvm/llvm-project/commit/10a55caccf4e2d397f94c1455b93d774591be45f
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv-inline-asm.c
M clang/test/Sema/inline-asm-validate-riscv.c
M llvm/docs/LangRef.rst
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
R llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
A llvm/test/CodeGen/RISCV/inline-asm-s-constraint-error.ll
A llvm/test/CodeGen/RISCV/inline-asm-s-constraint.ll
Log Message:
-----------
[RISCV] Support constraint "s" (#80201)
GCC has supported a generic constraint "s" for a long time (since at
least 1992), which references a symbol or label with an optional
constant offset. "i" is a superset that also supports a constant
integer.
GCC's RISC-V port also supports a machine-specific constraint "S",
which cannot be used with a preemptible symbol. (We don't bother to
check preemptibility.) In PIC code, an external symbol is preemptible by
default, making "S" less useful if you want to create an artificial
reference for linker garbage collection, or define sections to hold
symbol addresses:
```
void fun();
// error: impossible constraint in ‘asm’ for riscv64-linux-gnu-gcc -fpie/-fpic
void foo() { asm(".reloc ., BFD_RELOC_NONE, %0" :: "S"(fun)); }
// good even if -fpie/-fpic
void foo() { asm(".reloc ., BFD_RELOC_NONE, %0" :: "s"(fun)); }
```
This patch adds support for "s". Modify https://reviews.llvm.org/D105254
("S") to handle multi-depth GEPs (https://reviews.llvm.org/D61560).
Commit: f0c8d88e25dbed02605994da227dfa75c1304d4a
https://github.com/llvm/llvm-project/commit/f0c8d88e25dbed02605994da227dfa75c1304d4a
Author: alx32 <103613512+alx32 at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/MachO/ObjC.cpp
M lld/test/MachO/objc-category-conflicts.s
Log Message:
-----------
[lld-macho] Make ObjC category checker print the source file name of category (#80221)
When printing category conflicts in the ObjC category checker, also
print the source file name of the problematic categories. Currently we
only print the object file name. This change is mostly useful only for
thinLTO builds, where the object file name will be of form
999.arm64.lto.o and thus does not reveal any information about the
original source file.
---------
Co-authored-by: Alex Borcan <alexborcan at meta.com>
Commit: cc0c8e592f8ff58ab821a04b7dcfb71403b4bea6
https://github.com/llvm/llvm-project/commit/cc0c8e592f8ff58ab821a04b7dcfb71403b4bea6
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp
Log Message:
-----------
[OpenMP] Fix build breakage (NFC) (#80313)
Assign `nullptr` to the pointer instead.
Commit: 58b87300ecaac71e237cefec80d3934610f55fbd
https://github.com/llvm/llvm-project/commit/58b87300ecaac71e237cefec80d3934610f55fbd
Author: Marius Brehler <marius.brehler at iml.fraunhofer.de>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Conversion/SCFToEmitC/SCFToEmitC.h
Log Message:
-----------
[mlir][EmitC] Harmonize include guard (NFC)
Harmonizes the include guard as it is rather uncommon within the MLIR
subproject to append an underscore to include guards.
Commit: ef7f6aca149c88089ec4964e87889f3709321f03
https://github.com/llvm/llvm-project/commit/ef7f6aca149c88089ec4964e87889f3709321f03
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Log Message:
-----------
[SLP][NFC]Add some extra checks/reorganize the code to improve compile time, NFC.
Commit: e296cedcd686e24fee75756185669f1bb3b47fdd
https://github.com/llvm/llvm-project/commit/e296cedcd686e24fee75756185669f1bb3b47fdd
Author: Brendan Sweeney <brs at eecs.berkeley.edu>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/RISCV/rv32zalasr-invalid.s
A llvm/test/MC/RISCV/rv32zalasr-valid.s
A llvm/test/MC/RISCV/rv64zalasr-invalid.s
A llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] MC layer support for the experimental zalasr extension (#79911)
This PR implements experimental support for the RISC-V Atomic
Load-Acquire and Store-Release Extension (Zalasr). It has been approved
to be pursued as a fast track extension
(https://lists.riscv.org/g/tech-unprivileged/topic/arc_architecture_review/101951698),
but has not yet been approved by ARC or ratified. See
https://github.com/mehnadnerd/riscv-zalasr for draft spec.
---------
Co-authored-by: brs <turtwig at utexas.edu>
Co-authored-by: Philip Reames <preames at rivosinc.com>
Commit: 20a9fa3e145999d7cb0d311c832ee6c72fc276fb
https://github.com/llvm/llvm-project/commit/20a9fa3e145999d7cb0d311c832ee6c72fc276fb
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
Log Message:
-----------
[mlir][sparse] add sparsification options to pretty print and debug s… (#80205)
…parse loops.
Commit: 41be5412e2da0235811af24b10eb2dacab03f8b5
https://github.com/llvm/llvm-project/commit/41be5412e2da0235811af24b10eb2dacab03f8b5
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/test/MC/RISCV/supervisor-csr-names.s
Log Message:
-----------
[RISCV] Add srmcfg CSR from Ssqosid extension. (#79914)
Based on the spec here
https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1
Ssqosid extension name will be added in a separate patch.
Commit: 10c2d5ff7c6de8096c8f4c4621612970940f6dd3
https://github.com/llvm/llvm-project/commit/10c2d5ff7c6de8096c8f4c4621612970940f6dd3
Author: Jiahan Xie <88367305+jiahanxie353 at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
Log Message:
-----------
[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)
RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.
Commit: f883365cc7600cf1c29b36343f2f8cdbe3394881
https://github.com/llvm/llvm-project/commit/f883365cc7600cf1c29b36343f2f8cdbe3394881
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/include/stdbit_test.cpp
Log Message:
-----------
[libc] fix stdbit include test when not all entrypoints are available (#80323)
The intent of the test is to check that: 1. The type generic macros are
defined. 2. Those macros dispatch to the correct underlying function.
The issue is that when new functionality is added to our stdbit.h without
rolling out the new entrypoint to all targets, this test breaks because our
generated stdbit.h will not contain declarations for the underlying function.
In that case, we should just declare the underlying functions first before
including our generated stdbit.h which just contains declarations. A definition
is a declaration, but redeclarations must match, hence the additions of
noexcept and extern "C".
Commit: 116e801a15569386c452085de783ecb9223050ff
https://github.com/llvm/llvm-project/commit/116e801a15569386c452085de783ecb9223050ff
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
A bolt/test/X86/phdr-out-of-order.test
Log Message:
-----------
[BOLT] Adjust section sizes based on file offsets (#80226)
When we adjust section sizes while rewriting a binary, we should be
using section offsets and not addresses to determine if section overlap.
NFC for existing binaries.
Commit: a693ae5306d224228acbbc1366dc90432afce434
https://github.com/llvm/llvm-project/commit/a693ae5306d224228acbbc1366dc90432afce434
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/test/X86/linux-orc.s
Log Message:
-----------
[BOLT] Enable re-writing of Linux kernel binary (#80228)
Write modified Linux kernel binary to disk. The output is not supposed
to be functional at the moment, but it will allow for future patches to
test the output binary.
Commit: a063df20abeee3513d3577dc41bff7e54159efa5
https://github.com/llvm/llvm-project/commit/a063df20abeee3513d3577dc41bff7e54159efa5
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/CMakeLists.txt
Log Message:
-----------
[OpenMP] Fix typo (NFC) (#80332)
Commit: 6f32d6a4f362ad1c7f6328232a68f44a44fc2d2e
https://github.com/llvm/llvm-project/commit/6f32d6a4f362ad1c7f6328232a68f44a44fc2d2e
Author: Carlos Galvez <carlosgalvezp at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/prefer-member-initializer.rst
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init.cpp
Log Message:
-----------
[clang-tidy] Remove enforcement of rule C.48 from cppcoreguidelines-prefer-member-init (#80330)
This functionality already exists in
cppcoreguidelines-use-default-member-init. It was deprecated from this
check in clang-tidy 17.
This allows us to fully decouple this check from the corresponding
modernize check, which has an unhealthy dependency.
Fixes https://github.com/llvm/llvm-project/issues/62169
---------
Co-authored-by: Carlos Gálvez <carlos.galvez at zenseact.com>
Commit: 7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
https://github.com/llvm/llvm-project/commit/7a7d5481ad5c925d4f31bee3ab66bd1d7d514b73
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
Log Message:
-----------
[libc] add bazel support for most of unistd (#80078)
Much of unistd involves modifying files. The tests for these functions
need to use libc_make_test_file_path which didn't exist when they were
first implemented. This patch adds most of unistd to the bazel along
with the corresponding tests. Tests that modify directories had to be
disabled since bazel doesn't seem to handle them properly.
Commit: aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
https://github.com/llvm/llvm-project/commit/aaaff74fd1273d88d990ed5f93a714fc0a8ca4be
Author: Micah Weston <micahsweston at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/tools/llvm-readobj/ELFDumper.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP][llvm-readobj] Implements llvm-readobj handling for PGOAnalysisMap. (#79520)
Adds raw printing of PGOAnalysisMap in llvm-readobj.
I'm leaving the fixme's for a later patch that will provide a 'pretty'
printing for BBFreq and BrProb (i.e. relative frequencies and
probabilities) that will apply to both llvm-readobj and llvm-objdump.
Commit: 08fccf80949c649e2c4c81bf9149fd77206002c4
https://github.com/llvm/llvm-project/commit/08fccf80949c649e2c4c81bf9149fd77206002c4
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
Log Message:
-----------
[AArch64][PAC] Expand blend(reg, imm) operation in aarch64-pauth pass (#74729)
In preparation for implementing code generation for more @llvm.ptrauth.* intrinsics, move the expansion of blend(register, small integer) variant of @llvm.ptrauth.blend to the AArch64PointerAuth pass, where most other PAuth-related code generation takes place.
Commit: fe408eb5845737f8d6bf5eeed0aca8651991e687
https://github.com/llvm/llvm-project/commit/fe408eb5845737f8d6bf5eeed0aca8651991e687
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M flang/lib/Lower/DirectivesCommon.h
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
Log Message:
-----------
[flang][openacc][openmp] Use #0 from hlfir.declare value when generating bound ops (#80317)
`getDataOperandBaseAddr` retrieve the address of a value when we need to
generate bound operations. When switching to HLFIR, we did not really
handle the fact that this value was then pointing to the result of a
hlfir.declare. Because of that the `#1` value was being used. `#0` value
is carrying the correct information about lowerbounds and should be
used. This patch updates the `getDataOperandBaseAddr` function to use
the correct result value from hlfir.declare.
Commit: 243bfed68367263cfc3fb3f396660acf60051fbf
https://github.com/llvm/llvm-project/commit/243bfed68367263cfc3fb3f396660acf60051fbf
Author: Artem Dergachev <adergachev at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
A clang/test/Analysis/html_diagnostics/counter.c
Log Message:
-----------
[analyzer][HTMLRewriter] Cache partial rewrite results. (#80220)
This is a follow-up for 721dd3bc2 [analyzer] NFC: Don't regenerate
duplicate HTML reports.
Because HTMLRewriter re-runs the Lexer for syntax highlighting and macro
expansion purposes, it may get fairly expensive when the rewriter is
invoked multiple times on the same file. In the static analyzer (which
uses HTMLRewriter for HTML output mode) we only get away with this
because there are usually very few reports emitted per file. But if loud
checkers are enabled, such as `webkit.*`, this may explode in complexity
and even cause the compiler to run over the 32-bit SourceLocation
addressing limit.
This patch caches intermediate results so that re-lexing only needed to
happen once.
As the clever __COUNTER__ test demonstrates, "once" is still too many.
Ideally we shouldn't re-lex anything at all, which remains a TODO.
Commit: 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
https://github.com/llvm/llvm-project/commit/8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7
Author: Alexey Bataev <5361294+alexey-bataev at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
Log Message:
-----------
[TTI]Add support for strided loads/stores.
Added basic legality check and cost estimation functions for strided loads and stores.
These interfaces will be built upon in https://github.com/llvm/llvm-project/pull/80310.
Reviewers: preames
Reviewed By: preames
Pull Request: https://github.com/llvm/llvm-project/pull/80329
Commit: 59e559067b1e47b72f3c631483c1f71919d5358e
https://github.com/llvm/llvm-project/commit/59e559067b1e47b72f3c631483c1f71919d5358e
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
Log Message:
-----------
Revert "[RISCV] Refine cost on Min/Max reduction" (#80340)
Reverts llvm/llvm-project#79402. Crash reported. On closer inspection,
this patch does not handle Intrinsic::maximum and Intrinsic::minimum.
Commit: edbd93d3706b806e7c91dfd2c359476488dfcc96
https://github.com/llvm/llvm-project/commit/edbd93d3706b806e7c91dfd2c359476488dfcc96
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/stdbit/stdc_leading_ones_uc.cpp
M libc/src/stdbit/stdc_leading_ones_uc.h
M libc/src/stdbit/stdc_leading_ones_ul.cpp
M libc/src/stdbit/stdc_leading_ones_ul.h
M libc/src/stdbit/stdc_leading_ones_ull.cpp
M libc/src/stdbit/stdc_leading_ones_ull.h
M libc/src/stdbit/stdc_leading_ones_us.cpp
M libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/test/include/stdbit_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
Log Message:
-----------
[libc][stdbit] fix return types (#80337)
All of the functions I've previously implemented return an unsigned int; not
the parameter type.
Commit: 5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
https://github.com/llvm/llvm-project/commit/5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/StackSlotColoring.cpp
A llvm/test/CodeGen/RISCV/pr80052.mir
M llvm/test/CodeGen/X86/pr30821.mir
Log Message:
-----------
[StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)
The stack slot coloring pass is concerned with optimizing spill
slots. If any change is a pass is made over the function to remove
stack stores that use the same register and stack slot as an
immediately preceding load.
The register check is too simple for constant registers like AArch64
and RISC-V's zero register. This register can be used as the result
of a load if we want to discard the result, but still have the memory
access performed. Like for a volatile or atomic load.
If the code sees a load from the zero register followed by a store
of the zero register at the same stack slot, the pass mistakenly
believes the store isn't needed.
Since the main stack coloring optimization is only concerned with
spill slots, it seems reasonable that RemoveDeadStores should
only be concerned with spills. Since we never generate a reload of
x0, this avoids the issue seen by RISC-V.
Test case concept is adapted from pr30821.mir from X86. That test
had to be updated to mark the stack slot as a spill slot.
Fixes #80052.
Commit: 33b463ad9976fa7a27c1a22419297fcccd79f99f
https://github.com/llvm/llvm-project/commit/33b463ad9976fa7a27c1a22419297fcccd79f99f
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
A mlir/test/Dialect/SparseTensor/external.mlir
Log Message:
-----------
[mlir][sparse] external entry method wrapper for sparse tensors (#80326)
Similar to the emit_c_interface, this pull request adds a pass that
converts public entry methods that use sparse tensors as input
parameters and/or output return values into wrapper functions that
[dis]assemble the individual tensors that constitute the actual storage
used externally into MLIR sparse tensors. This pass can be used to
prepare the public entry methods of a program that is compiled by the
MLIR sparsifier to interface with an external runtime, e.g., when
passing sparse tensors as numpy arrays from and to Python. Note that
eventual bufferization decisions (e.g. who [de]allocates the underlying
memory) should be resolved in agreement with the external runtime
(Python, PyTorch, JAX, etc.)
Commit: 5d228eaf0f5d9c873ba12fc439609148f3f88733
https://github.com/llvm/llvm-project/commit/5d228eaf0f5d9c873ba12fc439609148f3f88733
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add beginner-focused office hours (#80308)
These are initially being hosted by a rotating cast of: @danakj
@gburgessiv @nickdesaulniers @sudonatalie
Commit: 9258f3e692493a69e0f4755bb129a5391ef10b50
https://github.com/llvm/llvm-project/commit/9258f3e692493a69e0f4755bb129a5391ef10b50
Author: Greg Clayton <gclayton at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
Log Message:
-----------
[lldb] Fix a crash when using .dwp files and make type lookup reliable with the index cache (#79544)
When using split DWARF with .dwp files we had an issue where sometimes
the DWO file within the .dwp file would be parsed _before_ the skeleton
compile unit. The DWO file expects to be able to always be able to get a
link back to the skeleton compile unit. Prior to this fix, the only time
the skeleton compile unit backlink would get set, was if the unit
headers for the main executable have been parsed _and_ if the unit DIE
was parsed in that DWARFUnit. This patch ensures that we can always get
the skeleton compile unit for a DWO file by adding a function:
```
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
```
Prior to this fix DWARFUnit had some unsafe accessors that were used to
store two different things:
```
void *DWARFUnit::GetUserData() const;
void DWARFUnit::SetUserData(void *d);
```
This was used by SymbolFileDWARF to cache the `lldb_private::CompileUnit
*` for a SymbolFileDWARF and was also used to store the `DWARFUnit *`
for SymbolFileDWARFDwo. This patch clears up this unsafe usage by adding
two separate accessors and ivars for this:
```
lldb_private::CompileUnit *DWARFUnit::GetLLDBCompUnit() const { return m_lldb_cu; }
void DWARFUnit::SetLLDBCompUnit(lldb_private::CompileUnit *cu) { m_lldb_cu = cu; }
DWARFCompileUnit *DWARFUnit::GetSkeletonUnit();
void DWARFUnit::SetSkeletonUnit(DWARFUnit *skeleton_unit);
```
This will stop anyone from calling `void *DWARFUnit::GetUserData()
const;` and casting the value to an incorrect value.
A crash could occur in `SymbolFileDWARF::GetCompUnitForDWARFCompUnit()`
when the `non_dwo_cu`, which is a backlink to the skeleton compile unit,
was not set and was NULL. There is an assert() in the code, and then the
code just will kill the program if the assert isn't enabled because the
code looked like:
```
if (dwarf_cu.IsDWOUnit()) {
DWARFCompileUnit *non_dwo_cu =
static_cast<DWARFCompileUnit *>(dwarf_cu.GetUserData());
assert(non_dwo_cu);
return non_dwo_cu->GetSymbolFileDWARF().GetCompUnitForDWARFCompUnit(
*non_dwo_cu);
}
```
This is now fixed by calling the `DWARFUnit::GetSkeletonUnit()` which
will correctly always get the skeleton compile uint for a DWO file
regardless of if the skeleton unit headers have been parse or if the
skeleton unit DIE wasn't parsed yet.
To implement the ability to get the skeleton compile units, I added code
the DWARFDebugInfo.cpp/.h that make a map of DWO ID -> skeleton
DWARFUnit * that gets filled in for DWARF5 when the unit headers are
parsed. The `DWARFUnit::GetSkeletonUnit()` will end up parsing the unit
headers of the main executable to fill in this map if it already hasn't
been done. For DWARF4 and earlier we maintain a separate map that gets
filled in only for any DWARF4 compile units that have a DW_AT_dwo_id or
DW_AT_gnu_dwo_id attributes. This is more expensive, so this is done
lazily and in a thread safe manor. This allows us to be as efficient as
possible when using DWARF5 and also be backward compatible with DWARF4 +
split DWARF.
There was also an issue that stopped type lookups from succeeding in
`DWARFDIE SymbolFileDWARF::GetDIE(const DIERef &die_ref)` where it
directly was accessing the `m_dwp_symfile` ivar without calling the
accessor function that could end up needing to locate and load the .dwp
file. This was fixed by calling the
`SymbolFileDWARF::GetDwpSymbolFile()` accessor to ensure we always get a
valid value back if we can find the .dwp file. Prior to this fix it was
down which APIs were called and if any APIs were called that loaded the
.dwp file, it worked fine, but it might not if no APIs were called that
did cause it to get loaded.
When we have valid debug info indexes and when the lldb index cache was
enabled, this would cause this issue to show up more often.
I modified an existing test case to test that all of this works
correctly and doesn't crash.
Commit: 1bc7be6bce861acfe477f0c9abd349c1dc6ea160
https://github.com/llvm/llvm-project/commit/1bc7be6bce861acfe477f0c9abd349c1dc6ea160
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add cost model coverage for vp.strided.load and vp.strided.store
Commit: 391393179a6e316909add3b8455eb6d7c7c38ddb
https://github.com/llvm/llvm-project/commit/391393179a6e316909add3b8455eb6d7c7c38ddb
Author: Kyungwoo Lee <kyulee at meta.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
Log Message:
-----------
[lld-macho] icf objc stubs (#79730)
This supports icf for objc stubs.
Commit: ecdbffe59e80666c9cadf3f80bd20bb34828fb47
https://github.com/llvm/llvm-project/commit/ecdbffe59e80666c9cadf3f80bd20bb34828fb47
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M libc/src/sys/epoll/linux/epoll_wait.cpp
Log Message:
-----------
[libc] Support epoll_wait using epoll_pwait (#80224)
The epoll_wait syscall is equivalent to calling epoll_pwait with a null
sigset. This is useful to support systems that have epoll_pwait but not
epoll_wait.
Commit: bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
https://github.com/llvm/llvm-project/commit/bfc6eaa26326e4d0d20d1f4a1f0064c6df0135bd
Author: Hana Dusíková <hanicka at hanicka.net>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/test/CoverageMapping/if.cpp
Log Message:
-----------
[coverage] fix crash in code coverage and `if constexpr` with `ExprWithCleanups` (#80292)
Fixes https://github.com/llvm/llvm-project/issues/80285
Commit: 375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
https://github.com/llvm/llvm-project/commit/375bd2201ce0d2c76cb47a02c87b8ca5ba8a3509
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV] Add aligned/unaligned tests for vp.strided.load and vp.strided.store
Commit: 07bf1ddb4eb0abfff20542fd4459bace1f72107f
https://github.com/llvm/llvm-project/commit/07bf1ddb4eb0abfff20542fd4459bace1f72107f
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
Log Message:
-----------
[mlir][sparse] support non-id map for [Dis]assembleOp (#80355)
Commit: 4eac14683855e040adaf507ed6b14e28a09f983e
https://github.com/llvm/llvm-project/commit/4eac14683855e040adaf507ed6b14e28a09f983e
Author: Greg Clayton <clayborg at gmail.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
Log Message:
-----------
Fix buildbots after #79544
https://github.com/llvm/llvm-project/pull/79544
Commit: 4a653b4df5d84c4d2df8f6d4040ef46413ac3816
https://github.com/llvm/llvm-project/commit/4a653b4df5d84c4d2df8f6d4040ef46413ac3816
Author: Peiming Liu <36770114+PeimingLiu at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
Log Message:
-----------
[mlir][sparse] Support pretty print to debug sparse iteration. (#80207)
Commit: 8fd0bce43c4c8334bcb31d214a32260914f59515
https://github.com/llvm/llvm-project/commit/8fd0bce43c4c8334bcb31d214a32260914f59515
Author: Jakub Kuderski <jakub at nod-labs.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
Log Message:
-----------
[mlir][spirv][memref] Calculate alignment for `PhysicalStorageBuffer`s (#80243)
The SPIR-V spec requires that memory accesses to
`PhysicalStorageBuffer`s are annotated with appropriate alignment
attributes [1]. Calculate these based on memref alignment attributes or
scalar type sizes.
[1] Otherwise spirv-val complains:
```
[VULKAN] ! Validation Error: [ VUID-VkShaderModuleCreateInfo-pCode-01379 ] | MessageID = 0x2a1bf17f | SPIR-V module not valid: [VUID-StandaloneSpirv-PhysicalStorageBuffer64-04708] Memory accesses with PhysicalStorageBuffer must use Aligned.
%48 = OpLoad %float %47
```
Commit: 4d89356fef1a568de790ad8b3f53dc494b461e5b
https://github.com/llvm/llvm-project/commit/4d89356fef1a568de790ad8b3f53dc494b461e5b
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
Log Message:
-----------
[libc][bazel] disable epoll_pwait2 (#80362)
Similar to #80051. The epoll_pwait2 syscall isn't available on all
target platforms, and this is causing downstream test failures. This
patch disables it until it can be detected whether or not it is
available.
Commit: ff3194037071e7f5fe859ad2173a5b67eed08b3b
https://github.com/llvm/llvm-project/commit/ff3194037071e7f5fe859ad2173a5b67eed08b3b
Author: Nico Weber <thakis at chromium.org>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] port ecb5a1b0e236
Commit: 59eadcd28f787a98a2fd5f057beb3df7950654ee
https://github.com/llvm/llvm-project/commit/59eadcd28f787a98a2fd5f057beb3df7950654ee
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M mlir/test/python/dialects/memref.py
Log Message:
-----------
[mlir][py] Reduce size of allocation memrefs in test.
Commit: cc0d752f345f0e8995bec8807e3f365f38864fb6
https://github.com/llvm/llvm-project/commit/cc0d752f345f0e8995bec8807e3f365f38864fb6
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
Log Message:
-----------
[Github] Add git to actions container image (#80341)
Commit: 70eab122bceb94b15218c86db7045ff2448ea979
https://github.com/llvm/llvm-project/commit/70eab122bceb94b15218c86db7045ff2448ea979
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[AArch64][MachinePipeliner] Add pipeliner support for AArch64 (#79589)
Add AArch64 implementations for the interfaces of MachinePipeliner pass.
The pass is disabled by default for AArch64. It is enabled by specifying
--aarch64-enable-pipeliner.
5 tests in llvm-test-suites show performance improvement by more than 5%
on a Neoverse V1 processor.
| test | improvement |
| ---------------------------------------------------------------- |
-----------:|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-dbl.test | 16%
|
| MultiSource/Benchmarks/TSVC/Recurrences-dbl/Recurrences-flt.test | 16%
|
| SingleSource/Benchmarks/Adobe-C++/loop_unroll.test | 14% |
| SingleSource/Benchmarks/Misc/flops-5.test | 13% |
| SingleSource/Benchmarks/BenchmarkGame/spectral-norm.test | 6% |
(base flags: -mcpu=neoverse-v1 -O3 -mrecip, flags for pipelining: -mllvm
-aarch64-enable-pipeliner -mllvm
-pipeliner-max-stages=100 -mllvm -pipeliner-max-mii=100 -mllvm
-pipeliner-enable-copytophi=0)
On the other hand, there are cases of significant performance
degradation. Algorithm improvements and adding the option/pragma will be
needed in the future.
Commit: acec6419e811a46050b0603dfa72fc6a169aa0f7
https://github.com/llvm/llvm-project/commit/acec6419e811a46050b0603dfa72fc6a169aa0f7
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Driver/Options.td
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
A clang/test/Driver/basic-block-address-map.c
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
A lld/test/ELF/lto/basic-block-address-map.ll
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
A llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
A llvm/test/CodeGen/X86/basic-block-address-map.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels.ll
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP] Allow basic-block-sections and labels be used together by decoupling the handling of the two features. (#74128)
Today `-split-machine-functions` and `-fbasic-block-sections={all,list}`
cannot be combined with `-basic-block-sections=labels` (the labels
option will be ignored).
The inconsistency comes from the way basic block address map -- the
underlying mechanism for basic block labels -- encodes basic block
addresses
(https://lists.llvm.org/pipermail/llvm-dev/2020-July/143512.html).
Specifically, basic block offsets are computed relative to the function
begin symbol. This relies on functions being contiguous which is not the
case for MFS and basic block section binaries. This means Propeller
cannot use binary profiles collected from these binaries, which limits
the applicability of Propeller for iterative optimization.
To make the `SHT_LLVM_BB_ADDR_MAP` feature work with basic block section
binaries, we propose modifying the encoding of this section as follows.
First let us review the current encoding which emits the address of each
function and its number of basic blocks, followed by basic block entries
for each basic block.
| | |
|--|--|
| Address of the function | Function Address |
| Number of basic blocks in this function | NumBlocks |
| BB entry 1
| BB entry 2
| ...
| BB entry #NumBlocks
To make this work for basic block sections, we treat each basic block
section similar to a function, except that basic block sections of the
same function must be encapsulated in the same structure so we can map
all of them to their single function.
We modify the encoding to first emit the number of basic block sections
(BB ranges) in the function. Then we emit the address map of each basic
block section section as before: the base address of the section, its
number of blocks, and BB entries for its basic block. The first section
in the BB address map is always the function entry section.
| | |
|--|--|
| Number of sections for this function | NumBBRanges |
| Section 1 begin address | BaseAddress[1] |
| Number of basic blocks in section 1 | NumBlocks[1] |
| BB entries for Section 1
|..................|
| Section #NumBBRanges begin address | BaseAddress[NumBBRanges] |
| Number of basic blocks in section #NumBBRanges |
NumBlocks[NumBBRanges] |
| BB entries for Section #NumBBRanges
The encoding of basic block entries remains as before with the minor
change that each basic block offset is now computed relative to the
begin symbol of its containing BB section.
This patch adds a new boolean codegen option `-basic-block-address-map`.
Correspondingly, the front-end flag `-fbasic-block-address-map` and LLD
flag `--lto-basic-block-address-map` are introduced.
Analogously, we add a new TargetOption field `BBAddrMap`. This means BB
address maps are either generated for all functions in the compiling
unit, or for none (depending on `TargetOptions::BBAddrMap`).
This patch keeps the functionality of the old
`-fbasic-block-sections=labels` option but does not remove it. A
subsequent patch will remove the obsolete option.
We refactor the `BasicBlockSections` pass by separating the BB address
map and BB sections handing to their own functions (named
`handleBBAddrMap` and `handleBBSections`). `handleBBSections` renumbers
basic blocks and places them in their assigned sections.
`handleBBAddrMap` is invoked after `handleBBSections` (if requested) and
only renumbers the blocks.
- New tests added:
- Two tests basic-block-address-map-with-basic-block-sections.ll and
basic-block-address-map-with-mfs.ll to exercise the combination of
`-basic-block-address-map` with `-basic-block-sections=list` and
'-split-machine-functions`.
- A driver sanity test for the `-fbasic-block-address-map` option
(basic-block-address-map.c).
- An LLD test for testing the `--lto-basic-block-address-map` option.
This reuses the LLVM IR from `lld/test/ELF/lto/basic-block-sections.ll`.
- Renamed and modified the two existing codegen tests for basic block
address map (`basic-block-sections-labels-functions-sections.ll` and
`basic-block-sections-labels.ll`)
- Removed `SHT_LLVM_BB_ADDR_MAP_V0` tests. Full deprecation of
`SHT_LLVM_BB_ADDR_MAP_V0` and `SHT_LLVM_BB_ADDR_MAP` version less than 2
will happen in a separate PR in a few months.
Commit: 3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
https://github.com/llvm/llvm-project/commit/3ff7caea330def5f8433e3eb2b89ae3fe5e9f9a0
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
Log Message:
-----------
[TTI] Use Register in isLoadFromStackSlot and isStoreToStackSlot [nfc] (#80339)
Commit: 58c494f47cf56a30bf50024d22661c75003db809
https://github.com/llvm/llvm-project/commit/58c494f47cf56a30bf50024d22661c75003db809
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Add -march support for many of the S extensions mentioned in the profile specification. (#79399)
This is a good portion of the extensions mentioned in the RVA23 profile
here
https://github.com/riscv/riscv-profiles/blob/main/rva23-profile.adoc
I don't believe these add any new CSRs. Sstc does add new CSRs, but we
already added them without the extension name a while back.
I tried to keep the descriptions in RISCVFeatures.td fairly short since
the strings show up in `-print-supported-extensions`.
Commit: 082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
https://github.com/llvm/llvm-project/commit/082fe9a5ddfab22f4f07d2332d2d2ec96a5be3ae
Author: Maksim Panchenko <maks at fb.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
Log Message:
-----------
[BOLT] Remove duplicate expression (#80380)
Reported by cpp check static analyzer in #80111.
Fixes #80111.
Commit: e270ec47cda26a8f0a3cdd195aa60992f109df8a
https://github.com/llvm/llvm-project/commit/e270ec47cda26a8f0a3cdd195aa60992f109df8a
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
Log Message:
-----------
[X86] X86InstrInfo.cpp - Remove dead code for memory folding, NFCI
`commuteInstruction(MI, false, OpNum, CommuteOpIdx2)` should never create
any new instruction, so we don't need to check and erase it.
Commit: 7dd790db8b77c4a833c06632e903dc4f13877a64
https://github.com/llvm/llvm-project/commit/7dd790db8b77c4a833c06632e903dc4f13877a64
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
Log Message:
-----------
[lldb] NFC fixes addressing David's feedback
David Spickett had several suggestions for
https://github.com/llvm/llvm-project/pull/79962 after I'd
already merged it. Address those.
Commit: dee8786f70a3d62b639113343fa36ef55bdbad63
https://github.com/llvm/llvm-project/commit/dee8786f70a3d62b639113343fa36ef55bdbad63
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-01 (Thu, 01 Feb 2024)
Changed paths:
M lld/ELF/Writer.cpp
M lld/test/ELF/linkerscript/insert-before.test
Log Message:
-----------
[ELF] Fix compareSections assertion failure when OutputDescs in sectionCommands are non-contiguous
In a `--defsym y0=0 -T a.lds` link where a.lds contains only INSERT
commands, the `script->sectionCommands` layout may be:
```
orphan sections
SymbolAssignment due to --defsym
sections created by INSERT commands
```
The `OutputDesc` objects are not contiguous in sortInputSections, and
`compareSections` will be called with a SymbolAssignment argument,
leading to an assertion failure.
Commit: 374a600df7207fbe2002e754a799c7595a0e4833
https://github.com/llvm/llvm-project/commit/374a600df7207fbe2002e754a799c7595a0e4833
Author: Yuta Mukai <mukai.yuta at fujitsu.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
M llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
M llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
M llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
Log Message:
-----------
[MachinePipeliner] Fix missing requirements for tests (#80386)
Add asserts requirements for tests that verify debug output.
Commit: 2147a2a4f3ef344a561677b55444ce4d028ec59f
https://github.com/llvm/llvm-project/commit/2147a2a4f3ef344a561677b55444ce4d028ec59f
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/auto-type.c
Log Message:
-----------
[clang][Interp] Not all TypeTraitExprs are of bool type
In C, they return an integer, so emit their value as such.
Commit: 58ceefe09cd992c3692bb3af7c2807ac8949ba67
https://github.com/llvm/llvm-project/commit/58ceefe09cd992c3692bb3af7c2807ac8949ba67
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Support ChooseExprs
Commit: a2da7d06c7e1ec75812ff8ced29541d4af3668c9
https://github.com/llvm/llvm-project/commit/a2da7d06c7e1ec75812ff8ced29541d4af3668c9
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Ignore LValueToRValue casts before doing the load
If the SubExpr results in an invalid pointer, we will otherwise
reject the constant expression.
Commit: 65ac8c16e028b23b49fd6b03817faa1ab6c0229d
https://github.com/llvm/llvm-project/commit/65ac8c16e028b23b49fd6b03817faa1ab6c0229d
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
Log Message:
-----------
[mlir] Skip invalid test on big endian platform (s390x) (#80246)
The buildbot test running on s390x platform keeps failing since [this
time](https://lab.llvm.org/buildbot/#/builders/199/builds/31136). This
is because of the dependency on the endianness of the platform. It
expects the format invalid in the big endian platform (s390x). We can
simply skip it.
See: https://discourse.llvm.org/t/mlir-s390x-linux-failure/76695
Commit: a8b5994b337cf1d461202a65204a4ee6c5eae341
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp][NFC] Add a broken test case
The LHS of the subtraction returns 16 right now, but should
return 0.
Commit: d9c20e437fe110fb79b5ca73a52762e5b930b361
https://github.com/llvm/llvm-project/commit/d9c20e437fe110fb79b5ca73a52762e5b930b361
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/test/CodeGen/aarch64-inline-asm.c
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
Log Message:
-----------
[AArch64][SME] Implement inline-asm clobbers for za/zt0 (#79276)
This enables specifing "za" or "zt0" to the clobber list for inline asm.
This complies with the acle SME addition to the asm extension here:
https://github.com/ARM-software/acle/pull/276
Commit: 0be39155bd22258b3e90468b6184bfd87a948bec
https://github.com/llvm/llvm-project/commit/0be39155bd22258b3e90468b6184bfd87a948bec
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/Interp.cpp
M clang/test/Sema/warn-cast-qual.c
Log Message:
-----------
[clang][Interp] Protect stores against dummy pointers
Commit: 3be79790ede30762f73b95218be8877c3b2c3774
https://github.com/llvm/llvm-project/commit/3be79790ede30762f73b95218be8877c3b2c3774
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang] Update documentation for `#pragma diagnostic` (#78095)
GCC has changed over the past decade, and we're not implementing
everything they do.
Fixes #51472
---------
Co-authored-by: Aaron Ballman <aaron at aaronballman.com>
Commit: 75c4339ef31922bf8c883a7a5dfe638ec6818ab2
https://github.com/llvm/llvm-project/commit/75c4339ef31922bf8c883a7a5dfe638ec6818ab2
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/AST/Interp/EvaluationResult.cpp
Log Message:
-----------
[clang][Interp][NFC] Implement dumping Invalid/Valid results
This was just an omission from an earlier commit, clearly
we can print them.
Commit: 0f26441cb83c1dea9aef12c748a79e3f38e3230a
https://github.com/llvm/llvm-project/commit/0f26441cb83c1dea9aef12c748a79e3f38e3230a
Author: Maciej Gabka <maciej.gabka at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
Log Message:
-----------
[TLI][AArch64] Adjust TLI mappings to vector functions taking linear pointers (#80296)
The masked symbols in SLEEF are incorrectly implemented as calls to non
masked variants, what only works fine for functions which do not modify
memory.
For vector variants which modify memory we can only use a non masked
symbols for now.
The SVE ArmPL mappings need to be removed for now as well.
Commit: 237a799e938aca86dc7e62def792b26974bbae5d
https://github.com/llvm/llvm-project/commit/237a799e938aca86dc7e62def792b26974bbae5d
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/IR/Builders.cpp
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Notify about block insertion when cloning an op (#80262)
`OpBuilder::clone(Operation &)` should trigger not only
`notifyOperationInserted` but also `notifyBlockInserted` (for all block
contained in `op`).
Commit: a792cb6e3e03aff22dabb6cc94db68d15d953a55
https://github.com/llvm/llvm-project/commit/a792cb6e3e03aff22dabb6cc94db68d15d953a55
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/lib/IR/Builders.cpp
Log Message:
-----------
[mlir][IR] Do not trigger `notifyOperationInserted` for unlinked ops (#80278)
This commit changes `OpBuilder::create` and `OpBuilder::createOrFold`
such that `notifyOperationInserted` is no longer triggered if no
insertion point is set. In such a case, an unlinked operation is created
but not inserted, so `notifyOperationInserted` should not be triggered.
Note: Inserting another op into a block that belongs to an unlinked op
(e.g., by the builder of the unlinked op) will trigger a notification.
Commit: c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
https://github.com/llvm/llvm-project/commit/c07fcd45f140bb95fb0f1ed10468db2bb6b1a77b
Author: ManuelvOK <info at manuel-thieme.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
Log Message:
-----------
[Coverage] Map regions from system headers (#76950)
In 2155195131a57f2f01e7cfabb85bb027518c2dc6, the
"system-headers-coverage" option has been added but not used in all
necessary places.
This is the recommit since it has been reverted in
faef68bca852d08511ea0311d8a0d221cb202e73
Potential reviewers: @gulfemsavrun @petrhosek
Co-authored-by: Manuel Kalettka <manuel.kalettka at kernkonzept.com>
Commit: b840d2968391dd610b792a65133a1edc1bcc397c
https://github.com/llvm/llvm-project/commit/b840d2968391dd610b792a65133a1edc1bcc397c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Send notifications for `cloneRegionBefore` (#66871)
Similar to `OpBuilder::clone`, operation/block insertion notifications
should be sent when cloning the contents of a region. E.g., this is to
ensure that the newly created operations are put on the worklist of the
greedy pattern rewriter driver.
Also move `cloneRegionBefore` from `RewriterBase` to `OpBuilder`. It
only creates new IR, so it should be part of the builder API (like
`clone(Operation &)`). The function does not have to be virtual. Now
that notifications are properly sent, the override in the dialect
conversion is no longer needed.
Commit: 73e546625d6567e5a33454741d257b6929c89635
https://github.com/llvm/llvm-project/commit/73e546625d6567e5a33454741d257b6929c89635
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix up broken test case
This was not working right on armv8:
https://lab.llvm.org/buildbot/#/builders/245/builds/20020
Commit: 9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
https://github.com/llvm/llvm-project/commit/9efdccb26f35e9b32aa0f303eb0cfcec1e7c2c71
Author: Matthias Springer <me at m-sp.org>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
Log Message:
-----------
[mlir][memref] `memref.subview`: Verify result strides with rank reductions (#80158)
This is a follow-up on #79865. Result strides are now also verified if
the `memref.subview` op has rank reductions.
Commit: 9e649518e6038a5b9ea38cfa424468657d3be59e
https://github.com/llvm/llvm-project/commit/9e649518e6038a5b9ea38cfa424468657d3be59e
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/test/Preprocessor/aarch64-target-features.c
M clang/test/Preprocessor/init-aarch64.c
Log Message:
-----------
[Clang][AArch64] Add missing SME macros (#80293)
__ARM_STATE_ZA and __ARM_STATE_ZT0 are set when the compiler can parse
the "za" and "zt0" strings in the SME attributes.
__ARM_FEATURE_SME and __ARM_FEATURE_SME2 are set when the compiler can
generate code for attributes with "za" and "zt0" state, respectively.
__ARM_FEATURE_LOCALLY_STREAMING is set when the compiler supports the
__arm_locally_streaming attribute.
Commit: 438fe1db09b0c20708ea1020519d8073c37feae8
https://github.com/llvm/llvm-project/commit/438fe1db09b0c20708ea1020519d8073c37feae8
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
Log Message:
-----------
CoverageMappingWriter: Emit `Decision` before `Expansion` (#78966)
To relax scanning record, tweak order by `Decision < Expansion`, or
`Expansion` could not be distinguished whether it belonged to `Decision`
or not.
Relevant to #77871
Commit: acf6811d0f2b6b453be46ddf7e046e1346991c98
https://github.com/llvm/llvm-project/commit/acf6811d0f2b6b453be46ddf7e046e1346991c98
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/ReleaseNotes.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
A llvm/test/TableGen/deftype.td
Log Message:
-----------
[TableGen] Support type aliases via new keyword deftype
We can use `deftype` (not using `typedef` here to be consistent
with `def`, `defm`, `defset`, `defvar`, etc) to define type aliases.
Currently, only primitive types and type aliases are supported to be
the source type and `deftype` statements can only appear at the top
level.
Reviewers: fpetrogalli, Artem-B, nhaehnle, jroelofs
Reviewed By: jroelofs, nhaehnle, Artem-B
Pull Request: https://github.com/llvm/llvm-project/pull/79570
Commit: a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
https://github.com/llvm/llvm-project/commit/a52e9eca3001b23c7952300e5a32b5c58ef2e0e2
Author: Nemanja Ivanovic <nemanja.i.ibm at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Lex/PPMacroExpansion.cpp
A clang/test/Preprocessor/has_builtin_cpuid.c
Log Message:
-----------
[Preprocessor] Fix __has_builtin for CPU ID functions (#80058)
My recent commit (67c1c1d) made the CPU ID builtins target-independent
so they can be used on PPC as well. However, that had the unintended
consequence of changing the behaviour of __has_builtin in that it
reports these as supported at the pre-processor level. This makes it
impossible to guard the use of these with this feature test macro which
is clearly not ideal.
This patch restores the behaviour of __has_builtin for __builtin_cpu_is,
__builtin_cpu_init,
__builtin_cpu_supports. Now the preprocessor queries the target to
determine whether the target supports the builtin.
Commit: 42ec9934e1079742e0b5d839e420bc3f746fc73b
https://github.com/llvm/llvm-project/commit/42ec9934e1079742e0b5d839e420bc3f746fc73b
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
Log Message:
-----------
[PowerPC] Fix gcc -Wparentheses warning [NFC]
Without this gcc warns like
../lib/Target/PowerPC/PPCAsmPrinter.cpp:1650:33: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
1650 | (InstDisp >= -32768) &&
| ~~~~~~~~~~~~~~~~~~~~~^~
1651 | "Expecting the instruction displacement for local-exec TLS "
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
1652 | "variables to be between [-32768, 32768)!");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
https://github.com/llvm/llvm-project/commit/5b8e1a6ebf11b6e93bcc96a0d009febe4bb3d7bc
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/test/Transforms/IndVarSimplify/pr79861.ll
Log Message:
-----------
[SCEVExpander] Do not reuse disjoint or (#80281)
SCEV treats "or disjoint" the same as "add nsw nuw". However, when
expanding, we cannot generally replace an add SCEV node with an "or
disjoint" instruction. Just dropping the poison flag is insufficient in
this case, we would have to actually convert the or into an add.
This is a partial fix for #79861.
Commit: 84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
https://github.com/llvm/llvm-project/commit/84c8d0377de1f7f45e65e85d1f3cc69ca5e29af5
Author: lorenzo chelini <l.chelini at icloud.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
Log Message:
-----------
[MLIR][Vector] Implement memory effect for print (#80400)
Add write memory effect for the print operation. The exact memory
behavior is implemented in other print-like operations such as
`transform::PrintOp` or `gpu::printf`.
Providing memory behavior allows using the operation in passes like
buffer deallocation instead of emitting an error.
Commit: c2dea7122cd9f559f64cd0b34431d21e61f5bf15
https://github.com/llvm/llvm-project/commit/c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
Log Message:
-----------
[mlir][ArmSME] Fold extracts from 3D create_masks of SME-like masks (#80148)
When unrolling the reduction dimension of something like a matmul for
SME, it is possible to get 3D masks, which are vectors of SME-like
masks. The 2D masks for individual operations are then extracted from
the 3D masks.
i.e.:
```mlir
%mask = vector.create_mask %nonConstantDim, %a, %b : vector<4x[4]x[4]xi1>
%subMask = vector.extract %mask[2]
: vector<[4]x[4]xi1> from vector<4x[4]x[4]xi1>
```
ArmSME only supports lowering 2D create_masks, so we must fold the
extract into the create_mask. This can be done by checking if the
extraction index is within the true region, then using that select the
first dimension of the 2D mask. This is shown below.
```mlir
%extractionInTrueRegion = arith.cmpi slt, %c2, %nonConstantDim : index
%newMaskFrontDim = arith.select %extractionInTrueRegion, %a, %c0 : index
%subMask = vector.create_mask %newMaskFrontDim, %b : vector<[4]x[4]xi1>
```
Commit: 6d1d2c67e7597dc417c097d5027558b0159ed2e2
https://github.com/llvm/llvm-project/commit/6d1d2c67e7597dc417c097d5027558b0159ed2e2
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
[clang] Fix a possible out-of-bounds read (#80023)
Fixes #79964
Commit: 4b8e514334786e1aa6f86d7d777385aa9702d835
https://github.com/llvm/llvm-project/commit/4b8e514334786e1aa6f86d7d777385aa9702d835
Author: Tuan Chuong Goh <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Pre-Commit tests for Legalize BSWAP Vectors
Commit: 2cf415f2a03433fd3661938fb2f4af0754ad2274
https://github.com/llvm/llvm-project/commit/2cf415f2a03433fd3661938fb2f4af0754ad2274
Author: Peter Smith <peter.smith at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/SecurityTransparencyReports.rst
Log Message:
-----------
Add security group 2023 transparency report. (#80320)
Commit: ffb3589b8cb3468713d25ff2a4378918eafa7044
https://github.com/llvm/llvm-project/commit/ffb3589b8cb3468713d25ff2a4378918eafa7044
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/vector
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
Log Message:
-----------
[libc++] Remove transitive <locale> include from <vector> (#80282)
This reduces the time to include `<vector>` from 468ms to 367ms.
Commit: 9410019ac977141bc73aee19690b5896ded59219
https://github.com/llvm/llvm-project/commit/9410019ac977141bc73aee19690b5896ded59219
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/ctpop-combine.ll
M llvm/test/CodeGen/X86/popcnt.ll
Log Message:
-----------
[X86] Add i8 CTPOP lowering using i32 MUL (#79989)
This is the first basic proposal in #79823 - we can investigate improving support for other widths if we can find further use cases.
Commit: 10943695f76f513503162026669e84cb72275e84
https://github.com/llvm/llvm-project/commit/10943695f76f513503162026669e84cb72275e84
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/bswap.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)
Add support of i16 vector operation for BSWAP and change to TableGen to
select instructions
Handle vector types that are smaller/larger than legal for BSWAP
Commit: cca9f9b78fc657c280f7e4024a552af43a315bdb
https://github.com/llvm/llvm-project/commit/cca9f9b78fc657c280f7e4024a552af43a315bdb
Author: Benjamin Kramer <benny.kra at googlemail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[bazel] Add missing dependency for c2dea7122cd9f559f64cd0b34431d21e61f5bf15
Commit: 2d1f5af8b0b07a4ac19eae699aa660debb1a5613
https://github.com/llvm/llvm-project/commit/2d1f5af8b0b07a4ac19eae699aa660debb1a5613
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
Log Message:
-----------
[AMDGPU] Reduce duplication in SOP instruction definitions. NFCI. (#80413)
Use !tolower instead of repeating the name when defining a renamed Real
instruction.
Commit: 589b21f38932ed1150906fc30307f030c62f6e8f
https://github.com/llvm/llvm-project/commit/589b21f38932ed1150906fc30307f030c62f6e8f
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/include/__memory/temporary_buffer.h
Log Message:
-----------
[libc++][NFC] Remove <__type_traits/alignment_of.h> include
Commit: 2e669ff59ebb096d67d02ec51dbb7050dc5e2235
https://github.com/llvm/llvm-project/commit/2e669ff59ebb096d67d02ec51dbb7050dc5e2235
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] LowerBuildVector* - share the same SDLoc argument instead of recreating it over and over again.
Commit: b5d35feacb7246573c6a4ab2bddc4919a4228ed5
https://github.com/llvm/llvm-project/commit/b5d35feacb7246573c6a4ab2bddc4919a4228ed5
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/avx512-arith.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/combine-addo.ll
M llvm/test/CodeGen/X86/combine-and.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-pavg.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/combine-sub.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/combine-urem.ll
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/extract-concat.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-shuffle.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/packus.ll
M llvm/test/CodeGen/X86/paddus.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/pr48215.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr61964.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/pr63507.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-512.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-512.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - load+sign-extend vector constants that can be stored in a truncated form (#79815)
Reduce the size of the vector constant by storing it in the constant pool in a truncated form, and sign-extend it as part of the load.
I've extended the existing FixupConstant functionality to support these sext constant rebuilds - we still select the smallest stored constant entry and prefer vzload/broadcast/vextload for same bitwidth to avoid domain flips.
I intend to add the matching load+zero-extend handling in a future PR, but that requires some alterations to the existing MC shuffle comments handling first.
Commit: ffd84a6a9afc43968fe24c9057bd4f86e148e283
https://github.com/llvm/llvm-project/commit/ffd84a6a9afc43968fe24c9057bd4f86e148e283
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in MemRefOps.cpp (NFC)
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2763:23:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() == droppedDims.size() && "incorrect number of bits");
~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~
llvm-project/mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp:2764:38:
error: comparison of integers of different signs: 'int64_t' (aka 'long') and 'size_type' (aka 'unsigned long') [-Werror,-Wsign-compare]
assert(t1.getRank() - t2.getRank() == droppedDims.count() &&
~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~
Commit: d912f1f0cb49465b08f82fae89ece222404e5640
https://github.com/llvm/llvm-project/commit/d912f1f0cb49465b08f82fae89ece222404e5640
Author: NAKAMURA Takumi <geek4civic at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
A llvm/test/tools/llvm-cov/mcdc-macro.test
Log Message:
-----------
[Coverage] Let `Decision` take account of expansions (#78969)
The current implementation (D138849) assumes `Branch`(es) would follow
after the corresponding `Decision`. It is not true if `Branch`(es) are
forwarded to expanded file ID. As a result, consecutive `Decision`(s)
would be confused with insufficient number of `Branch`(es).
`Expansion` will point `Branch`(es) in other file IDs if `Expansion` is
included in the range of `Decision`.
Fixes #77871
---------
Co-authored-by: Alan Phipps <a-phipps at ti.com>
Commit: 4cf2ed4396ddeda1487d6c5151a7dfdf14573920
https://github.com/llvm/llvm-project/commit/4cf2ed4396ddeda1487d6c5151a7dfdf14573920
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Fix -Wsign-compare in X86MCInstLower.cpp (NFC)
llvm-project/llvm/lib/Target/X86/X86MCInstLower.cpp:1588:48:
error: comparison of integers of different signs: 'unsigned int' and 'int' [-Werror,-Wsign-compare]
if (C && C->getType()->getScalarSizeInBits() == SrcEltBits) {
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~
1 error generated.
Commit: 319f4c03ba2909c7240ac157cc46216bf1518c10
https://github.com/llvm/llvm-project/commit/319f4c03ba2909c7240ac157cc46216bf1518c10
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaChecking.cpp
M clang/test/Sema/aarch64-sme-func-attrs.c
Log Message:
-----------
[Clang][AArch64] Emit 'unimplemented' diagnostic for SME (#80295)
When a function F has ZA and ZT0 state, calls another function G that
only shares ZT0 state with its caller, F will have to save ZA before
the call to G, and restore it afterwards (rather than setting up a
lazy-sve).
This is not yet implemented in LLVM and does not result in a
compile-time error either. So instead of silently generating incorrect
code, it's better to emit an error saying this is not yet implemented.
Commit: b8025d1482a9664463cfc727a0e51cad86fdf2fe
https://github.com/llvm/llvm-project/commit/b8025d1482a9664463cfc727a0e51cad86fdf2fe
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
Reapply "[AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode." (#80303)
Reapply #71556 with added lit test constraint: `REQUIRES: amdgpu-registered-target`.
This reverts commit 9791e5414960f92396582b9e9ee503ac15799312.
Commit: c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
https://github.com/llvm/llvm-project/commit/c66cedb3a7326c8403aae9a3928f3f4ab7fb2173
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
Log Message:
-----------
[SCEV] Add SCEV analysis tests with congruent IVs.
This patch adds a set of tests taken
from/llvm/test/Transforms/IndVarSimplify/iv-poison.ll with multiple
congruent IVs but different set of flags on the increments.
Extra tests for https://github.com/llvm/llvm-project/pull/80430.
Commit: 7a4570acdb1a32935d96831142748ba3298a2b7f
https://github.com/llvm/llvm-project/commit/7a4570acdb1a32935d96831142748ba3298a2b7f
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/HLFIR/array-ctor-character.f90
Log Message:
-----------
[flang] sanitize set_length in lowering (#80412)
In fortran, it is possible to give a negative "i" in "character(i)" in
which case the standard says the length is zero. So the length must be
sanitized as max(0, user_input) in lowering.
This is already done when lowering specification parts, but was not done
when "character(i)" appears in array constructors. Sanitize the length
when lowering SetLength in lowering.
Fixes https://github.com/llvm/llvm-project/issues/80270
Commit: 92bbf615f50c67030ed536f08cc5bb266e0718db
https://github.com/llvm/llvm-project/commit/92bbf615f50c67030ed536f08cc5bb266e0718db
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
Log Message:
-----------
[Flang][MLIR][OpenMP] Use function-attached target attributes for OpenMP lowering (#78291)
This patch removes the omp.target module attribute, since the
information it held on the target CPU and features is available through
the fir.target_cpu and fir.target_features module attributes. Target
outlining during the MLIR to LLVM IR translation stage is updated, so
that these attributes, at that point available as llvm.func attributes,
are passed along to the newly created function.
Commit: 3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
https://github.com/llvm/llvm-project/commit/3c2a73ad6c2f3a3e5846d33688f790e85c420ae5
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] FP<->INT helpers - share the same SDLoc argument instead of recreating it over and over again.
Commit: a1df10da59e8eb0c1d90df81bf9000d2f7869328
https://github.com/llvm/llvm-project/commit/a1df10da59e8eb0c1d90df81bf9000d2f7869328
Author: Konstantin Zhuravlyov <kzhuravl_dev at outlook.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
AMDGPU/NFC: Add predicate for supporting ds_add_f64 (#80379)
Commit: 1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
https://github.com/llvm/llvm-project/commit/1f4a5d8a5b2ba62f3d9f65bdd4a65d6f5593d4cd
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/test/AST/Interp/c.c
Log Message:
-----------
[clang][Interp] Fix broken test case again
Instead of asserting that it's wrong, assert the correct
value.
See the discussion in
https://github.com/llvm/llvm-project/commit/a8b5994b337cf1d461202a65204a4ee6c5eae341
Commit: 274d1b000cae57acf2dc988fcb65cfe7383ed2b0
https://github.com/llvm/llvm-project/commit/274d1b000cae57acf2dc988fcb65cfe7383ed2b0
Author: Harald van Dijk <harald at gigawatt.nl>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/lib/CodeGen/TargetLoweringBase.cpp
Log Message:
-----------
[NFC] Add useFPRegsForHalfType(). (#74147)
Currently, half operations can be promoted in one of two ways.
* If softPromoteHalfType() returns false, fp16 values are passed around
in fp32 registers, and whole chains of fp16 operations are promoted to
fp32 in one go.
* If softPromoteHalfType() returns true, fp16 values are passed around
in i16 registers, and individual fp16 operations are promoted to fp32
and the result truncated to fp16 right away.
The softPromoteHalfType behavior is necessary for correctness, but
changing this for an existing target breaks the ABI. Therefore, this
commit adds a third option:
* If softPromoteHalfType() returns true and useFPRegsForHalfType()
returns true as well, fp16 values are passed around in fp32 registers,
but individual fp16 operations are promoted to fp32 and the result
truncated to fp16 right away.
This change does not yet update any target to make use of it.
Commit: 1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
https://github.com/llvm/llvm-project/commit/1e7d5871eed1bdf1eeb4b50eb9b911774f420ca1
Author: lifengxiang1025 <lifengxiang.1025 at bytedance.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Analysis/MemoryProfileInfo.cpp
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
Log Message:
-----------
[MemProf] Fix when CallStackTrie has a single chain to leaf with multi alloc type (#79433)
Fix one corner case when `CallStackTrie` has a single chain to leaf with
multi alloc type. This will cause stackIds in function summary is empty.
Commit: 275729ae06d568e9589392c142a416fb8c2bb1a8
https://github.com/llvm/llvm-project/commit/275729ae06d568e9589392c142a416fb8c2bb1a8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
Log Message:
-----------
[X86] Generalize i8 CTPOP expansion to work with any input with 8 or less active bits
Extend #79989 slightly to use KnownBits on the CTPOP input - this should make it easier to add additional cases identified in #79823
Commit: 66b339aa6ba3ee63806c87630aec1dc6a45e63c5
https://github.com/llvm/llvm-project/commit/66b339aa6ba3ee63806c87630aec1dc6a45e63c5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
Log Message:
-----------
[IndVars] Regenerate test checks (NFC)
Commit: a986f5e218ab8a68097fcc1fd3234b8743839ef8
https://github.com/llvm/llvm-project/commit/a986f5e218ab8a68097fcc1fd3234b8743839ef8
Author: alexfh <alexfh at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Frontend/TextDiagnostic.cpp
Log Message:
-----------
Fix clang crash when printing highlighted code in diagnostic (after #66514) (#80442)
Implements the fix proposed by Evgeny Eltsin on
https://github.com/llvm/llvm-project/pull/66514#issuecomment-1924039038.
No test case provided, since the bug is extremely sensitive to the
preprocessor
state (headers, macros, including the ones defined on command line), and
it
turned out to be non-trivial to create an isolated test.
Commit: fbf9356be07408efc05621a7a8d0472a61c66228
https://github.com/llvm/llvm-project/commit/fbf9356be07408efc05621a7a8d0472a61c66228
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/test/CodeGen/X86/ctpop-mask.ll
Log Message:
-----------
[X86] Add ctpop-mask.ll - test coverage based off #79823
Commit: 46b6756255029f442165148115bad99d04057622
https://github.com/llvm/llvm-project/commit/46b6756255029f442165148115bad99d04057622
Author: Yaxun (Sam) Liu <yaxun.liu at amd.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
M clang/test/Driver/hip-options.hip
Log Message:
-----------
[AMDGPU] Diagnose unaligned atomic (#80322)
AMDGPU does not support unaligned atomics, therefore make the warning an
error.
This patch is transferred from
https://reviews.llvm.org/D99201
Commit: 43dd1e84df1ecdad872e1004af47b489e08fc228
https://github.com/llvm/llvm-project/commit/43dd1e84df1ecdad872e1004af47b489e08fc228
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
Log Message:
-----------
[SCEV] Move canReuseInstruction() helper into SCEV (NFC)
To allow reusing it in IndVars.
Commit: 7524b037257cdeb67e3ed80364da94eab8e98122
https://github.com/llvm/llvm-project/commit/7524b037257cdeb67e3ed80364da94eab8e98122
Author: Natalie Chouinard <sudonatalie at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/docs/GettingInvolved.rst
Log Message:
-----------
[docs] Add note about calendar timezones (#80346)
Commit: 67eee4a029797c09129889c3655416d1be487cfe
https://github.com/llvm/llvm-project/commit/67eee4a029797c09129889c3655416d1be487cfe
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
M libcxx/include/libcxx.imp
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/support/count_new.h
Log Message:
-----------
[libc++] Optimize vector growing of trivially relocatable types (#76657)
This patch introduces a new trait to represent whether a type is
trivially
relocatable, and uses that trait to optimize the growth of a std::vector
of trivially relocatable objects.
```
--------------------------------------------------
Benchmark old new
--------------------------------------------------
bm_grow<int> 1354 ns 1301 ns
bm_grow<std::string> 5584 ns 3370 ns
bm_grow<std::unique_ptr<int>> 3506 ns 1994 ns
bm_grow<std::deque<int>> 27114 ns 27209 ns
```
This also changes to order of moving and destroying the objects when
growing the vector. This should not affect our conformance.
Commit: 30503116550c2bffe706366e93dbaee15850014c
https://github.com/llvm/llvm-project/commit/30503116550c2bffe706366e93dbaee15850014c
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn build] Port 67eee4a02979
Commit: b629414ae13d6dcd641e92d0389c5d4b7638a644
https://github.com/llvm/llvm-project/commit/b629414ae13d6dcd641e92d0389c5d4b7638a644
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
Log Message:
-----------
[libc][NFC] Simplify logic in `sqrt` (#80426)
Commit: 28865da37451904c4654f20cdaddee815fdeff1d
https://github.com/llvm/llvm-project/commit/28865da37451904c4654f20cdaddee815fdeff1d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
Log Message:
-----------
[LSR][term-fold] Adjust expansion budget based on trip count (#80304)
Follow up to https://github.com/llvm/llvm-project/pull/74747
This change extends the previously added fixed expansion threshold by
scaling down the cost allowed for an expansion for a loop with either a
small known trip count or a profile which indicates the trip count is
likely small. The goal here is to improve code generation for a loop
nest where the outer loop has a high trip count, and the inner loop runs
only a handful of iterations.
---------
Co-authored-by: Nikita Popov <github at npopov.com>
Commit: 1437a83491cbe4af1b452a3f862a6b609057c26d
https://github.com/llvm/llvm-project/commit/1437a83491cbe4af1b452a3f862a6b609057c26d
Author: Rushi Bhamani <99245918+rushiraj7677 at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
Log Message:
-----------
Add --abort-on-invalid-reduction to more lit tests (#80263)
Commit: b78b264518e0f341d99a4291cbf24134c7536f6d
https://github.com/llvm/llvm-project/commit/b78b264518e0f341d99a4291cbf24134c7536f6d
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/test/Analysis/CostModel/RISCV/gep.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[TTI] Add costing for vp.strided.load and vp.strided.store (#80360)
The primary motivation of this patch is to add testing infrastructure
atop the recently landed 8ad14b6d90121d2d0687a3a7f6f6c6f2b34c4aa7, so
that we can separate the costing aspects of strided memory operations
from the SLP implementation details.
I want to be clear that I am *not* proposing that we use the
vp.strided.* forms as our canonical IR representation. I'm merely using
them as a testing vehicle to exercise the costing machinery. The
canonical IR form remains a masked.gather or masked.scatter. I do want
to explore adding a non-vp strided load/store intrinsic, but that's a
separate line of work.
There is one costing change included in this. As I wrote my test, I
discovered that the default implementation was scalarized (if invoked
via generic routines such as getInstructionCost), and when adding the
call into the strided specific costing discovered that we hadn't modeled
the fallback to scalarization properly in the initial patch. After
fixing that, there is a minor difference in scalarization cost reported
for the unaligned case but I believe that to be uninteresting.
For the record, I did confirm that vp.strided.store is lowered to a
strided store on RISCV. :)
Commit: a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
https://github.com/llvm/llvm-project/commit/a768bc6ef6a0c1a7365134505fdfcaeeaaffdb41
Author: Manish Kausik H <46352931+Nirhar at users.noreply.github.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
A llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
Log Message:
-----------
[SelectionDAG] Use unaligned store to move AVX registers onto stack for `extractelement` (#78422)
Prior to this patch, SelectionDAG generated aligned move onto stacks for
AVX registers when the function was marked as a no-realign-stack
function. This lead to misalignment between the stack and the
instruction generated. This patch fixes the issue.
Fixes #77730
Commit: 7b08b4360b488b35428c97132b3f9d2a777bd770
https://github.com/llvm/llvm-project/commit/7b08b4360b488b35428c97132b3f9d2a777bd770
Author: Nathan Gauër <brioche at google.com>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
Log Message:
-----------
[SPIR-V] add convergence region analysis (#78456)
This new analysis returns a hierarchical view of the convergence regions
in the given function.
This will allow our passes to query which basic block belongs to which
convergence region, and structurize the code in consequence.
Definition
----------
A convergence region is a CFG with:
- a single entry node.
- one or multiple exit nodes (different from LLVM's regions).
- one back-edge
- zero or more subregions.
Excluding sub-regions nodes, the nodes of a region can only reference a
single convergence token. A subregion uses a different convergence
token.
Algorithm
---------
This algorithm assumes all loops are in the Simplify form.
Create an initial convergence region for the whole function.
- the convergence token is the function entry token.
- the entry is the function entrypoint.
- Exits are all the basic blocks terminating with a return instruction.
Take the function CFG, and process it in DAG order (ignoring
back-edges). If a basic block is a loop header:
- Create a new region.
- The parent region is the parent's loop region if any, otherwise, the
top level region.
- The region blocks are all the blocks belonging to this loop.
- For each loop exit: - visit the rest of the CFG in DAG order (ignore
back-edges). - if the region's convergence token is found, add all the
blocks dominated by the exit from which the token is reachable to the
region.
- continue the algorithm with the loop headers successors.
Commit: 3fac3a94b7ae5d2c3096fb551531ae0363ed833f
https://github.com/llvm/llvm-project/commit/3fac3a94b7ae5d2c3096fb551531ae0363ed833f
Author: Fangrui Song <i at maskray.me>
Date: 2024-02-02 (Fri, 02 Feb 2024)
Changed paths:
M .github/workflows/containers/github-action-ci/Dockerfile
M bolt/include/bolt/Core/BinaryContext.h
M bolt/include/bolt/Rewrite/RewriteInstance.h
M bolt/lib/Passes/BinaryPasses.cpp
M bolt/lib/Profile/StaleProfileMatching.cpp
M bolt/lib/Profile/YAMLProfileReader.cpp
M bolt/lib/Rewrite/RewriteInstance.cpp
M bolt/lib/Target/X86/X86MCPlusBuilder.cpp
M bolt/test/X86/linux-orc.s
A bolt/test/X86/phdr-out-of-order.test
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.cpp
M clang-tools-extra/clang-tidy/cppcoreguidelines/PreferMemberInitializerCheck.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/docs/clang-tidy/checks/cppcoreguidelines/prefer-member-initializer.rst
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init-assignment.cpp
R clang-tools-extra/test/clang-tidy/checkers/cppcoreguidelines/prefer-member-initializer-modernize-use-default-member-init.cpp
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/include/clang/AST/DeclTemplate.h
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/CodeGenOptions.def
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Rewrite/Core/HTMLRewrite.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/DeclTemplate.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/Interp/EvaluationResult.cpp
M clang/lib/AST/Interp/Interp.cpp
M clang/lib/AST/Interp/Interp.h
M clang/lib/AST/TypePrinter.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AArch64.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/CodeGen/BackendUtil.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGCall.cpp
M clang/lib/CodeGen/CGObjCMac.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/CodeGenPGO.cpp
M clang/lib/CodeGen/CoverageMappingGen.cpp
M clang/lib/Driver/ToolChains/AMDGPU.cpp
M clang/lib/Driver/ToolChains/AMDGPU.h
M clang/lib/Driver/ToolChains/AMDGPUOpenMP.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/HIPAMD.cpp
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/UnwrappedLineParser.cpp
M clang/lib/Frontend/FrontendActions.cpp
M clang/lib/Frontend/TextDiagnostic.cpp
M clang/lib/Lex/PPMacroExpansion.cpp
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseTemplate.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Rewrite/HTMLRewrite.cpp
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaConcept.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Sema/SemaTemplateInstantiate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
M clang/test/AST/Interp/c.c
A clang/test/Analysis/html_diagnostics/counter.c
M clang/test/CXX/temp/p3.cpp
M clang/test/CodeGen/RISCV/riscv-inline-asm.c
M clang/test/CodeGen/aarch64-inline-asm.c
M clang/test/CodeGen/aarch64-sme-intrinsics/aarch64-sme-attrs.cpp
M clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c
M clang/test/CodeGen/aarch64-targetattr.c
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64.cl
M clang/test/CoverageMapping/if.cpp
M clang/test/Driver/amdgpu-openmp-toolchain.c
M clang/test/Driver/amdgpu-toolchain-opencl.cl
A clang/test/Driver/basic-block-address-map.c
M clang/test/Driver/hip-options.hip
M clang/test/Driver/rocm-detect.hip
M clang/test/Interpreter/cxx20-modules.cppm
M clang/test/Modules/aarch64-sme-keywords.cppm
M clang/test/OpenMP/declare_simd_messages.cpp
M clang/test/Preprocessor/aarch64-target-features.c
A clang/test/Preprocessor/has_builtin_cpuid.c
M clang/test/Preprocessor/init-aarch64.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/Sema/PR2919-builtin-types-compat-strips-crv.c
M clang/test/Sema/aarch64-sme-func-attrs.c
M clang/test/Sema/auto-type.c
M clang/test/Sema/c2x-auto.c
M clang/test/Sema/c2x-bool.c
M clang/test/Sema/check-increment.c
M clang/test/Sema/inline-asm-validate-riscv.c
M clang/test/Sema/warn-cast-qual.c
M clang/test/SemaCXX/datasizeof.cpp
M clang/test/SemaCXX/decomposition-openmp.cpp
M clang/unittests/Format/TokenAnnotatorTest.cpp
M flang/include/flang/Lower/AbstractConverter.h
M flang/include/flang/Tools/CrossToolHelpers.h
M flang/lib/Frontend/FrontendActions.cpp
M flang/lib/Lower/ConvertCall.cpp
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Lower/ConvertType.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp
M flang/test/HLFIR/invalid.fir
M flang/test/Lower/HLFIR/array-ctor-character.f90
M flang/test/Lower/HLFIR/minval.f90
M flang/test/Lower/HLFIR/procedure-pointer.f90
M flang/test/Lower/OpenACC/acc-bounds.f90
M flang/test/Lower/OpenACC/acc-data-operands.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-declare.f90
M flang/test/Lower/OpenACC/acc-enter-data.f90
M flang/test/Lower/OpenACC/acc-exit-data.f90
M flang/test/Lower/OpenACC/acc-host-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-private.f90
M flang/test/Lower/OpenACC/acc-reduction.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/FIR/target_cpu_features.f90
M flang/test/Lower/OpenMP/array-bounds.f90
M flang/test/Lower/OpenMP/target.f90
M flang/test/Lower/OpenMP/target_cpu_features.f90
A flang/test/Lower/derived-types-kind-params-2.f90
M libc/cmake/modules/LLVMLibCFlagRules.cmake
M libc/cmake/modules/LLVMLibCLibraryRules.cmake
M libc/cmake/modules/LLVMLibCObjectRules.cmake
M libc/cmake/modules/LLVMLibCTestRules.cmake
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/stdbit.rst
M libc/include/errno.h.def
M libc/include/llvm-libc-macros/stdbit-macros.h
M libc/spec/stdc.td
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
M libc/src/errno/CMakeLists.txt
M libc/src/errno/libc_errno.cpp
M libc/src/errno/libc_errno.h
M libc/src/stdbit/CMakeLists.txt
A libc/src/stdbit/stdc_leading_ones_uc.cpp
A libc/src/stdbit/stdc_leading_ones_uc.h
A libc/src/stdbit/stdc_leading_ones_ui.cpp
A libc/src/stdbit/stdc_leading_ones_ui.h
A libc/src/stdbit/stdc_leading_ones_ul.cpp
A libc/src/stdbit/stdc_leading_ones_ul.h
A libc/src/stdbit/stdc_leading_ones_ull.cpp
A libc/src/stdbit/stdc_leading_ones_ull.h
A libc/src/stdbit/stdc_leading_ones_us.cpp
A libc/src/stdbit/stdc_leading_ones_us.h
M libc/src/stdbit/stdc_leading_zeros_uc.cpp
M libc/src/stdbit/stdc_leading_zeros_uc.h
M libc/src/stdbit/stdc_leading_zeros_ul.cpp
M libc/src/stdbit/stdc_leading_zeros_ul.h
M libc/src/stdbit/stdc_leading_zeros_ull.cpp
M libc/src/stdbit/stdc_leading_zeros_ull.h
M libc/src/stdbit/stdc_leading_zeros_us.cpp
M libc/src/stdbit/stdc_leading_zeros_us.h
M libc/src/sys/epoll/linux/epoll_wait.cpp
M libc/test/include/stdbit_test.cpp
M libc/test/integration/startup/linux/tls_test.cpp
M libc/test/src/errno/errno_test.cpp
M libc/test/src/stdbit/CMakeLists.txt
A libc/test/src/stdbit/stdc_leading_ones_uc_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ui_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ul_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_ull_test.cpp
A libc/test/src/stdbit/stdc_leading_ones_us_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_uc_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ul_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_ull_test.cpp
M libc/test/src/stdbit/stdc_leading_zeros_us_test.cpp
M libc/test/src/stdio/remove_test.cpp
M libc/test/src/stdlib/StrtolTest.h
M libc/test/src/sys/mman/linux/madvise_test.cpp
M libc/test/src/sys/mman/linux/mlock_test.cpp
M libc/test/src/sys/mman/linux/mmap_test.cpp
M libc/test/src/sys/mman/linux/mprotect_test.cpp
M libc/test/src/sys/mman/linux/posix_madvise_test.cpp
M libc/test/src/sys/stat/mkdirat_test.cpp
M libc/test/src/time/asctime_r_test.cpp
M libc/test/src/time/asctime_test.cpp
M libc/test/src/unistd/CMakeLists.txt
M libc/test/src/unistd/access_test.cpp
M libc/test/src/unistd/chdir_test.cpp
M libc/test/src/unistd/dup2_test.cpp
M libc/test/src/unistd/dup3_test.cpp
M libc/test/src/unistd/dup_test.cpp
M libc/test/src/unistd/fchdir_test.cpp
M libc/test/src/unistd/ftruncate_test.cpp
M libc/test/src/unistd/isatty_test.cpp
M libc/test/src/unistd/link_test.cpp
M libc/test/src/unistd/linkat_test.cpp
M libc/test/src/unistd/lseek_test.cpp
M libc/test/src/unistd/pread_pwrite_test.cpp
M libc/test/src/unistd/read_write_test.cpp
M libc/test/src/unistd/readlink_test.cpp
M libc/test/src/unistd/readlinkat_test.cpp
M libc/test/src/unistd/rmdir_test.cpp
M libc/test/src/unistd/symlink_test.cpp
M libc/test/src/unistd/symlinkat_test.cpp
M libc/test/src/unistd/truncate_test.cpp
M libc/test/src/unistd/unlink_test.cpp
M libc/test/src/unistd/unlinkat_test.cpp
M libcxx/benchmarks/ContainerBenchmarks.h
M libcxx/benchmarks/vector_operations.bench.cpp
M libcxx/docs/FeatureTestMacroTable.rst
M libcxx/docs/ReleaseNotes/19.rst
M libcxx/docs/Status/Cxx23Papers.csv
M libcxx/docs/Status/Cxx2cIssues.csv
M libcxx/include/CMakeLists.txt
M libcxx/include/__format/formatter_bool.h
M libcxx/include/__format/formatter_integral.h
M libcxx/include/__memory/allocate_at_least.h
M libcxx/include/__memory/allocator_traits.h
M libcxx/include/__memory/temporary_buffer.h
M libcxx/include/__memory/uninitialized_algorithms.h
M libcxx/include/__memory/unique_ptr.h
A libcxx/include/__type_traits/is_trivially_relocatable.h
R libcxx/include/experimental/__memory
M libcxx/include/libcxx.imp
M libcxx/include/memory
M libcxx/include/module.modulemap.in
M libcxx/include/string
M libcxx/include/vector
M libcxx/include/version
M libcxx/modules/std/memory.inc
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
A libcxx/test/libcxx/type_traits/is_trivially_relocatable.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/memory.version.compile.pass.cpp
M libcxx/test/std/language.support/support.limits/support.limits.general/version.version.compile.pass.cpp
R libcxx/test/std/utilities/memory/allocator.traits/allocate_at_least.pass.cpp
A libcxx/test/std/utilities/memory/allocator.traits/allocator.traits.members/allocate_at_least.pass.cpp
M libcxx/test/support/count_new.h
M libcxx/utils/generate_feature_test_macro_components.py
M lld/ELF/Config.h
M lld/ELF/Driver.cpp
M lld/ELF/LTO.cpp
M lld/ELF/Options.td
M lld/ELF/Writer.cpp
M lld/MachO/Arch/ARM64.cpp
M lld/MachO/Arch/ARM64Common.h
M lld/MachO/Arch/ARM64_32.cpp
M lld/MachO/Arch/X86_64.cpp
M lld/MachO/ObjC.cpp
M lld/MachO/SyntheticSections.cpp
M lld/MachO/SyntheticSections.h
M lld/MachO/Target.h
M lld/MachO/Writer.cpp
M lld/test/ELF/linkerscript/insert-before.test
A lld/test/ELF/lto/basic-block-address-map.ll
M lld/test/MachO/objc-category-conflicts.s
M lld/test/MachO/objc-selrefs.s
M lld/test/MachO/x86-64-objc-stubs.s
M lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h
M lldb/source/Breakpoint/WatchpointResource.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFDebugInfo.h
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp
M lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.h
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDwo.h
A lldb/test/API/commands/target/debuginfo/TestDebugInfoSize.py
A lldb/test/API/commands/target/debuginfo/a.out-foo.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out-main.dwo.yaml
A lldb/test/API/commands/target/debuginfo/a.out.yaml
M lldb/test/API/functionalities/watchpoint/unaligned-large-watchpoint/TestUnalignedLargeWatchpoint.py
M lldb/test/Shell/SymbolFile/DWARF/x86/dwp-separate-debug-file.cpp
M lldb/unittests/Breakpoint/WatchpointAlgorithmsTests.cpp
M llvm/docs/AArch64SME.rst
M llvm/docs/CommandGuide/llvm-exegesis.rst
M llvm/docs/GettingInvolved.rst
M llvm/docs/GlobalISel/MIRPatterns.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/docs/SecurityTransparencyReports.rst
M llvm/docs/TableGen/ProgRef.rst
M llvm/include/llvm/Analysis/ScalarEvolution.h
M llvm/include/llvm/Analysis/TargetTransformInfo.h
M llvm/include/llvm/Analysis/TargetTransformInfoImpl.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h
M llvm/include/llvm/CodeGen/TargetInstrInfo.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/DebugInfo/DIContext.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFVerifier.h
M llvm/include/llvm/MC/MCDisassembler/MCDisassembler.h
M llvm/include/llvm/Object/ELFObjectFile.h
M llvm/include/llvm/Object/ELFTypes.h
M llvm/include/llvm/ObjectYAML/ELFYAML.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Analysis/MemoryProfileInfo.cpp
M llvm/lib/Analysis/ScalarEvolution.cpp
M llvm/lib/Analysis/TargetTransformInfo.cpp
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineFunction.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
M llvm/lib/CodeGen/StackSlotColoring.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetLoweringObjectFileImpl.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/DebugInfo/DWARF/DWARFContext.cpp
M llvm/lib/DebugInfo/DWARF/DWARFVerifier.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugInfoMetadata.cpp
M llvm/lib/IR/Function.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCContext.cpp
M llvm/lib/Object/ELF.cpp
M llvm/lib/ObjectYAML/ELFEmitter.cpp
M llvm/lib/ObjectYAML/ELFYAML.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp
M llvm/lib/Support/CommandLine.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Support/StringRef.cpp
M llvm/lib/TableGen/TGLexer.cpp
M llvm/lib/TableGen/TGLexer.h
M llvm/lib/TableGen/TGParser.cpp
M llvm/lib/TableGen/TGParser.h
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64PointerAuth.cpp
M llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
M llvm/lib/Target/AArch64/AArch64SchedA510.td
M llvm/lib/Target/AArch64/AArch64Subtarget.cpp
M llvm/lib/Target/AArch64/AArch64Subtarget.h
M llvm/lib/Target/AArch64/AArch64TargetMachine.cpp
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/SMEABIPass.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/R600TargetMachine.cpp
M llvm/lib/Target/AMDGPU/R600TargetMachine.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/ARC/ARCInstrInfo.cpp
M llvm/lib/Target/ARC/ARCInstrInfo.h
M llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
M llvm/lib/Target/ARM/ARMBaseInstrInfo.h
M llvm/lib/Target/AVR/AVRInstrInfo.cpp
M llvm/lib/Target/AVR/AVRInstrInfo.h
M llvm/lib/Target/CSKY/CSKYInstrInfo.cpp
M llvm/lib/Target/CSKY/CSKYInstrInfo.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiInstrInfo.cpp
M llvm/lib/Target/Lanai/LanaiInstrInfo.h
M llvm/lib/Target/Mips/Mips16InstrInfo.cpp
M llvm/lib/Target/Mips/Mips16InstrInfo.h
M llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
M llvm/lib/Target/Mips/MipsSEInstrInfo.h
M llvm/lib/Target/NVPTX/NVPTXInstrInfo.h
M llvm/lib/Target/PowerPC/PPCAsmPrinter.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
M llvm/lib/Target/PowerPC/PPCInstrInfo.h
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
A llvm/lib/Target/RISCV/RISCVInstrInfoZalasr.td
M llvm/lib/Target/RISCV/RISCVSystemOperands.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
A llvm/lib/Target/SPIRV/Analysis/CMakeLists.txt
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.cpp
A llvm/lib/Target/SPIRV/Analysis/SPIRVConvergenceRegionAnalysis.h
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRV.h
M llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.cpp
M llvm/lib/Target/Sparc/SparcInstrInfo.h
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZInstrInfo.h
M llvm/lib/Target/VE/VEInstrInfo.cpp
M llvm/lib/Target/VE/VEInstrInfo.h
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86FrameLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.cpp
M llvm/lib/Target/XCore/XCoreInstrInfo.h
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Utils/LoopUnrollRuntime.cpp
M llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
M llvm/test/Analysis/CostModel/RISCV/gep.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-max.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-min.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
A llvm/test/Analysis/ScalarEvolution/iv-poison.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-irtranslator-switch.ll
M llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/select-unreachable-blocks.mir
A llvm/test/CodeGen/AArch64/aarch64-za-clobber.ll
A llvm/test/CodeGen/AArch64/bswap.ll
M llvm/test/CodeGen/AArch64/callbr-asm-outputs-indirect-isel.ll
M llvm/test/CodeGen/AArch64/implicit-def-with-impdef-greedy-assert.mir
A llvm/test/CodeGen/AArch64/ptrauth-pseudo-instructions.mir
M llvm/test/CodeGen/AArch64/regalloc-last-chance-recolor-with-split.mir
M llvm/test/CodeGen/AArch64/select_fmf.ll
M llvm/test/CodeGen/AArch64/sme-disable-gisel-fisel.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call-remarks.ll
M llvm/test/CodeGen/AArch64/sme-lazy-save-call.ll
M llvm/test/CodeGen/AArch64/sme-new-za-function.ll
M llvm/test/CodeGen/AArch64/sme-shared-za-interface.ll
M llvm/test/CodeGen/AArch64/sme-zt0-state.ll
A llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir
A llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir
A llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir
A llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir
M llvm/test/CodeGen/AArch64/tail-dup-redundant-phi.mir
M llvm/test/CodeGen/AArch64/tbl-loops.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmax-legalization.ll
M llvm/test/CodeGen/AArch64/vecreduce-fmin-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-scalar-float-sop2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-unmerge-undef.mir
M llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
M llvm/test/CodeGen/AMDGPU/dagcombine-fma-crash.ll
M llvm/test/CodeGen/AMDGPU/insert-singleuse-vdst.mir
M llvm/test/CodeGen/AMDGPU/lower-control-flow-live-intervals.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-ignorable-exec-use.mir
M llvm/test/CodeGen/AMDGPU/machine-sink-temporal-divergence-swdev407790.ll
M llvm/test/CodeGen/AMDGPU/opt-exec-masking-pre-ra-update-liveness.mir
M llvm/test/CodeGen/AMDGPU/optimize-compare.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-mask-pre-ra-def-after-use.mir
M llvm/test/CodeGen/AMDGPU/optimize-exec-masking-pre-ra.mir
M llvm/test/CodeGen/AMDGPU/ra-inserted-scalar-instructions.mir
M llvm/test/CodeGen/AMDGPU/ran-out-of-sgprs-allocation-failure.mir
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/si-lower-control-flow.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/tuple-allocation-failure.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/ARM/cmpxchg.mir
M llvm/test/CodeGen/ARM/machine-outliner-noreturn.mir
M llvm/test/CodeGen/ARM/popcnt.ll
M llvm/test/CodeGen/MIR/X86/unreachable-block-print.mir
M llvm/test/CodeGen/Mips/GlobalISel/instruction-select/phi.mir
M llvm/test/CodeGen/Mips/GlobalISel/legalizer/jump_table_and_brjt.mir
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-char.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-double.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-float.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-int.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll
A llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll
M llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-short.ll
M llvm/test/CodeGen/PowerPC/branch_coalescing.mir
M llvm/test/CodeGen/PowerPC/machine-cse-rm-pre.mir
M llvm/test/CodeGen/PowerPC/nofpexcept.ll
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv32.mir
M llvm/test/CodeGen/RISCV/GlobalISel/legalizer/legalize-phi-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/calls.ll
M llvm/test/CodeGen/RISCV/float-select-verify.ll
R llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll
A llvm/test/CodeGen/RISCV/inline-asm-s-constraint-error.ll
A llvm/test/CodeGen/RISCV/inline-asm-s-constraint.ll
A llvm/test/CodeGen/RISCV/pr80052.mir
M llvm/test/CodeGen/RISCV/tail-calls.ll
M llvm/test/CodeGen/Thumb2/cmpxchg.mir
M llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir
M llvm/test/CodeGen/X86/GlobalISel/select-phi.mir
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avg.ll
M llvm/test/CodeGen/X86/avx-vperm2x128.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/avx2-vector-shifts.ll
M llvm/test/CodeGen/X86/avx512-arith.ll
M llvm/test/CodeGen/X86/avx512-intrinsics.ll
M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
M llvm/test/CodeGen/X86/avx512-shuffles/permute.ll
M llvm/test/CodeGen/X86/avx512bw-intrinsics.ll
M llvm/test/CodeGen/X86/avx512bwvl-intrinsics.ll
M llvm/test/CodeGen/X86/avx512vl-intrinsics-upgrade.ll
A llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll
A llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll
A llvm/test/CodeGen/X86/basic-block-address-map.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels-functions-sections.ll
R llvm/test/CodeGen/X86/basic-block-sections-labels.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-sext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool-zext.ll
M llvm/test/CodeGen/X86/bitcast-int-to-vector-bool.ll
M llvm/test/CodeGen/X86/branchfolding-landingpad-cfg.mir
M llvm/test/CodeGen/X86/broadcast-elm-cross-splat-vec.ll
M llvm/test/CodeGen/X86/coalescer-remat-with-undef-implicit-def-operand.mir
M llvm/test/CodeGen/X86/combine-add.ll
M llvm/test/CodeGen/X86/combine-addo.ll
M llvm/test/CodeGen/X86/combine-and.ll
M llvm/test/CodeGen/X86/combine-bitselect.ll
M llvm/test/CodeGen/X86/combine-mul.ll
M llvm/test/CodeGen/X86/combine-pavg.ll
M llvm/test/CodeGen/X86/combine-pmuldq.ll
M llvm/test/CodeGen/X86/combine-sdiv.ll
M llvm/test/CodeGen/X86/combine-shl.ll
M llvm/test/CodeGen/X86/combine-sra.ll
M llvm/test/CodeGen/X86/combine-srem.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-sub-usat.ll
M llvm/test/CodeGen/X86/combine-sub.ll
M llvm/test/CodeGen/X86/combine-udiv.ll
M llvm/test/CodeGen/X86/combine-urem.ll
M llvm/test/CodeGen/X86/cse-two-preds.mir
M llvm/test/CodeGen/X86/ctpop-combine.ll
A llvm/test/CodeGen/X86/ctpop-mask.ll
M llvm/test/CodeGen/X86/expand-vp-int-intrinsics.ll
M llvm/test/CodeGen/X86/extract-concat.ll
M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
M llvm/test/CodeGen/X86/i64-to-float.ll
M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
M llvm/test/CodeGen/X86/icmp-pow2-diff.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-shuffle.ll
M llvm/test/CodeGen/X86/known-signbits-vector.ll
M llvm/test/CodeGen/X86/masked_compressstore.ll
M llvm/test/CodeGen/X86/masked_expandload.ll
M llvm/test/CodeGen/X86/masked_load.ll
M llvm/test/CodeGen/X86/masked_store.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/masked_store_trunc_ssat.ll
M llvm/test/CodeGen/X86/masked_store_trunc_usat.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-128.ll
M llvm/test/CodeGen/X86/midpoint-int-vec-256.ll
M llvm/test/CodeGen/X86/min-legal-vector-width.ll
M llvm/test/CodeGen/X86/movmsk-cmp.ll
M llvm/test/CodeGen/X86/oddshuffles.ll
M llvm/test/CodeGen/X86/packus.ll
M llvm/test/CodeGen/X86/paddus.ll
M llvm/test/CodeGen/X86/pmul.ll
M llvm/test/CodeGen/X86/pmulh.ll
M llvm/test/CodeGen/X86/popcnt.ll
M llvm/test/CodeGen/X86/pr30821.mir
M llvm/test/CodeGen/X86/pr48215.ll
M llvm/test/CodeGen/X86/pr57340.ll
M llvm/test/CodeGen/X86/pr61964.ll
M llvm/test/CodeGen/X86/pr62014.ll
M llvm/test/CodeGen/X86/pr63507.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/pr77459.ll
M llvm/test/CodeGen/X86/prefer-avx256-mask-shuffle.ll
M llvm/test/CodeGen/X86/psubus.ll
M llvm/test/CodeGen/X86/sat-add.ll
M llvm/test/CodeGen/X86/setcc-non-simple-type.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-512.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/slow-pmulld.ll
M llvm/test/CodeGen/X86/srem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/srem-vector-lkk.ll
M llvm/test/CodeGen/X86/sse-domains.ll
M llvm/test/CodeGen/X86/statepoint-invoke-ra-remove-back-copies.mir
M llvm/test/CodeGen/X86/subvector-broadcast.ll
M llvm/test/CodeGen/X86/tail-dup-asm-goto.ll
A llvm/test/CodeGen/X86/unaligned_extract_from_vector_through_stack.ll
M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-splat.ll
M llvm/test/CodeGen/X86/urem-seteq-vec-tautological.ll
M llvm/test/CodeGen/X86/urem-vector-lkk.ll
M llvm/test/CodeGen/X86/usub_sat_vec.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vec_int_to_fp.ll
M llvm/test/CodeGen/X86/vec_setcc-2.ll
M llvm/test/CodeGen/X86/vec_setcc.ll
M llvm/test/CodeGen/X86/vec_shift6.ll
M llvm/test/CodeGen/X86/vec_smulo.ll
M llvm/test/CodeGen/X86/vec_umulo.ll
M llvm/test/CodeGen/X86/vector-bo-select.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-512.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-512.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
M llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-mul.ll
M llvm/test/CodeGen/X86/vector-pack-512.ll
M llvm/test/CodeGen/X86/vector-popcnt-128-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-popcnt-256-ult-ugt.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-reduce-ctpop.ll
M llvm/test/CodeGen/X86/vector-reduce-xor-bool.ll
M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-sext.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-512.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v4.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bw.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512bwvl.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512f.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining-avx512vbmi.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
M llvm/test/CodeGen/X86/vector-trunc-math.ll
M llvm/test/CodeGen/X86/vector-trunc-packus.ll
M llvm/test/CodeGen/X86/vector-trunc-ssat.ll
M llvm/test/CodeGen/X86/vector-trunc-usat.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vector-unsigned-cmp.ll
M llvm/test/CodeGen/X86/vector-zext.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-pcmp.ll
M llvm/test/CodeGen/X86/vselect.ll
M llvm/test/CodeGen/X86/widen_arith-5.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/DebugInfo/X86/skeleton-unit-verify.s
M llvm/test/DebugInfo/dwarfdump-accel.test
M llvm/test/MC/RISCV/attribute-arch.s
A llvm/test/MC/RISCV/rv32zalasr-invalid.s
A llvm/test/MC/RISCV/rv32zalasr-valid.s
A llvm/test/MC/RISCV/rv64zalasr-invalid.s
A llvm/test/MC/RISCV/rv64zalasr-valid.s
M llvm/test/MC/RISCV/supervisor-csr-names.s
A llvm/test/TableGen/GlobalISelCombinerEmitter/Inputs/test-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/builtin-pattern-errors.td
A llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/pattern-errors.td
M llvm/test/TableGen/GlobalISelCombinerEmitter/pattern-parsing.td
A llvm/test/TableGen/deftype.td
M llvm/test/TableGen/lit.local.cfg
M llvm/test/Transforms/IndVarSimplify/X86/inner-loop-by-latch-cond.ll
M llvm/test/Transforms/IndVarSimplify/iv-poison.ll
A llvm/test/Transforms/IndVarSimplify/pr79861.ll
M llvm/test/Transforms/Inline/AArch64/sme-pstateza-attrs.ll
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
M llvm/test/Transforms/LoopStrengthReduce/lsr-term-fold.ll
A llvm/test/Transforms/LoopUnroll/runtime-i128.ll
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.exe
A llvm/test/Transforms/PGOProfile/Inputs/memprof_loop_unroll.memprofraw
M llvm/test/Transforms/PGOProfile/Inputs/update_memprof_inputs.sh
A llvm/test/Transforms/PGOProfile/memprof_loop_unroll.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-vectorized.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-indices.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-loads-with-external-use-ptr.ll
A llvm/test/Transforms/SLPVectorizer/RISCV/strided-unsupported-type.ll
M llvm/test/Transforms/Util/add-TLI-mappings.ll
M llvm/test/Verifier/sme-attributes.ll
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.c
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.o
A llvm/test/tools/llvm-cov/Inputs/mcdc-macro.proftext
A llvm/test/tools/llvm-cov/mcdc-macro.test
M llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_attr_file_indexes_no_files.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_file_encoding.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_overlapping_cu_ranges.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_parent_zero_length.yaml
M llvm/test/tools/llvm-dwarfdump/X86/verify_split_cu.s
M llvm/test/tools/llvm-mca/AArch64/Cortex/A510-basic-instructions.s
A llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-cov5.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx11.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx12.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-gfx90a.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-sgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-vgpr.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx10.s
M llvm/test/tools/llvm-objdump/ELF/AMDGPU/kd-zeroed-gfx9.s
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-disassemble-symbolize-operands.yaml
M llvm/test/tools/llvm-objdump/X86/elf-bbaddrmap-symbolize-relocatable.yaml
M llvm/test/tools/llvm-objdump/X86/elf-pgoanalysismap.yaml
A llvm/test/tools/llvm-readobj/ELF/bb-addr-map-pgo-analysis-map.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map-relocatable.test
M llvm/test/tools/llvm-readobj/ELF/bb-addr-map.test
M llvm/test/tools/llvm-reduce/custom-delta-passes.ll
M llvm/test/tools/llvm-reduce/do-not-remove-terminator.ll
M llvm/test/tools/llvm-reduce/fail-file-open.test
M llvm/test/tools/llvm-reduce/granularity-level.ll
M llvm/test/tools/llvm-reduce/no-replace-intrinsic-callee-with-undef.ll
M llvm/test/tools/llvm-reduce/operands-skip-parallel.ll
M llvm/test/tools/llvm-reduce/operands-skip.ll
M llvm/test/tools/llvm-reduce/operands-to-args.ll
M llvm/test/tools/llvm-reduce/oracle-count.ll
M llvm/test/tools/llvm-reduce/parallel-workitem-kill.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress-wrong-function.ll
M llvm/test/tools/llvm-reduce/reduce-functions-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-alias.ll
M llvm/test/tools/llvm-reduce/remove-all-of-multiple-args.ll
M llvm/test/tools/llvm-reduce/remove-args-2.ll
M llvm/test/tools/llvm-reduce/remove-args-fn-passed-through-call.ll
M llvm/test/tools/llvm-reduce/remove-args-from-declaration.ll
M llvm/test/tools/llvm-reduce/remove-args-used-by-ret.ll
M llvm/test/tools/llvm-reduce/remove-args.ll
M llvm/test/tools/llvm-reduce/remove-attributes-from-intrinsic-like-functions.ll
M llvm/test/tools/llvm-reduce/remove-dp-values.ll
M llvm/test/tools/llvm-reduce/remove-funcs.ll
M llvm/test/tools/llvm-reduce/remove-function-arguments-of-funcs-used-in-blockaddress.ll
M llvm/test/tools/llvm-reduce/remove-function-bodies-comdat.ll
M llvm/test/tools/llvm-reduce/remove-global-variable-attributes.ll
M llvm/test/tools/llvm-reduce/remove-metadata-args.ll
M llvm/test/tools/llvm-reduce/remove-multiple-use-of-global-vars-in-same-instruction.ll
M llvm/test/tools/llvm-reduce/remove-operand-bundles.ll
M llvm/test/tools/llvm-reduce/remove-single-arg.ll
M llvm/test/tools/llvm-reduce/remove-unused-declarations.ll
M llvm/test/tools/llvm-reduce/run-ir-passes.ll
M llvm/test/tools/obj2yaml/ELF/bb-addr-map.yaml
M llvm/test/tools/yaml2obj/ELF/bb-addr-map.yaml
M llvm/tools/llvm-dwarfdump/llvm-dwarfdump.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkResult.h
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.h
M llvm/tools/llvm-exegesis/lib/ResultAggregator.cpp
M llvm/tools/llvm-exegesis/llvm-exegesis.cpp
M llvm/tools/llvm-objdump/llvm-objdump.cpp
M llvm/tools/llvm-readobj/ELFDumper.cpp
M llvm/tools/obj2yaml/elf2yaml.cpp
M llvm/unittests/Object/ELFObjectFileTest.cpp
M llvm/unittests/Object/ELFTypesTest.cpp
M llvm/unittests/ProfileData/CoverageMappingTest.cpp
M llvm/unittests/Support/RISCVISAInfoTest.cpp
M llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
A llvm/unittests/Target/SPIRV/CMakeLists.txt
A llvm/unittests/Target/SPIRV/SPIRVConvergenceRegionAnalysisTests.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/unittests/tools/llvm-exegesis/Mips/BenchmarkResultTest.cpp
M llvm/unittests/tools/llvm-exegesis/ResultAggregatorTest.cpp
M llvm/unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp
M llvm/utils/TableGen/CodeGenInstruction.cpp
M llvm/utils/TableGen/GlobalISel/Patterns.cpp
M llvm/utils/TableGen/GlobalISel/Patterns.h
M llvm/utils/TableGen/GlobalISelCombinerEmitter.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
M llvm/utils/git/github-automation.py
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
A mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitC.h
A mlir/include/mlir/Conversion/FuncToEmitC/FuncToEmitCPass.h
M mlir/include/mlir/Conversion/Passes.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Conversion/SCFToEmitC/SCFToEmitC.h
M mlir/include/mlir/Dialect/ArmSME/Transforms/Passes.td
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.h
M mlir/include/mlir/Dialect/EmitC/IR/EmitC.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.h
M mlir/include/mlir/Dialect/SparseTensor/Transforms/Passes.td
M mlir/include/mlir/Dialect/Vector/IR/VectorOps.td
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/OperationSupport.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.cpp
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/CMakeLists.txt
A mlir/lib/Conversion/FuncToEmitC/CMakeLists.txt
A mlir/lib/Conversion/FuncToEmitC/FuncToEmitC.cpp
A mlir/lib/Conversion/FuncToEmitC/FuncToEmitCPass.cpp
M mlir/lib/Conversion/GPUToROCDL/LowerGpuOpsToROCDLOps.cpp
M mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp
M mlir/lib/Conversion/TosaToTensor/TosaToTensor.cpp
M mlir/lib/Dialect/ArmSME/Transforms/VectorLegalization.cpp
M mlir/lib/Dialect/EmitC/IR/CMakeLists.txt
M mlir/lib/Dialect/EmitC/IR/EmitC.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/SCF/Transforms/ParallelLoopFusion.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/CMakeLists.txt
A mlir/lib/Dialect/SparseTensor/Transforms/SparseAssembler.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorPasses.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/CodegenEnv.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.h
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorLevel.h
M mlir/lib/Dialect/Tensor/Transforms/ConcatOpPatterns.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/OperationSupport.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Target/Cpp/TranslateToCpp.cpp
M mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
A mlir/test/Conversion/FuncToEmitC/func-to-emitc.mlir
M mlir/test/Conversion/MemRefToSPIRV/memref-to-spirv.mlir
M mlir/test/Dialect/ArmSME/enable-arm-za.mlir
M mlir/test/Dialect/ArmSME/vector-legalization.mlir
M mlir/test/Dialect/Bufferization/Transforms/OwnershipBasedBufferDeallocation/dealloc-other.mlir
M mlir/test/Dialect/EmitC/invalid_ops.mlir
M mlir/test/Dialect/EmitC/ops.mlir
M mlir/test/Dialect/MemRef/canonicalize.mlir
M mlir/test/Dialect/MemRef/fold-memref-alias-ops.mlir
M mlir/test/Dialect/MemRef/invalid.mlir
M mlir/test/Dialect/SCF/parallel-loop-fusion.mlir
A mlir/test/Dialect/SparseTensor/external.mlir
M mlir/test/Dialect/SparseTensor/sparse_conv_2d_slice_based.mlir
M mlir/test/Dialect/SparseTensor/sparse_reinterpret_map.mlir
A mlir/test/Target/Cpp/func.mlir
M mlir/test/Target/LLVMIR/Import/function-attributes.ll
A mlir/test/Target/LLVMIR/llvmir-le-specific.mlir
M mlir/test/Target/LLVMIR/llvmir.mlir
M mlir/test/Target/LLVMIR/omptarget-parallel-llvm.mlir
A mlir/test/Target/LLVMIR/omptarget-target-cpu-features.mlir
M mlir/test/Transforms/test-legalizer-full.mlir
M mlir/test/Transforms/test-strict-pattern-driver.mlir
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/python/dialects/memref.py
M openmp/cmake/HandleOpenMPOptions.cmake
M openmp/libomptarget/plugins-nextgen/CMakeLists.txt
M openmp/libomptarget/plugins-nextgen/cuda/src/rtl.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdio/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/sys/epoll/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/unistd/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
remove RISC-V S test
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/8ce25b59ac48...3fac3a94b7ae
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