[all-commits] [llvm/llvm-project] 109436: [AArch64][GlobalISel] Legalize BSWAP for Vector Ty...

[chuongg3 via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 10943695f76f513503162026669e84cb72275e84
      https://github.com/llvm/llvm-project/commit/10943695f76f513503162026669e84cb72275e84
  Author: chuongg3 <chuong.goh at arm.com>
  Date:   2024-02-02 (Fri, 02 Feb 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
    M llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
    M llvm/test/CodeGen/AArch64/GlobalISel/select-bswap.mir
    M llvm/test/CodeGen/AArch64/bswap.ll

  Log Message:
  -----------
  [AArch64][GlobalISel] Legalize BSWAP for Vector Types (#80036)

Add support of i16 vector operation for BSWAP and change to TableGen to
select instructions

Handle vector types that are smaller/larger than legal for BSWAP