[all-commits] [llvm/llvm-project] 5cf0fb: [StackSlotColoring] Ignore non-spill objects in Re...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
      https://github.com/llvm/llvm-project/commit/5cf0fb4317f4f9a5e48d8dc1f861d63b5e0df11c
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-02-01 (Thu, 01 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/StackSlotColoring.cpp
    A llvm/test/CodeGen/RISCV/pr80052.mir
    M llvm/test/CodeGen/X86/pr30821.mir

  Log Message:
  -----------
  [StackSlotColoring] Ignore non-spill objects in RemoveDeadStores. (#80242)

The stack slot coloring pass is concerned with optimizing spill
slots. If any change is a pass is made over the function to remove
stack stores that use the same register and stack slot as an
immediately preceding load.
    
The register check is too simple for constant registers like AArch64
and RISC-V's zero register. This register can be used as the result
of a load if we want to discard the result, but still have the memory
access performed. Like for a volatile or atomic load.
    
If the code sees a load from the zero register followed by a store
of the zero register at the same stack slot, the pass mistakenly
believes the store isn't needed.
    
Since the main stack coloring optimization is only concerned with
spill slots, it seems reasonable that RemoveDeadStores should
only be concerned with spills. Since we never generate a reload of
x0, this avoids the issue seen by RISC-V.
    
Test case concept is adapted from pr30821.mir from X86. That test
had to be updated to mark the stack slot as a spill slot.
    
Fixes #80052.