[all-commits] [llvm/llvm-project] 10c2d5: [RISCV][GISel] RegBank select and instruction sele...

[Jiahan Xie via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 10c2d5ff7c6de8096c8f4c4621612970940f6dd3
      https://github.com/llvm/llvm-project/commit/10c2d5ff7c6de8096c8f4c4621612970940f6dd3
  Author: Jiahan Xie <88367305+jiahanxie353 at users.noreply.github.com>
  Date:   2024-02-01 (Thu, 01 Feb 2024)

  Changed paths:
    M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
    M llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/add.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rvv/sub.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/add.mir
    A llvm/test/CodeGen/RISCV/GlobalISel/regbankselect/rvv/sub.mir

  Log Message:
  -----------
  [RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB (#74114)

RegisterBank Selection for scalable vector G_ADD and G_SUB by creating
new mappings for different types of vector register banks.
Then implement Instruction Selection for the same operations by choosing
the correct RISC-V vector register class.