[all-commits] [llvm/llvm-project] 560531: [RISCV] Add test to showcase miscompile from #79072

[Luke Lau via All-commits]

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 5605312fc5742c1e9825bfa4deafe29509795e78
      https://github.com/llvm/llvm-project/commit/5605312fc5742c1e9825bfa4deafe29509795e78
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll

  Log Message:
  -----------
  [RISCV] Add test to showcase miscompile from #79072


  Commit: aca7586ac9cef896a0ab47bd1ccfbbcf9ec50e61
      https://github.com/llvm/llvm-project/commit/aca7586ac9cef896a0ab47bd1ccfbbcf9ec50e61
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll

  Log Message:
  -----------
  [RISCV] Fix M1 shuffle on wrong SrcVec in lowerShuffleViaVRegSplitting

This fixes a miscompile from #79072 where we were taking the wrong SrcVec to do
the M1 shuffle. E.g. if the SrcVecIdx was 2 and we had 2 VRegsPerSrc, we ended
up taking it from V1 instead of V2.


Compare: https://github.com/llvm/llvm-project/compare/e502141a420a...aca7586ac9ce