[all-commits] [llvm/llvm-project] cf401f: [RISCV] Use Zacas for AtomicRMWInst::Nand i32 and ...

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: cf401f72e1b5aa6be0719ab45c95c10ea06bec9a
      https://github.com/llvm/llvm-project/commit/cf401f72e1b5aa6be0719ab45c95c10ea06bec9a
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/atomic-rmw.ll
    M llvm/test/CodeGen/RISCV/atomic-signext.ll

  Log Message:
  -----------
  [RISCV] Use Zacas for AtomicRMWInst::Nand i32 and XLen. (#80119)

We don't have an AMO instruction for Nand, so with the A extension we
use an LR/SC loop. If we have Zacas we can use a CAS loop instead.

According to the Zacas spec, a CAS loop scales to highly parallel
systems better than LR/SC.