[all-commits] [llvm/llvm-project] 5d7d89: [AArch64] Use add_and_or_is_add for CSINC (#79552)

[David Green via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5d7d89de31ad017a91204988cacc2f0ff69d47da
      https://github.com/llvm/llvm-project/commit/5d7d89de31ad017a91204988cacc2f0ff69d47da
  Author: David Green <david.green at arm.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AArch64/AArch64InstrInfo.td
    M llvm/test/CodeGen/AArch64/arm64-csel.ll

  Log Message:
  -----------
  [AArch64] Use add_and_or_is_add for CSINC (#79552)

Adds or add-like-or's of 1 can both be turned into csinc, which can help
fold more instructions into a csinc.