[all-commits] [llvm/llvm-project] c2c650: [AMDGPU] Stop combining arbitrary offsets into PAL...

[Jay Foad via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: c2c650f62e15ca2444e1a938fdf869c84535ef16
      https://github.com/llvm/llvm-project/commit/c2c650f62e15ca2444e1a938fdf869c84535ef16
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2024-01-31 (Wed, 31 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/global-constant.ll
    M llvm/test/CodeGen/AMDGPU/llvm.memcpy.ll
    M llvm/test/CodeGen/AMDGPU/rel32.ll

  Log Message:
  -----------
  [AMDGPU] Stop combining arbitrary offsets into PAL relocs (#80034)

PAL uses ELF REL (not RELA) relocations which can only store a 32-bit
addend in the instruction, even for reloc types like R_AMDGPU_ABS32_HI
which require the upper 32 bits of a 64-bit address calculation to be
correct. This means that it is not safe to fold an arbitrary offset into
a GlobalAddressSDNode, so stop doing that.

In practice this is mostly a problem for small negative offsets which do
not work as expected because PAL treats the 32-bit addend as unsigned.