[all-commits] [llvm/llvm-project] 6a21e0: [AMDGPU][AsmParser] Allow `v_writelane_b32` to use...

[Shilei Tian via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 6a21e00e397648141ed36aae4bd958efa09908f3
      https://github.com/llvm/llvm-project/commit/6a21e00e397648141ed36aae4bd958efa09908f3
  Author: Shilei Tian <i at tianshilei.me>
  Date:   2024-01-30 (Tue, 30 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
    A llvm/test/MC/AMDGPU/writelane_m0.s
    A llvm/test/MachineVerifier/writelane_m0.mir

  Log Message:
  -----------
  [AMDGPU][AsmParser] Allow `v_writelane_b32` to use SGPR and M0 as source operands at the same time (#78827)

Currently the asm parser takes `v_writelane_b32 v1, s13, m0` as illegal
instruction for pre-gfx11 because it uses two constant buses while the
hardware
can only allow one. However, based on the comment of
`AMDGPUInstructionSelector::selectWritelane`,
it is allowed to have M0 as lane selector and a SGPR used as SRC0
because the
lane selector doesn't count as a use of constant bus. In fact, codegen
can already
generate this form, but this inconsistency is not exposed because the
validation
of constant bus limitation only happens when paring an assembly but we
don't have
a test case when both SGPR and M0 used as source operands for the
instruction.