[all-commits] [llvm/llvm-project] d09082: [RISCV] Relax march string order constraint (#78120)

[Piyou Chen via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d09082f6fd517759e5c0874a2e73bddd550de299
      https://github.com/llvm/llvm-project/commit/d09082f6fd517759e5c0874a2e73bddd550de299
  Author: Piyou Chen <piyou.chen at sifive.com>
  Date:   2024-01-30 (Tue, 30 Jan 2024)

  Changed paths:
    M clang/test/Driver/riscv-arch.c
    M llvm/lib/Support/RISCVISAInfo.cpp
    M llvm/unittests/Support/RISCVISAInfoTest.cpp

  Log Message:
  -----------
  [RISCV] Relax march string order constraint (#78120)

Follow
https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/14 by
dropping the order requirement of `-march`.

1. single-letter extension can be arbitrary order
    - march=rv32iamdf 
2. single-letter extension and multi-letter extension can be mixed
    - march=rv32i_zihintntl_m_a_f_d_svinval
3. multi-letter extension need seperate the following extension by
underscore, otherwise it will be intreprete as one extension.
    - march=rv32i_zbam -> i,zbam
    - march=rv32i_zba_m -> i,zba,m