[all-commits] [llvm/llvm-project] a69410: [mlir][Vector] Add patterns for efficient i4 -> i8...

[Diego Caballero via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a694104022cff5e8b38321f99fd0bc34d8847f5d
      https://github.com/llvm/llvm-project/commit/a694104022cff5e8b38321f99fd0bc34d8847f5d
  Author: Diego Caballero <diegocaballero at google.com>
  Date:   2024-01-29 (Mon, 29 Jan 2024)

  Changed paths:
    M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
    M mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir

  Log Message:
  -----------
  [mlir][Vector] Add patterns for efficient i4 -> i8 conversion emulation (#79494)

This PR adds new patterns to improve the generated vector code for the emulation of any conversion that have to go through an i4 -> i8 type extension (only signed extensions are supported for now). This will impact any i4 -> i8/i16/i32/i64 signed extensions as well as sitofp i4 -> f8/f16/f32/f64.

The asm code generated for the supported cases is significantly better after this PR for both x86 and aarch64.