[all-commits] [llvm/llvm-project] 046144: [RISCV][ISel] Add ISel support for experimental Zi...

[Jivan Hakobyan via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 0461448313800b47189cc9024a0f2a9f75b44470
      https://github.com/llvm/llvm-project/commit/0461448313800b47189cc9024a0f2a9f75b44470
  Author: Jivan Hakobyan <jivanhakobyan9 at gmail.com>
  Date:   2024-01-29 (Mon, 29 Jan 2024)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsRISCV.td
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoZimop.td
    A llvm/test/CodeGen/RISCV/rv32zimop-intrinsic.ll
    A llvm/test/CodeGen/RISCV/rv64zimop-intrinsic.ll

  Log Message:
  -----------
  [RISCV][ISel] Add ISel support for experimental Zimop extension (#77089)

This implements ISel support for mopr[0-31] and moprr[0-7] instructions
for 32 and 64 bits

---------

Co-authored-by: ln8-8 <lyut.nersisyan at gmail.com>