[all-commits] [llvm/llvm-project] 4c8cf4: [AMDGPU] New llvm.amdgcn.wave.id intrinsic (#79325)

[Jay Foad via All-commits]

  Branch: refs/heads/release/18.x
  Home:   https://github.com/llvm/llvm-project
  Commit: 4c8cf4a1c29da834f1999a1c56c7e637c6886825
      https://github.com/llvm/llvm-project/commit/4c8cf4a1c29da834f1999a1c56c7e637c6886825
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2024-01-29 (Mon, 29 Jan 2024)

  Changed paths:
    M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.h
    A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll

  Log Message:
  -----------
  [AMDGPU] New llvm.amdgcn.wave.id intrinsic (#79325)

This is only valid on targets with architected SGPRs.


  Commit: 824a3e5dec3aabc91428f009c1f439a75f577469
      https://github.com/llvm/llvm-project/commit/824a3e5dec3aabc91428f009c1f439a75f577469
  Author: Jay Foad <jay.foad at amd.com>
  Date:   2024-01-29 (Mon, 29 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    M llvm/lib/Target/AMDGPU/SIISelLowering.cpp

  Log Message:
  -----------
  [AMDGPU] Do not bother adding reserved registers to liveins (#79436)

Tweak the implementation of llvm.amdgcn.wave.id to not add TTMP8 to the
function liveins.


Compare: https://github.com/llvm/llvm-project/compare/b73cd5ec7147...824a3e5dec3a