[all-commits] [llvm/llvm-project] 179ade: [clang-format] Fix an issue reported by static ana...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Mon Jan 29 10:32:46 PST 2024
Branch: refs/heads/users/MaskRay/spr/llvm-cov-simplify-and-optimize-mcdc-computation
Home: https://github.com/llvm/llvm-project
Commit: 179ade6a6d78533179205640dd161bf179daa9ee
https://github.com/llvm/llvm-project/commit/179ade6a6d78533179205640dd161bf179daa9ee
Author: Owen Pan <owenpiano at gmail.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M clang/lib/Format/WhitespaceManager.cpp
Log Message:
-----------
[clang-format] Fix an issue reported by static analyzer
Fixes #79685.
Commit: c70d3874e95ba24d7f1f9e69102db8916d9c41f1
https://github.com/llvm/llvm-project/commit/c70d3874e95ba24d7f1f9e69102db8916d9c41f1
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M llvm/include/llvm/ADT/ArrayRef.h
Log Message:
-----------
[ADT] Remove makeArrayRef and makeMutableArrayRef (#79719)
These have been deprecated since:
commit 36117cc46388d677359f1180bd536f80d0c5fe97
Author: serge-sans-paille <sguelton at mozilla.com>
Date: Tue Jan 10 11:49:15 2023 +0100
commit c4b39cd09c4eeef2b3e3d32cb674f92c17eeb517
Author: Joe Loser <joeloser at fastmail.com>
Date: Mon Jan 16 14:52:16 2023 -0700
Commit: 5f4c89edd0ade97ab3e2d6df5375974f4b975d58
https://github.com/llvm/llvm-project/commit/5f4c89edd0ade97ab3e2d6df5375974f4b975d58
Author: Rageking8 <106309953+Rageking8 at users.noreply.github.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M clang/test/Analysis/additive-op-on-sym-int-expr.c
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTypeUtilities.h
M llvm/test/MC/AArch64/neon-diagnostics.s
M llvm/test/MC/AArch64/neon-scalar-shift-imm.s
M llvm/test/MC/Disassembler/AArch64/neon-instructions.txt
M mlir/docs/Dialects/Linalg/OpDSL.md
M mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py
Log Message:
-----------
Fix unsigned typos (#76670)
Commit: 8f8cab6b7849944e5d1a9ddb773d0be851da6503
https://github.com/llvm/llvm-project/commit/8f8cab6b7849944e5d1a9ddb773d0be851da6503
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[llvm] Use Instruction::hasMetadata (NFC)
Commit: d6ad67df6bdd1e49f4f57ae8dfa1b05daf081c6e
https://github.com/llvm/llvm-project/commit/d6ad67df6bdd1e49f4f57ae8dfa1b05daf081c6e
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
Log Message:
-----------
[clang-tidy] Use StringRef::consume_back (NFC)
Commit: 687136e7cd2ba897dc1f3688af6db58549ab95f2
https://github.com/llvm/llvm-project/commit/687136e7cd2ba897dc1f3688af6db58549ab95f2
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
Log Message:
-----------
[Transforms] Use a range-based for loop (NFC)
Commit: 7d7f358cee659564358904584a871facfd5f765b
https://github.com/llvm/llvm-project/commit/7d7f358cee659564358904584a871facfd5f765b
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-27 (Sat, 27 Jan 2024)
Changed paths:
M llvm/tools/llvm-profdata/llvm-profdata.cpp
Log Message:
-----------
[llvm-profdata] Simplify a string equality comparison (NFC)
Commit: 5abbb7b5d038c62d3dc37ac8a2d7d57deebac0c7
https://github.com/llvm/llvm-project/commit/5abbb7b5d038c62d3dc37ac8a2d7d57deebac0c7
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
Log Message:
-----------
[X86][test] Update CHECK prefixes in CodeGen/X86/vector-interleaved-load-*.ll to suppress warnings
Suppress warnings like
WARNING: Prefix AVX had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX1 had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX2 had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX2-ONLY had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX512 had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX512F had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX512F-ONLY had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX512-FAST had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
WARNING: Prefix AVX512DQ-ONLY had conflicting output from different RUN lines for all functions in test vector-interleaved-load-i16-stride-7.ll
Commit: 23b233c8adad5b81e185e50d04356fab64c2f870
https://github.com/llvm/llvm-project/commit/23b233c8adad5b81e185e50d04356fab64c2f870
Author: Andrew Schenk <154034018+schenka0 at users.noreply.github.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang-tools-extra/clangd/SourceCode.cpp
M clang-tools-extra/clangd/unittests/SourceCodeTests.cpp
Log Message:
-----------
[clangd] Fix isSpelledInSource crash on invalid FileID (#76668)
This fixes the crash reported in #76667 and adds an initial unit test
for isSpelledInSource().
Note that in that issue there was still some underlying corrupted AST,
but this at least makes isSpelledInSource() robust to it.
---------
Co-authored-by: Younan Zhang <zyn7109 at gmail.com>
Commit: d14c8f06ea1dceba1ec6c0823e55e3a142a48f46
https://github.com/llvm/llvm-project/commit/d14c8f06ea1dceba1ec6c0823e55e3a142a48f46
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] getFauxShuffleMask - don't allow undefs in constant for AND/ANDNP shuffle masks
Early out from getTargetConstantBitsFromNode call instead of just returning if an undef was found.
Commit: 1b37e8087e1e1ecf5aadd8da536ee17dc21832e2
https://github.com/llvm/llvm-project/commit/1b37e8087e1e1ecf5aadd8da536ee17dc21832e2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlan.cpp
Log Message:
-----------
[VPlan] use getVPValueOrAddLiveIn in VPlan::duplicate.
Instead of creating live-ins manually, use getOrAddLiveIn which
automatically takes care of adding them to VPLiveInsToFree. Also use it
to create the VPValue for the trip-count. This fixes a leak:
https://lab.llvm.org/buildbot/#/builders/168/builds/18308/steps/10/logs/stdio
Commit: b13d5df84c2f3888e6775ce207b21e17bbf5cd1d
https://github.com/llvm/llvm-project/commit/b13d5df84c2f3888e6775ce207b21e17bbf5cd1d
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
Log Message:
-----------
[DAG] ComputeKnownBits - use KnownBits::usub_sat instead of a custom variant
KnownBits::usub_sat is already exhaustively tested in the unit tests
Commit: 70e22537549c65d69ae97a311d821c6459b32289
https://github.com/llvm/llvm-project/commit/70e22537549c65d69ae97a311d821c6459b32289
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang/lib/AST/Interp/Context.cpp
Log Message:
-----------
[clang][Interp][NFC] Remove unnecessary braces
Commit: a2f4c80ea8792f6d4c27e4cf9967400ac65d9ec6
https://github.com/llvm/llvm-project/commit/a2f4c80ea8792f6d4c27e4cf9967400ac65d9ec6
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] getTargetConstantBitsFromNode - add explicit support for whole/partial undef elements to all constant folding uses.
A NFC step before I start restricting the use of undef elements in getTargetConstantBitsFromNode
Commit: 74e5418ae6630d298982f8014c184b01bebcf455
https://github.com/llvm/llvm-project/commit/74e5418ae6630d298982f8014c184b01bebcf455
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] Fix typo in assertion message. NFC.
We are NOT expecting undefs in AND/ANDNP faux shuffle masks
Commit: 354548621fdbaead4832361d26922b91488e401a
https://github.com/llvm/llvm-project/commit/354548621fdbaead4832361d26922b91488e401a
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][Interp][NFC] Make some variables in the opcode emitter const
Commit: 916bd7d3bb42627f52e2f8ed2f87e08db4960a72
https://github.com/llvm/llvm-project/commit/916bd7d3bb42627f52e2f8ed2f87e08db4960a72
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
Log Message:
-----------
[clang][Interp][NFC] Remove Root record from opcode emitter
It's only used once and only for its name, so replace that with
a string literal.
Commit: f297d0bc6d5c9ca8db704b65fd0946ef2e9610ff
https://github.com/llvm/llvm-project/commit/f297d0bc6d5c9ca8db704b65fd0946ef2e9610ff
Author: David Green <david.green at arm.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AArch64/fcmp.ll
Log Message:
-----------
[AArch64][GlobalISel] More FCmp legalization. (#78734)
This fills out the fcmp handling to be more like the other instructions,
adding better support for fp16 and some larger vectors.
Select of f16 values is still not handled optimally in places as the
select is only legal for s32 values, not s16. This would be correct for
integer but not necessarily for fp. It is as if we need to do
legalization -> regbankselect -> extra legaliation -> selection.
Commit: 720ade25044536aed7372554e1818eac9536dc3a
https://github.com/llvm/llvm-project/commit/720ade25044536aed7372554e1818eac9536dc3a
Author: Sirui Mu <msrlancern at gmail.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M libc/cmake/modules/LLVMLibCArchitectures.cmake
Log Message:
-----------
[libc][CMake] fix CMake configure issues on openSUSE (#79751)
Commit: 60dbb2cec1bbf65aacf6752a59b0666a23aaa3ae
https://github.com/llvm/llvm-project/commit/60dbb2cec1bbf65aacf6752a59b0666a23aaa3ae
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
Log Message:
-----------
[X86][test] Update CHECK prefixes in CodeGen/X86/vector-interleaved-store-*.ll to suppress warnings
Suppress warnings like
WARNING: Prefix AVX had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX1 had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX2 had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX2-ONLY had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX512 had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX512F had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX512F-ONLY had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX512-FAST had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
WARNING: Prefix AVX512DQ-ONLY had conflicting output from different RUN lines for all functions in test vector-interleaved-store-i16-stride-7.ll
Commit: 6d7c8a6e062a237f1a23e7753c6737f5796e5188
https://github.com/llvm/llvm-project/commit/6d7c8a6e062a237f1a23e7753c6737f5796e5188
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
Log Message:
-----------
[X86][test] Update failed tests in 60dbb2cec1bbf65aacf6752a59b0666a23aaa3ae after rebase
Commit: 915c3d9e5a2d1314afe64cd6116a3b6c9809ec90
https://github.com/llvm/llvm-project/commit/915c3d9e5a2d1314afe64cd6116a3b6c9809ec90
Author: David Green <david.green at arm.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/test/CodeGen/AArch64/arm64-addrmode.ll
M llvm/test/CodeGen/AArch64/large-offset-ldr-merge.mir
Log Message:
-----------
Revert "[AArch64] merge index address with large offset into base address"
This reverts commit 32878c2065c8005b3ea30c79e16dfd7eed55d645 due to #79756 and #76202.
Commit: 72fd10adcbf8194a08141e38a95e11f4f1a8d7c2
https://github.com/llvm/llvm-project/commit/72fd10adcbf8194a08141e38a95e11f4f1a8d7c2
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
[X86] getTargetConstantBitsFromNode - don't support partial undefs by default.
Noticed by inspection - as undef bits are seen as zero, we could be matching in places where we require a zero but end up referencing an undef that could then get changed in a later fold.
Creating a test case has proven difficult as multi-use limits usually saves us, but really we shouldn't be allowing partial undefs for anything but constant folding.
Commit: d1427fb6d0e1dbe3b7dbf46c26e43ce96b9b56d5
https://github.com/llvm/llvm-project/commit/d1427fb6d0e1dbe3b7dbf46c26e43ce96b9b56d5
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang/lib/Edit/RewriteObjCFoundationAPI.cpp
Log Message:
-----------
[Edit] Use StringRef::consume_back (NFC)
Commit: 26648daeb2ea1e9443d214e3923583efba346603
https://github.com/llvm/llvm-project/commit/26648daeb2ea1e9443d214e3923583efba346603
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/lib/ExtractAPI/DeclarationFragments.cpp
Log Message:
-----------
[ExtractAPI] Use StringRef::starts_with (NFC)
Commit: 3bf21ba597d00253c6ef55bb0b499711dd778d84
https://github.com/llvm/llvm-project/commit/3bf21ba597d00253c6ef55bb0b499711dd778d84
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
Log Message:
-----------
[AMDGPU] Use MachineBasicBlock::instrs (NFC)
Commit: 2c552d319a5f0378c48390524de436265b05b943
https://github.com/llvm/llvm-project/commit/2c552d319a5f0378c48390524de436265b05b943
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
A llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
Log Message:
-----------
[AArch64][GlobalISel] Legalize G_ABS for Larger/Smaller Vectors (#79117)
Legalize G_ABS for larger/smaller width vectors with legal element sizes
Fallsback for the smaller width vector tests because it is unable to
legalize for G_ANYEXT smaller width vectors
Commit: a7cfff8dc6b38e54c6c5adee3b4b781f1090ee25
https://github.com/llvm/llvm-project/commit/a7cfff8dc6b38e54c6c5adee3b4b781f1090ee25
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/test/CodeGen/AArch64/arm64-rev.ll
Log Message:
-----------
[AArch64][GlobalISel] Lower Shuffle Vector to REV (#79591)
Add lowering for i16 and i32 vectors for Shuffle Vector instructions
with REV mask
Commit: 2d0d65b3babecbd339b01fdf7da29b8dfd69f889
https://github.com/llvm/llvm-project/commit/2d0d65b3babecbd339b01fdf7da29b8dfd69f889
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
Log Message:
-----------
[VPlan] Create edge masks all cases up front needed.(NFC)
Similarly to how block masks are created up front and later only
retrieved also make sure masks are created in cases where edge masks are
needed, i.e. blend recipes.
Creating block-in masks for all blocks in the loop also ensures edge
masks for all relevant edges have been created. Later, the new
getEdgeMask can be used to look up cached edge masks.
This makes sure edge masks are available in all cases for
https://github.com/llvm/llvm-project/pull/76090.
Commit: c34aa784f8867517315d8ef32a8038ee9dbb7165
https://github.com/llvm/llvm-project/commit/c34aa784f8867517315d8ef32a8038ee9dbb7165
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateDeduction.cpp
A clang/test/SemaTemplate/PR77189.cpp
Log Message:
-----------
[Clang][Sema] fix deducing auto& from const int in template parameters is impossible in partial specializations (#79733)
Fix [issue](https://github.com/llvm/llvm-project/issues/77189)
AutoType is possible cv qualified.
Co-authored-by: huqizhi <836744285 at qq.com>
Commit: 70c3e30e01bd123e87824e36b6e38a39451ac28d
https://github.com/llvm/llvm-project/commit/70c3e30e01bd123e87824e36b6e38a39451ac28d
Author: Jianjian Guan <jacquesguan at me.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
Log Message:
-----------
[RISCV][NFC] Remove unused methods of tuimm5 (#79680)
Since we only use tuimm5 in patterns, it doesn't need those methods for
MC layer. And there is not `getUImmOpValue` defination now, leave those
methods is confusing.
Commit: a3f379e4e9db9d88265e6dfc464fc3a5be3ae315
https://github.com/llvm/llvm-project/commit/a3f379e4e9db9d88265e6dfc464fc3a5be3ae315
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
Log Message:
-----------
[Frontend] Use StringRef::consume_back (NFC)
Commit: fc1573118333845e3ce0dc659b9e7cc3394d3c82
https://github.com/llvm/llvm-project/commit/fc1573118333845e3ce0dc659b9e7cc3394d3c82
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/GVN.cpp
Log Message:
-----------
[Transforms] Use a range-based for loop (NFC)
Commit: 1f5934a901d52786470c7e26c214b2b9773efd87
https://github.com/llvm/llvm-project/commit/1f5934a901d52786470c7e26c214b2b9773efd87
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
Log Message:
-----------
[PowerPC] Directly call Instruction::getMetadata (NFC)
Commit: ae46855f53b6fe39a8d17797a49b2911c08fb973
https://github.com/llvm/llvm-project/commit/ae46855f53b6fe39a8d17797a49b2911c08fb973
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[Target] Use getConstantOperand (NFC)
Commit: 07dfa61ace272fc5fc7f486cf42a3d603c8c21f5
https://github.com/llvm/llvm-project/commit/07dfa61ace272fc5fc7f486cf42a3d603c8c21f5
Author: ZhaoQi <zhaoqi01 at loongson.cn>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
Log Message:
-----------
[LoongArch] Fix a typo in getVariantKindName (NFC) (#79567)
Looks like a slip of the pen.
Commit: 0fbaf03f703db2cb29d1bde23708b80db049164f
https://github.com/llvm/llvm-project/commit/0fbaf03f703db2cb29d1bde23708b80db049164f
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
A llvm/lib/Target/SPIRV/SPIRVMetadata.h
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll
A llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll
A llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll
Log Message:
-----------
[SPIR-V] Cast ptr kernel args to i8* when used as Store's value operand (#78603)
Handle a special case when StoreInst's value operand is a kernel
argument of a pointer type. Since these arguments could have either a
basic element type (e.g. float*) or OpenCL builtin type (sampler_t),
bitcast the StoreInst's value operand to default pointer element type
(i8).
This pull request addresses the issue
https://github.com/llvm/llvm-project/issues/72864
Commit: a0b6747804e46665ecfd00295b60432bfe1775b6
https://github.com/llvm/llvm-project/commit/a0b6747804e46665ecfd00295b60432bfe1775b6
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
M clang/test/Modules/concept.cppm
M clang/test/Modules/no-eager-load.cppm
M clang/test/Modules/polluted-operator.cppm
M clang/test/Modules/pr76638.cppm
Log Message:
-----------
[C++20] [Modules] Don't perform ODR checks in GMF
Close https://github.com/llvm/llvm-project/issues/79240.
See the linked issue for details. Given the frequency of issue reporting
about false positive ODR checks (I received private issue reports too),
I'd like to backport this to 18.x too.
Commit: 86b3f8518f21532297e0aad0c6aea95c66389fc9
https://github.com/llvm/llvm-project/commit/86b3f8518f21532297e0aad0c6aea95c66389fc9
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M llvm/lib/Support/RISCVISAInfo.cpp
Log Message:
-----------
[RISCV] Used Twine concatenation instead of format strings RISCVISAInfo.cpp. NFC
We were converting several StringRefs to std::strings then to
char * so we could pass as %s to a format string. Use the Twine
signature of createStringError instead.
Commit: c09dc2d9855dbf81d95052ade22b2ca78b1d8b99
https://github.com/llvm/llvm-project/commit/c09dc2d9855dbf81d95052ade22b2ca78b1d8b99
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp
Log Message:
-----------
[mlir][openacc][flang] Support wait devnum and clean async/wait IR (#79525)
- Support wait(devnum: ) with device_type support on all operations that
require it
- devnum value is stored as the first value of waitOperands in its
device_type sub-segment. The hasWaitDevnum attribute inform which
sub-segment has a wait(devnum) value.
- Make async/wait information homogenous on compute ops, data and update
op.
- Unify operands/attributes names across operations and use the same
custom parser/printer
Commit: 4eeeeb305b6bb1c08e04482848f425b07029c82c
https://github.com/llvm/llvm-project/commit/4eeeeb305b6bb1c08e04482848f425b07029c82c
Author: Valentin Clement <clementval at gmail.com>
Date: 2024-01-28 (Sun, 28 Jan 2024)
Changed paths:
M flang/lib/Lower/OpenACC.cpp
Log Message:
-----------
[flang][openacc] Remove waitDevnum unused variable
Commit: 4118082f651a05cca258c684ab1199578b57afac
https://github.com/llvm/llvm-project/commit/4118082f651a05cca258c684ab1199578b57afac
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/lib/AST/ODRHash.cpp
A clang/test/Modules/cxx20-modules-enum-odr.cppm
Log Message:
-----------
[C++20] [Modules] Remove previous workaround for odr hashing enums
Previosly we land
https://github.com/llvm/llvm-project/commit/085eae6b863881fb9fda323e5b672b04a00ed19e
to workaround the false positive ODR violations in
https://github.com/llvm/llvm-project/issues/76638.
However, we decided to not perform ODR checks for decls from GMF in
https://github.com/llvm/llvm-project/issues/79240 and we land the
corresponding change. So we should be able to remove the workaround now.
The original tests get remained.
Commit: 4a39d08908942b2d415db405844cbe4af73e75d4
https://github.com/llvm/llvm-project/commit/4a39d08908942b2d415db405844cbe4af73e75d4
Author: Mark Johnston <markjdb at gmail.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M libcxx/src/filesystem/operations.cpp
M libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.remove_all/remove_all.pass.cpp
Log Message:
-----------
[libc++] Fix filesystem::remove_all() on FreeBSD (#79540)
remove_all_impl() opens the target path with O_NOFOLLOW, which fails if
the target is a symbolic link. On FreeBSD, rather than returning ELOOP,
openat() returns EMLINK. This is unlikely to change for compatibility
reasons, see https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=214633 .
Thus, check for EMLINK as well.
Commit: 66347e516e22f9159b86024071fb92f364ac4418
https://github.com/llvm/llvm-project/commit/66347e516e22f9159b86024071fb92f364ac4418
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
Log Message:
-----------
[mlir][vector] Drop inner unit dims for transfer ops on dynamic shapes. (#79752)
Commit: e3a38a75ddc6ff00301ec19a0e2488d00f2cc297
https://github.com/llvm/llvm-project/commit/e3a38a75ddc6ff00301ec19a0e2488d00f2cc297
Author: Andrei Golubev <andrey.golubev at intel.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M mlir/include/mlir/IR/Dialect.h
Log Message:
-----------
[mlir] Revert to old fold logic in IR::Dialect::add{Types, Attributes}() (#79582)
Fold expressions on Clang are limited to 256 elements. This causes
compilation errors in cases when the amount of elements added exceeds
this limit. Side-step the issue by restoring the original trick that
would use the std::initializer_list. For the record, in our downstream
Clang 16 gives:
mlir/include/mlir/IR/Dialect.h:269:23: fatal error: instantiating fold
expression with 688 arguments exceeded expression nesting limit of 256
(addType<Args>(), ...);
Partially reverts 26d811b3ecd2fa1ca3d9b41e17fb42b8c7ad03d6.
Co-authored-by: Nikita Kudriavtsev <nikita.kudriavtsev at intel.com>
Commit: 9f80ecb308c989523cc32d4256f7ab61c5b788d7
https://github.com/llvm/llvm-project/commit/9f80ecb308c989523cc32d4256f7ab61c5b788d7
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/unittests/AST/ASTImporterGenericRedeclTest.cpp
M clang/unittests/AST/ASTImporterTest.cpp
Log Message:
-----------
[clang][ASTImporter] Improve import of variable template specializations. (#78284)
Code of `VisitVarTemplateSpecializationDecl` was rewritten based on code
of `VisitVarDecl`. Additional changes (in structural equivalence) were
made to make tests pass.
Commit: ce8032394fa4ff55c36d857e85241c1bd0cacc60
https://github.com/llvm/llvm-project/commit/ce8032394fa4ff55c36d857e85241c1bd0cacc60
Author: Dominik Adamski <dominik.adamski at amd.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/lib/Lower/OpenMP.cpp
M flang/test/Lower/OpenMP/FIR/if-clause.f90
M flang/test/Lower/OpenMP/FIR/loop-combined.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-aligned.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-linear.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-safelen.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-simdlen.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-combined.f90
Log Message:
-----------
[Flang][OpenMP] Use simdloop operation only for omp simd pragma (#79559)
OpenMP standard differentiates between omp simd (2.9.3.1) and omp do/for
simd (2.9.3.2 for OpenMP 5.0 standard) pragmas. The first one describes
the loop which needs to be vectorized. The second pragma describes the
loop which needs to be workshared between existing threads. Each thread
can use SIMD instructions to execute its chunk of the loop.
That's why we need to model
```
!$omp simd
do-loop
```
as `omp.simdloop` operation and add compiler hints for vectorization.
The worksharing loop:
!$omp do simd
do-loop
should be represented as worksharing loop (`omp.wsloop`).
Currently Flang denotes both types of OpenMP pragmas by `omp.simdloop`
operation. In consequence we cannot differentiate between:
```
!$omp parallel simd
do-loop
```
and
```
!$omp parallel do simd
do-loop
```
The second loop should be workshared between multiple threads. The first one describes the loop which needs to be redundantly executed by multiple threads. Current Flang implementation does not perform worksharing for `!$omp do simd` pragma and generates valid code only for the first case.
Commit: 743946e8ef0d164cbaa3409d11b218e299ccd35e
https://github.com/llvm/llvm-project/commit/743946e8ef0d164cbaa3409d11b218e299ccd35e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
Log Message:
-----------
[VPlan] Replace VPRecipeOrVPValue with VP2VP recipe simplification. (#76090)
Move simplification of VPBlendRecipes from early VPlan construction to
VPlan-to-VPlan based recipe simplification. This simplifies initial
construction.
Note that some in-loop reduction tests are failing at the moment, due to
the reduction predicate being created after the reduction recipe. I will
provide a patch for that soon.
PR: https://github.com/llvm/llvm-project/pull/76090
Commit: 34d80f559a3ebaa354f7820022c5e050a47a9870
https://github.com/llvm/llvm-project/commit/34d80f559a3ebaa354f7820022c5e050a47a9870
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M lldb/include/lldb/Target/MemoryHistory.h
M lldb/source/API/SBBreakpointOptionCommon.h
Log Message:
-----------
[lldb][NFC] Fix license comment lines that are too long
These get wrapped by clang-format currently.
Commit: 89c9fee420e1ed099aaa4aab48f3b58e233a3ea9
https://github.com/llvm/llvm-project/commit/89c9fee420e1ed099aaa4aab48f3b58e233a3ea9
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M lldb/include/lldb/API/SBBreakpointName.h
M lldb/include/lldb/Breakpoint/BreakpointName.h
M lldb/include/lldb/Breakpoint/BreakpointResolverScripted.h
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.h
M lldb/source/Plugins/Architecture/Mips/ArchitectureMips.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp
Log Message:
-----------
[lldb][NFC] Fix more license headers
Extra characters and one with an incorrect file name.
Commit: 378f7ad3b7080fb17829e53452692fd5809f4790
https://github.com/llvm/llvm-project/commit/378f7ad3b7080fb17829e53452692fd5809f4790
Author: David Green <david.green at arm.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
A flang/test/HLFIR/maxloc-elemental.fir
Log Message:
-----------
[Flang] Maxloc elemental intrinsic lowering. (#79469)
This is an extension to #74828 to handle maxloc too, to keep the minloc
and maxloc symmetric.
Commit: ba5d92eb9c18a9037dd06a74f90ceba3f4e3ace9
https://github.com/llvm/llvm-project/commit/ba5d92eb9c18a9037dd06a74f90ceba3f4e3ace9
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/docs/CodeReview.rst
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/GettingStarted.rst
M llvm/docs/MyFirstTypoFix.rst
Log Message:
-----------
[llvm][Docs] Update MyFirstTypoFix doc (#79149)
I've not tried to change the purpose or style of the doc, just edited
for clarity and removed any Phabricator related language in favour of
GitHub terms.
Where possible, I've swapped direct links to LLVM's website with RST
links to the local documents. Which should be a bit more resilient.
Also it's less confusing if you're editing multiple pages locally, you
don't accidentally end up on the live site.
Commit: c9535d7b61a37d6fa58e51222a9ccecc54431193
https://github.com/llvm/llvm-project/commit/c9535d7b61a37d6fa58e51222a9ccecc54431193
Author: Stephan T. Lavavej <stl at nuwen.net>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.pointer.pass.cpp
Log Message:
-----------
[libc++][test] Silence MSVC warnings (#79791)
* `libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp`
emits a bunch of warnings, all caused by what appears to be intentional
code:
+ Silence MSVC warning C4245: conversion from `'int'` to `'wchar_t'`,
signed/unsigned mismatch
- Caused by: `test<U>(0, -1);`
+ Silence MSVC warning C4305: 'argument': truncation from `'int'` to
`'bool'`
- Caused by: `test<U>(0, -1);`
+ Silence MSVC warning C4310: cast truncates constant value
- Caused by: `test<U>(T(-129), U(-129));`
+ Silence MSVC warning C4805: `'=='`: unsafe mix of type `'char'` and
type `'bool'` in operation
- Caused by: `bool expect_match = val == to_find;`
*
`libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp`
+ Silence MSVC warning C4244: 'argument': conversion from `'double'` to
`'const int'`, possible loss of data
- Caused by `[](int const x, double const y) { return x + y; }`
deliberately being given `double`s to truncate.
*
`libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.pointer.pass.cpp`
+ Silence MSVC warnings about C++20 deprecated `volatile`.
- Caused by: `runtime_test< volatile T>();`
Commit: ef83894810db8ec72489f1b45bf943938f6b0af4
https://github.com/llvm/llvm-project/commit/ef83894810db8ec72489f1b45bf943938f6b0af4
Author: Stephan T. Lavavej <stl at nuwen.net>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M libcxx/test/std/algorithms/alg.nonmodifying/alg.contains/ranges.contains.pass.cpp
Log Message:
-----------
[libc++][test] Fix zero-length arrays and copy-pasted lambdas in `ranges.contains.pass.cpp` (#79792)
* Fix MSVC error C2466: cannot allocate an array of constant size 0
+ MSVC rejects this non-Standard extension. Previous fixes: #74183
* Fix MSVC warning C4805: `'=='`: unsafe mix of type `'int'` and type
`'const bool'` in operation
+ AFAICT, these lambdas were copy-pasted, and didn't intend to take and
return `int` here. This part of the test is using `vector<bool>` for
random-access but non-contiguous iterators, and it's checking how many
times the projection is invoked, but the projection doesn't need to do
anything squirrely, it should otherwise be an identity.
* Fix typos: "continuous" => "contiguous".
Commit: 2e2b6b53f5f63179b52168ee156df7c76b90bc71
https://github.com/llvm/llvm-project/commit/2e2b6b53f5f63179b52168ee156df7c76b90bc71
Author: Peter Waller <peter.waller at arm.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M compiler-rt/lib/builtins/aarch64/sme-libc-routines.c
Log Message:
-----------
[AArch64][compiler-rt] Avoid use of libc header in sme-libc-routines (#79454)
The use of `#include <stdlib.h>` introduces a libc dependency. In many
build environments such a file can be found under e.g. /usr/include, but
this does not necessarily correspond to the libc in use, which may not
be available until after the builtins have been built.
So far as I understand, it's not valid to have a dependency on libc from
builtins; there are a handful of such includes in builtins, but they are
protected by ifdefs.
Instead, use <stddef.h>, which provides `size_t` and is provided by the
compiler's resource headers and so should always be available.
Commit: 14a15103cc9dbdb3e95c04627e0b96b5e3aa4944
https://github.com/llvm/llvm-project/commit/14a15103cc9dbdb3e95c04627e0b96b5e3aa4944
Author: Yi Wu <43659785+yi-wu-arm at users.noreply.github.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/docs/Intrinsics.md
M flang/lib/Evaluate/intrinsics.cpp
A flang/test/Semantics/execute_command_line.f90
Log Message:
-----------
Apply kind code check on exitstat and cmdstat (#78286)
When testing on gcc, both exitstat and cmdstat must be a kind=4 integer,
e.g. DefaultInt. This patch changes the input arg requirement from
`AnyInt` to `TypePattern{IntType, KindCode::greaterOrEqualToKind, n}`.
The standard stated in 16.9.73
- EXITSTAT (optional) shall be a scalar of type integer with a decimal
exponent range of at least nine.
- CMDSTAT (optional) shall be a scalar of type integer with a decimal
exponent range of at least four.
```fortran
program bug
implicit none
integer(kind = 2) :: exitstatvar
integer(kind = 4) :: cmdstatvar
character(len=256) :: msg
character(len=:), allocatable :: command
command='echo hello'
call execute_command_line(command, exitstat=exitstatvar, cmdstat=cmdstatvar)
end program
```
When testing the above program with exitstatvar kind<4, an error would
occur:
```
$ ../build-release/bin/flang-new test.f90
error: Semantic errors in test.f90
./test.f90:8:47: error: Actual argument for 'exitstat=' has bad type or kind 'INTEGER(2)'
call execute_command_line(command, exitstat=exitstatvar)
```
When testing the above program with exitstatvar kind<2, an error would
occur:
```
$ ../build-release/bin/flang-new test.f90
error: Semantic errors in test.f90
./test.f90:8:47: error: Actual argument for 'cmdstat=' has bad type or kind 'INTEGER(1)'
call execute_command_line(command, cmdstat=cmdstatvar)
```
Test file for this semantics has been added to `flang/test/Semantic`
Fixes: https://github.com/llvm/llvm-project/issues/77990
Commit: 5f4ee5a2dfa97fe32ee62d1d67aa1413d5a059e6
https://github.com/llvm/llvm-project/commit/5f4ee5a2dfa97fe32ee62d1d67aa1413d5a059e6
Author: Shanzhi <chenshanzhi at huawei.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/lib/AST/ASTContext.cpp
A clang/test/AST/ast-crash-doc-function-template.cpp
Log Message:
-----------
[Clang][AST] Fix a crash on attaching doc comments (#78716)
This crash is basically caused by calling
`ASTContext::getRawCommentForDeclNoCacheImp` with its input arguments
`RepresentativeLocForDecl` and `CommentsInTheFile` refering to different
files. A reduced reproducer is provided in this patch.
After the source locations for instantiations of funtion template are
corrected in the commit 256a0b298c68b89688b80350b034daf2f7785b67, the
variable `CommitsInThisFile` in the function
`ASTContext::attachCommentsToJustParsedDecls` would refer to the source
file rather than the header file for implicit function template
instantiation. Therefore, in the first loop in
`ASTContext::attachCommentsToJustParsedDecls`, `D` should also be
adjusted for relevant scenarios like the second loop.
Fixes #67979
Fixes #68524
Fixes #70550
Commit: 888501bc631c4f6d373b4081ff6c504a1ce4a682
https://github.com/llvm/llvm-project/commit/888501bc631c4f6d373b4081ff6c504a1ce4a682
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBEvent.h
M lldb/include/lldb/API/SBStream.h
M lldb/include/lldb/Interpreter/Interfaces/ScriptedInterface.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedThreadPlanInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/ThreadPlanPython.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Target/ThreadPlanPython.cpp
M lldb/test/API/functionalities/step_scripted/Steps.py
M lldb/test/API/functionalities/thread_plan/wrap_step_over.py
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
Log Message:
-----------
[lldb] Make use of Scripted{Python,}Interface for ScriptedThreadPlan (#70392)
This patch makes ScriptedThreadPlan conforming to the ScriptedInterface
& ScriptedPythonInterface facilities by introducing 2
ScriptedThreadPlanInterface & ScriptedThreadPlanPythonInterface classes.
This allows us to get rid of every ScriptedThreadPlan-specific SWIG
method and re-use the same affordances as other scripting offordances,
like Scripted{Process,Thread,Platform} & OperatingSystem.
To do so, this adds new transformer methods for `ThreadPlan`, `Stream` &
`Event`, to allow the bijection between C++ objects and their python
counterparts.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: febb4c42b192ed7c88c17f91cb903a59acf20baf
https://github.com/llvm/llvm-project/commit/febb4c42b192ed7c88c17f91cb903a59acf20baf
Author: Med Ismail Bennani <ismail at bennani.ma>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
Log Message:
-----------
[lldb/Test] Temporarily XFAIL TestStepScripted.py
This patch XFAILs TestStepScripted.py temporarily following 888501bc631c,
until I fix it.
Signed-off-by: Med Ismail Bennani <ismail at bennani.ma>
Commit: ec8c8b6487d53b2c3222f1a2f8968e754b070912
https://github.com/llvm/llvm-project/commit/ec8c8b6487d53b2c3222f1a2f8968e754b070912
Author: David Green <david.green at arm.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
Log Message:
-----------
[Flang] Remove constexpr from isMax variable. NFC
The MSCV build doesn't allow the constexpr isMax variable to be used in lambda
without a capture. The -Weverything build does not allow isMax to be used in a
lambda capture as it is a constexpr. I've removed the constexpr as it shouldn't
be necessary.
Commit: 2dd254566d0242be2d78f1656cee12a84e7aea00
https://github.com/llvm/llvm-project/commit/2dd254566d0242be2d78f1656cee12a84e7aea00
Author: NimishMishra <42909663+NimishMishra at users.noreply.github.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/cosd.f90
A flang/test/Lower/Intrinsics/sind.f90
Log Message:
-----------
[flang] Add support for COSD/SIND (#79546)
Added support for COSD and SIND. This is quick fix. ATAND, TAND, COSD
and SIND needs to be revisited to make it a runtime call. This patch has
code changes and test cases.
Commit: 3a4a7dcd623b9cbd6371c3246a31e985f1f7f232
https://github.com/llvm/llvm-project/commit/3a4a7dcd623b9cbd6371c3246a31e985f1f7f232
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul64.ll
Log Message:
-----------
[X86] Replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Commit: bc879a90193151ef39f3915f6687423c18875486
https://github.com/llvm/llvm-project/commit/bc879a90193151ef39f3915f6687423c18875486
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/mul-i256.ll
Log Message:
-----------
[X86] mul-i256.ll - simplify function attributes and remove cfi noise
Commit: 754a8add57098ef71e4a51a9caa0cc175e94377d
https://github.com/llvm/llvm-project/commit/754a8add57098ef71e4a51a9caa0cc175e94377d
Author: Cullen Rhodes <cullen.rhodes at arm.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
Log Message:
-----------
[mlir][llvm] Add experimental.vector.interleave2 intrinsic (#79270)
Commit: 6d242914d784ed848d0f87bf6df9b6b2f2b27566
https://github.com/llvm/llvm-project/commit/6d242914d784ed848d0f87bf6df9b6b2f2b27566
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/test/CodeGen/SystemZ/unaligned-symbols.c
A clang/test/Driver/s390x-unaligned-symbols.c
Log Message:
-----------
[Clang, SystemZ] Split test into Driver and CodeGen parts (NFC) (#79808)
The test added in #73511 currently fails in
CLANG_DEFAULT_PIE_ON_LINUX=OFF configuration, because it uses the clang
driver in a codegen test.
Split the test into two, a driver test that checks that the appropriate
target feature is passed, and a codegen test that uses cc1.
Commit: 4a3d187075b2e3795b3e00e6ebb7a2a42143f3bb
https://github.com/llvm/llvm-project/commit/4a3d187075b2e3795b3e00e6ebb7a2a42143f3bb
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M libc/src/time/gpu/time_utils.h
Log Message:
-----------
[libc][NFC] Simplify AMDGPU constant frequency checks (#79653)
Summary:
The AMDGPU fixed frequency clock is fixed to a chip dependent frequency.
More modern chips have started to fix this at known values of 25 MHz or
100 MHz, so this function forwards those values. This was done using the
individual architectures. This patch simply uses the more concise
`__GFXn__` macro which indicates the major revision
Commit: a372460538595d4c5a769c4c248fe7b1b4d69882
https://github.com/llvm/llvm-project/commit/a372460538595d4c5a769c4c248fe7b1b4d69882
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_other.h
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_x86.h
Log Message:
-----------
[Sanitizer][NFC] Fix up comment in atomic_store of sanitizer_atomic_clang_*.h
Commit: d93f850c6f11aa315c83a34ec59210e1755528f8
https://github.com/llvm/llvm-project/commit/d93f850c6f11aa315c83a34ec59210e1755528f8
Author: Jason Eckhardt <jason.eckhardt at solana.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/include/llvm/MC/MCDecoderOps.h
A llvm/test/TableGen/trydecode-emission4.td
M llvm/utils/TableGen/DecoderEmitter.cpp
Log Message:
-----------
[TableGen] Extend OPC_ExtractField/OPC_CheckField start value widths. (#79723)
Both OPC_ExtractField and OPC_CheckField are currently defined to take
an unsigned 8-bit start value. On some architectures with long
instruction words, this value can silently overflow, resulting in a bad
decoder table.
This patch changes each to take a ULE128B-encoded start value instead.
Additionally, a range assertion is added for the 8-bit length to
prominently notify a user in case that field ever overflows.
This problem isn't currently exposed upstream since all in-tree targets
use small instruction words (i.e., bitwidth <= 64 bits). It does show up
in at least one downstream target with instructions > 64 bits long.
Co-authored-by: Jason Eckhardt <jeckhardt at nvidia.com>
Commit: 8a074c84ff01f8581b4a769c4af3abab9731fe5b
https://github.com/llvm/llvm-project/commit/8a074c84ff01f8581b4a769c4af3abab9731fe5b
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/fixup-bw-copy.ll
Log Message:
-----------
[X86] fixup-bw-copy.ll - replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Commit: ccb2810ee33588ad0707e51bb31af8fec5e39f76
https://github.com/llvm/llvm-project/commit/ccb2810ee33588ad0707e51bb31af8fec5e39f76
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/anyext.ll
Log Message:
-----------
[X86] anyext.ll - replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Commit: 06f5b956a0ba3bb1cad7d94707398a97750d8b37
https://github.com/llvm/llvm-project/commit/06f5b956a0ba3bb1cad7d94707398a97750d8b37
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/pmovsx-inreg.ll
Log Message:
-----------
[X86] pmovsx-inreg.ll - replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Commit: eb56bc2b105c792bafd36ef35c0e6eda9f0b822e
https://github.com/llvm/llvm-project/commit/eb56bc2b105c792bafd36ef35c0e6eda9f0b822e
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M libc/src/math/generic/asinf.cpp
M libc/src/math/generic/sincosf.cpp
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdio/sscanf_test.cpp
Log Message:
-----------
[libc] Remove specific nan payload in math functions (#79165)
Commit: 5e3fc9c37f01c75fad306db71b5235bdc300194b
https://github.com/llvm/llvm-project/commit/5e3fc9c37f01c75fad306db71b5235bdc300194b
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M .github/workflows/llvm-tests.yml
Log Message:
-----------
[workflows] Fix argument passing in abi-dump jobs (#79658)
This was broken by 859e6aa1008b80d9b10657bac37822a32ee14a23, which added
quotes around the EXTRA_ARGS variable.
Commit: c9a6e993f7b349405b6c8f9244cd9cf0f56a6a81
https://github.com/llvm/llvm-project/commit/c9a6e993f7b349405b6c8f9244cd9cf0f56a6a81
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl
M clang/test/Preprocessor/predefined-arch-macros.c
Log Message:
-----------
[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#79660)
Summary:
Currently, the AMDGPU toolchain accepts not passing `-mcpu` as a means
to create a sort of "generic" IR. The resulting IR will not contain any
target dependent attributes and can then be inserted into another
program via `-mlink-builtin-bitcode` to inherit its attributes.
However, there are a handful of macros that can leak incorrect
information when compiling for an unspecified architecture. Currently,
things like the wavefront size will default to 64, which is actually
variable. We should not expose these macros unless it is known.
Commit: 8b429fc3fe2d5a9c55f953b4d0eecdb1f9f6fe06
https://github.com/llvm/llvm-project/commit/8b429fc3fe2d5a9c55f953b4d0eecdb1f9f6fe06
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Update SITargetLowering::getAddrModeArguments (#78740)
Handle every intrinsic for which getTgtMemIntrinsic returns with
Info.ptrVal set to one of the intrinsic's operands. A bunch of these
cases were missing.
Commit: cfb702676cc181877482a282fe7e07109a24dc9d
https://github.com/llvm/llvm-project/commit/cfb702676cc181877482a282fe7e07109a24dc9d
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86InstrFoldTables.cpp
M llvm/lib/Target/X86/X86InstrFoldTables.h
Log Message:
-----------
[X86][NFC] Rename lookupBroadcastFoldTable to lookupBroadcastFoldTableBySize
Address RKSimon's comments in #79761
Commit: ce72f78f37199d693a65b6c7c1d637fafbb13727
https://github.com/llvm/llvm-project/commit/ce72f78f37199d693a65b6c7c1d637fafbb13727
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
Log Message:
-----------
[AMDGPU] Fix mul combine for MUL24 (#79110)
MUL24 can now return a i64 for i32 operands, but the combine was never
updated to handle this case. Extend the operand when rewriting the ADD
to handle it.
Fixes SWDEV-436654
Commit: df3f0eeeacbe50a6e4b2ce7c2a12f96e7b6ce5e0
https://github.com/llvm/llvm-project/commit/df3f0eeeacbe50a6e4b2ce7c2a12f96e7b6ce5e0
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/test/Fir/boxproc-2.fir
Log Message:
-----------
[flang] Fix invalid iterator erasure in boxed-procedure pass (#79830)
The code in BoxedProcedureRewrite was erasing the mappings <old type,
new type> once "new type" was fully translated. This was done in an
invalid way because the map was an llvm::SmallMapVector that do not have
stable iterators, and new items were added to the map between the
creation of the iterator and its erasure.
It is anyway not needed and expensive to erase the types (see
llvm::MapVector note), the cache can be used for the whole pass, which
is very beneficial in the context of an apps using "big derived types"
(dozens of components/parents).
Commit: d833b9d677c9dd0a35a211e2fdfada21ea9a464b
https://github.com/llvm/llvm-project/commit/d833b9d677c9dd0a35a211e2fdfada21ea9a464b
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
M llvm/test/MC/RISCV/rv32zicond-invalid.s
M llvm/test/MC/RISCV/rv32zicond-valid.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Graduate Zicond to non-experimental (#79811)
The Zicond extension was ratified in the last few months, with no
changes that affect the LLVM implementation. Although there's surely
more tuning that could be done about when to select Zicond or not, there
are no known correctness issues. Therefore, we should mark support as
non-experimental.
Commit: d133ada9460aad6d60393fb1260082e62d640500
https://github.com/llvm/llvm-project/commit/d133ada9460aad6d60393fb1260082e62d640500
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-30 (Tue, 30 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrFoldTables.cpp
Log Message:
-----------
[X86][CodeGen] Add missing BroadcastTable1 in X86MemUnfoldTable
Commit: ee08b992514bd1556c38f42409d92728af3451f7
https://github.com/llvm/llvm-project/commit/ee08b992514bd1556c38f42409d92728af3451f7
Author: Jimmy Z <51149050+jimmy-zx at users.noreply.github.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/test_rewrite.py
M clang/docs/ReleaseNotes.rst
Log Message:
-----------
[libclang/python] Expose Rewriter to the python binding (#77269)
Exposes `CXRewriter` API to the python binding as `class Rewriter`.
Commit: 70f5b220509cafb3dc4e876e4feecb3dcca78dec
https://github.com/llvm/llvm-project/commit/70f5b220509cafb3dc4e876e4feecb3dcca78dec
Author: Michael Liao <michael.hliao at gmail.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
Log Message:
-----------
[TableGen][AsmMatcher] Fix the range check on 'MatchClassKind'
- When selecting the minimal type for 'MatchClassKind' during the
emission of 'MatchEntry' and 'OperandMatchEntry', two pre-defined
kinds 'InvalidMatchClass' and 'OptionalMatchClass' are not taken into
account.
Commit: 169553688ca40d9a495f19e8ba2af1137e13cff8
https://github.com/llvm/llvm-project/commit/169553688ca40d9a495f19e8ba2af1137e13cff8
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-30 (Tue, 30 Jan 2024)
Changed paths:
M llvm/include/llvm/Support/X86FoldTablesUtils.h
M llvm/lib/Target/X86/X86InstrFoldTables.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
Log Message:
-----------
[X86][NFC] Remove TB_FOLDED_BCAST and format code in X86InstrFoldTables.cpp
Commit: 7c8ef76500b40c3b7cb65b839b61345b713aeb5a
https://github.com/llvm/llvm-project/commit/7c8ef76500b40c3b7cb65b839b61345b713aeb5a
Author: Yi Wu <43659785+yi-wu-arm at users.noreply.github.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/docs/Intrinsics.md
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
A flang/test/Lower/Intrinsics/system-optional.f90
A flang/test/Lower/Intrinsics/system.f90
M flang/unittests/Runtime/CommandTest.cpp
Log Message:
-----------
[flang] add SYSTEM runtime and lowering intrinsics support (#74309)
Calls std::system() function and pass the command,
cmd on Windows or shell on Linux.
Command parameter is required, exitstatus is optional.
call system(command)
call system(command, exitstatus)
It calls `execute_command_line` runtime function with `wait` set to true.
---------
Co-authored-by: Yi Wu <yiwu02 at wdev-yiwu02.arm.com>
Commit: ae8005ffb6cd18900de8ed5a86f60a4a16975471
https://github.com/llvm/llvm-project/commit/ae8005ffb6cd18900de8ed5a86f60a4a16975471
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/test/Driver/aarch64-mcpu.c
M clang/test/Misc/target-invalid-cpu-note.c
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][TargetParser] Add mcpu alias for Microsoft Azure Cobalt 100. (#79614)
With a690e86 we added -mcpu/mtune=native support to handle the Microsoft
Azure Cobalt 100 CPU as a Neoverse N2. This patch adds a CPU alias in
TargetParser to maintain compatibility with GCC.
Commit: 430c1fd50d774dc30a9628bcf60ce243f74ff376
https://github.com/llvm/llvm-project/commit/430c1fd50d774dc30a9628bcf60ce243f74ff376
Author: Gheorghe-Teodor Bercea <doru.bercea at amd.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M openmp/libomptarget/DeviceRTL/src/Parallelism.cpp
Log Message:
-----------
[libomptarget][NFC] Outline parallel SPMD function (#78642)
This patch outlines the SPMD code path into a separate function that can
be called directly.
Commit: 9520773c46777adbc1d489f831d6c93b8287ca0e
https://github.com/llvm/llvm-project/commit/9520773c46777adbc1d489f831d6c93b8287ca0e
Author: David Green <david.green at arm.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
Log Message:
-----------
[AArch64] Don't generate neon integer complex numbers with +sve2. NFC (#79829)
The condition for allowing integer complex number support could also
allow neon fixed length complex numbers if +sve2 was specified. This
tightens the condition to only allow integer complex number support for
scalable vectors.
We could generalize this in the future to generate SVE intrinsics for
fixed-length vectors, but for the moment this opts for the simpler fix.
Commit: cbe5985ff7cd21924ed88b6a46fd5c04acc7fca8
https://github.com/llvm/llvm-project/commit/cbe5985ff7cd21924ed88b6a46fd5c04acc7fca8
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/shift-amount-mod.ll
M llvm/test/CodeGen/X86/shift-and.ll
M llvm/test/CodeGen/X86/shift-combine.ll
Log Message:
-----------
[X86] Replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Commit: f28430d577276bf58d96945a6919399baa6c2527
https://github.com/llvm/llvm-project/commit/f28430d577276bf58d96945a6919399baa6c2527
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-30 (Tue, 30 Jan 2024)
Changed paths:
M llvm/include/llvm/Support/X86FoldTablesUtils.h
M llvm/lib/Target/X86/X86InstrInfo.cpp
Log Message:
-----------
[X86][CodeGen] Add entries for TB_BCAST_W in getBroadcastOpcode and fix typo
Commit: 72d4fc1b4d5cfc4f7d50cc5cf1b315543c088f4d
https://github.com/llvm/llvm-project/commit/72d4fc1b4d5cfc4f7d50cc5cf1b315543c088f4d
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.cpp
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave64.cl
M clang/test/Preprocessor/predefined-arch-macros.c
Log Message:
-----------
Revert "[AMDGPU] Do not emit arch dependent macros with unspecified cpu (#79660)"
This reverts commit c9a6e993f7b349405b6c8f9244cd9cf0f56a6a81.
This breaks HIP code that incorrectly depended on GPU-specific macros to
be set. The code is totally wrong as using `__WAVEFRTONSIZE__` on the
host is absolutely meaningless, but it seems this entire corner of the
toolchain is fundmentally broken. Reverting for now to avoid breakages.
Commit: 3e47e75febc8fefa19afe1e8ef2b15a106d2f791
https://github.com/llvm/llvm-project/commit/3e47e75febc8fefa19afe1e8ef2b15a106d2f791
Author: Slava Zakharin <szakharin at nvidia.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/Transforms/LoopVersioning.cpp
M flang/test/Transforms/loop-versioning.fir
Log Message:
-----------
[flang] Use DataLayout for computing type size in LoopVersioning. (#79778)
The existing type size computation in LoopVersioning does not work
for REAL*10, because the compute element size is 10 bytes,
which violates the power-of-two assertion.
We'd better use the DataLayout for computing the storage size
of each element of an array of the given type.
Commit: db6bf92123fbc82dd6e3da4f88e440415352692d
https://github.com/llvm/llvm-project/commit/db6bf92123fbc82dd6e3da4f88e440415352692d
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
A llvm/include/llvm/Support/DXILABI.h
R llvm/include/llvm/Support/DXILOperationCommon.h
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/utils/TableGen/DXILEmitter.cpp
Log Message:
-----------
[DirectX] Rename DXILOperationCommon.h to DXILABI.h. NFC
This is a good place to put all of the ABI-sensitive DXIL values that
we'll need in both reading and writing contexts.
Pull Request: https://github.com/llvm/llvm-project/pull/78224
Commit: 181eab27d244b9a9eb32d6716f9c38f7f3723356
https://github.com/llvm/llvm-project/commit/181eab27d244b9a9eb32d6716f9c38f7f3723356
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M flang/include/flang/Evaluate/common.h
M flang/include/flang/Lower/Bridge.h
M flang/lib/Evaluate/shape.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Evaluate/rewrite07.f90
M flang/unittests/Evaluate/expression.cpp
M flang/unittests/Evaluate/folding.cpp
M flang/unittests/Evaluate/intrinsics.cpp
Log Message:
-----------
[flang] Set KIND in compiler generated COUNT for SIZE(PACK) (#79801)
Compiler was rewriting SIZE(PACK(x, MASK)) to COUNT(MASK). It was
wrapping the COUNT call without a KIND argument (leading to INTEGER(4)
result in the characteristics) in an Expr<ExtentType> (implying
INTEGER(8) result), this lead to inconsistencies that later hit verifier
errors in lowering.
Set the KIND argument to the KIND of ExtentType to ensure the built
expression is consistent.
This requires giving access to some safe place where the "kind" name can
be saved and turned into a CharBlock (count has a DIM argument that
require using the KIND keyword here). For the FoldingContext that belong
to SemanticsContext, this is the same string set as the one used by
SemanticsContext for similar purposes.
Commit: 8c0a61125e52b137e45131773ec08bab3e2593e4
https://github.com/llvm/llvm-project/commit/8c0a61125e52b137e45131773ec08bab3e2593e4
Author: Will Hawkins <hawkinsw at obs.cr>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/compare.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/decrement.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/ctor.parent_iter.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/decrement.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/deref.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/compare.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/ctor.default.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/ctor.parent.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/types.h
Log Message:
-----------
[libcxx][NFC] Rename iterator/sentinel type template parameter names (#76201)
According to internally agreed upon best practices, type template
parameter names representing iterator types should be named `Iter`. For
type template parameters representing sentinel types, they should be
named `Sent`.
Signed-off-by: Will Hawkins <hawkinsw at obs.cr>
Commit: ad7131864f5a1a23f8c8d054a5e31c9979edd497
https://github.com/llvm/llvm-project/commit/ad7131864f5a1a23f8c8d054a5e31c9979edd497
Author: Justin Bogner <mail at justinbogner.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/include/llvm/Frontend/HLSL/HLSLResource.h
M llvm/include/llvm/Support/DXILABI.h
M llvm/lib/Target/DirectX/DXILResource.cpp
M llvm/lib/Target/DirectX/DXILResource.h
Log Message:
-----------
[DirectX] Move DXIL ResourceKind and ElementType to DXILABI.h. NFC
Pull Request: https://github.com/llvm/llvm-project/pull/78225
Commit: 2aef33230d3402878a837f9aaa37e37d0763d1ac
https://github.com/llvm/llvm-project/commit/2aef33230d3402878a837f9aaa37e37d0763d1ac
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/fast-isel-store.ll
Log Message:
-----------
[X86] fast-isel-store.ll - cleanup check prefixes
32/64-bit triples and check prefixes were inverted, and missing unwind attribute to strip cfi noise
Commit: 3ab5dbb1995982ab7d106e39a719daaea8bdfeee
https://github.com/llvm/llvm-project/commit/3ab5dbb1995982ab7d106e39a719daaea8bdfeee
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/sext-i1.ll
Log Message:
-----------
[X86] sext-i1.ll - replace X32 check prefixes with X86
We try to only use X32 for gnux32 triple tests.
Commit: 0a15ead01b6be095a87a405e63e9525ed123ac58
https://github.com/llvm/llvm-project/commit/0a15ead01b6be095a87a405e63e9525ed123ac58
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
A llvm/test/Transforms/BDCE/binops-multiuse.ll
Log Message:
-----------
[BDCE] Introduce test for PR79688 (NFC)
Commit: 20737825c9122b6e0a8912731cfa7e0558fe025d
https://github.com/llvm/llvm-project/commit/20737825c9122b6e0a8912731cfa7e0558fe025d
Author: Antonio Frighetto <me at antoniofrighetto.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/BDCE.cpp
M llvm/test/Transforms/BDCE/binops-multiuse.ll
M llvm/test/Transforms/BDCE/dead-uses.ll
Log Message:
-----------
[BDCE] Handle multi-use binary ops upon demanded bits
Simplify multi-use `and`/`or`/`xor` when these last
do not affect the demanded bits being considered.
Fixes: https://github.com/llvm/llvm-project/issues/78596.
Proofs: https://alive2.llvm.org/ce/z/EjuWHa.
Commit: 7b0396faabce0cec470779ae5e3a851bedb2ac12
https://github.com/llvm/llvm-project/commit/7b0396faabce0cec470779ae5e3a851bedb2ac12
Author: Shafik Yaghmour <shafik.yaghmour at intel.com>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaStmt.cpp
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
Log Message:
-----------
[Clang][Sema] Fix crash when type used in return statement contains errors (#79788)
In Sema in `BuildReturnStmt(...)` when we try to determine is the type
is move eligible or copy elidable we don't currently check of the init
of the `VarDecl` contain errors or not. This can lead to a crash since
we may send a type that is not complete into `getTypeInfo(...)` which
does not allow this.
This fixes: https://github.com/llvm/llvm-project/issues/63244
https://github.com/llvm/llvm-project/issues/79745
Commit: e27ec318dab2ee7d88bd3435bc188810084a3873
https://github.com/llvm/llvm-project/commit/e27ec318dab2ee7d88bd3435bc188810084a3873
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-29 (Mon, 29 Jan 2024)
Changed paths:
M .github/workflows/llvm-tests.yml
M clang-tools-extra/clang-tidy/ClangTidyDiagnosticConsumer.cpp
M clang-tools-extra/clangd/SourceCode.cpp
M clang-tools-extra/clangd/unittests/SourceCodeTests.cpp
M clang/bindings/python/clang/cindex.py
A clang/bindings/python/tests/cindex/test_rewrite.py
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ExtractAPI/DeclarationFragments.h
M clang/include/clang/Serialization/ASTReader.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/Interp/Context.cpp
M clang/lib/AST/ODRHash.cpp
M clang/lib/Edit/RewriteObjCFoundationAPI.cpp
M clang/lib/ExtractAPI/DeclarationFragments.cpp
M clang/lib/Format/WhitespaceManager.cpp
M clang/lib/Frontend/VerifyDiagnosticConsumer.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplateDeduction.cpp
M clang/lib/Serialization/ASTReader.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/Serialization/ASTWriter.cpp
M clang/lib/Serialization/ASTWriterDecl.cpp
A clang/test/AST/ast-crash-doc-function-template.cpp
M clang/test/Analysis/additive-op-on-sym-int-expr.c
M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
M clang/test/CodeGen/SystemZ/unaligned-symbols.c
M clang/test/Driver/aarch64-mcpu.c
A clang/test/Driver/s390x-unaligned-symbols.c
M clang/test/Misc/target-invalid-cpu-note.c
M clang/test/Modules/concept.cppm
A clang/test/Modules/cxx20-modules-enum-odr.cppm
M clang/test/Modules/no-eager-load.cppm
M clang/test/Modules/polluted-operator.cppm
M clang/test/Modules/pr76638.cppm
M clang/test/Preprocessor/riscv-target-features.c
M clang/test/SemaCXX/deduced-return-type-cxx14.cpp
A clang/test/SemaTemplate/PR77189.cpp
M clang/unittests/AST/ASTImporterGenericRedeclTest.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/utils/TableGen/ClangOpcodesEmitter.cpp
M compiler-rt/lib/builtins/aarch64/sme-libc-routines.c
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_other.h
M compiler-rt/lib/sanitizer_common/sanitizer_atomic_clang_x86.h
M flang/docs/Extensions.md
M flang/docs/Intrinsics.md
M flang/include/flang/Evaluate/common.h
M flang/include/flang/Lower/Bridge.h
M flang/include/flang/Optimizer/Builder/IntrinsicCall.h
M flang/include/flang/Optimizer/Dialect/FIRType.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Lower/Bridge.cpp
M flang/lib/Lower/OpenACC.cpp
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/lib/Optimizer/CodeGen/Target.cpp
M flang/lib/Optimizer/Dialect/FIRType.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/Transforms/LoopVersioning.cpp
M flang/lib/Semantics/semantics.cpp
A flang/test/Evaluate/rewrite07.f90
M flang/test/Fir/boxproc-2.fir
A flang/test/HLFIR/maxloc-elemental.fir
A flang/test/Lower/Intrinsics/cosd.f90
A flang/test/Lower/Intrinsics/sind.f90
A flang/test/Lower/Intrinsics/system-optional.f90
A flang/test/Lower/Intrinsics/system.f90
M flang/test/Lower/OpenACC/acc-data.f90
M flang/test/Lower/OpenACC/acc-kernels-loop.f90
M flang/test/Lower/OpenACC/acc-kernels.f90
M flang/test/Lower/OpenACC/acc-parallel-loop.f90
M flang/test/Lower/OpenACC/acc-parallel.f90
M flang/test/Lower/OpenACC/acc-serial-loop.f90
M flang/test/Lower/OpenACC/acc-serial.f90
M flang/test/Lower/OpenACC/acc-update.f90
M flang/test/Lower/OpenMP/FIR/if-clause.f90
M flang/test/Lower/OpenMP/FIR/loop-combined.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-aligned.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-linear.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-safelen.f90
A flang/test/Lower/OpenMP/Todo/omp-do-simd-simdlen.f90
M flang/test/Lower/OpenMP/if-clause.f90
M flang/test/Lower/OpenMP/loop-combined.f90
A flang/test/Semantics/execute_command_line.f90
M flang/test/Transforms/loop-versioning.fir
M flang/unittests/Evaluate/expression.cpp
M flang/unittests/Evaluate/folding.cpp
M flang/unittests/Evaluate/intrinsics.cpp
M flang/unittests/Runtime/CommandTest.cpp
M libc/cmake/modules/LLVMLibCArchitectures.cmake
M libc/src/math/generic/asinf.cpp
M libc/src/math/generic/sincosf.cpp
M libc/src/time/gpu/time_utils.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/stdio/sprintf_test.cpp
M libc/test/src/stdio/sscanf_test.cpp
M libcxx/src/filesystem/operations.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.contains/ranges.contains.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/find.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.fold/left_folds.pass.cpp
M libcxx/test/std/input.output/filesystems/fs.op.funcs/fs.op.remove_all/remove_all.pass.cpp
M libcxx/test/std/numerics/numeric.ops/numeric.ops.midpoint/midpoint.pointer.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/compare.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.chunk.by/range.chunk.by.iter/decrement.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/arrow.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/ctor.parent_iter.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/decrement.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/iterator/deref.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/base.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/compare.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/ctor.default.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/sentinel/ctor.parent.pass.cpp
M libcxx/test/std/ranges/range.adaptors/range.filter/types.h
M lldb/bindings/python/python-swigsafecast.swig
M lldb/bindings/python/python-wrapper.swig
M lldb/include/lldb/API/SBBreakpointName.h
M lldb/include/lldb/API/SBEvent.h
M lldb/include/lldb/API/SBStream.h
M lldb/include/lldb/Breakpoint/BreakpointName.h
M lldb/include/lldb/Breakpoint/BreakpointResolverScripted.h
M lldb/include/lldb/Interpreter/Interfaces/ScriptedInterface.h
A lldb/include/lldb/Interpreter/Interfaces/ScriptedThreadPlanInterface.h
M lldb/include/lldb/Interpreter/ScriptInterpreter.h
M lldb/include/lldb/Target/MemoryHistory.h
M lldb/include/lldb/Target/ThreadPlanPython.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/API/SBBreakpointOptionCommon.h
M lldb/source/Interpreter/ScriptInterpreter.cpp
M lldb/source/Plugins/ABI/X86/ABIWindows_x86_64.h
M lldb/source/Plugins/Architecture/Mips/ArchitectureMips.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/CMakeLists.txt
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPlatformPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedProcessPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedPythonInterface.h
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.cpp
A lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPlanPythonInterface.h
M lldb/source/Plugins/ScriptInterpreter/Python/Interfaces/ScriptedThreadPythonInterface.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/SWIGPythonBridge.h
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPython.cpp
M lldb/source/Plugins/ScriptInterpreter/Python/ScriptInterpreterPythonImpl.h
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Target/ThreadPlanPython.cpp
M lldb/test/API/functionalities/step_scripted/Steps.py
M lldb/test/API/functionalities/step_scripted/TestStepScripted.py
M lldb/test/API/functionalities/thread_plan/wrap_step_over.py
M lldb/unittests/Disassembler/x86/TestGetControlFlowKindx86.cpp
M lldb/unittests/ScriptInterpreter/Python/PythonTestSuite.cpp
M llvm/docs/CodeReview.rst
M llvm/docs/DeveloperPolicy.rst
M llvm/docs/GettingStarted.rst
M llvm/docs/MyFirstTypoFix.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/ADT/ArrayRef.h
M llvm/include/llvm/Frontend/Directive/DirectiveBase.td
M llvm/include/llvm/Frontend/HLSL/HLSLResource.h
M llvm/include/llvm/MC/MCDecoderOps.h
A llvm/include/llvm/Support/DXILABI.h
R llvm/include/llvm/Support/DXILOperationCommon.h
M llvm/include/llvm/Support/X86FoldTablesUtils.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/IR/ProfDataUtils.cpp
M llvm/lib/ProfileData/Coverage/CoverageMapping.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
M llvm/lib/Target/AArch64/AArch64InstrInfo.h
M llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
M llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PostLegalizerLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/DirectX/DXILOpBuilder.cpp
M llvm/lib/Target/DirectX/DXILResource.cpp
M llvm/lib/Target/DirectX/DXILResource.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchMCExpr.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoZicond.td
M llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
M llvm/lib/Target/SPIRV/CMakeLists.txt
M llvm/lib/Target/SPIRV/SPIRVCallLowering.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
A llvm/lib/Target/SPIRV/SPIRVMetadata.cpp
A llvm/lib/Target/SPIRV/SPIRVMetadata.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCTypeUtilities.h
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrFoldTables.cpp
M llvm/lib/Target/X86/X86InstrFoldTables.h
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Transforms/Scalar/BDCE.cpp
M llvm/lib/Transforms/Scalar/GVN.cpp
M llvm/lib/Transforms/Utils/PredicateInfo.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/VPRecipeBuilder.h
M llvm/lib/Transforms/Vectorize/VPlan.cpp
M llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
A llvm/test/CodeGen/AArch64/abs.ll
M llvm/test/CodeGen/AArch64/arm64-addrmode.ll
M llvm/test/CodeGen/AArch64/arm64-rev.ll
M llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll
M llvm/test/CodeGen/AArch64/fcmp.ll
M llvm/test/CodeGen/AArch64/large-offset-ldr-merge.mir
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
M llvm/test/CodeGen/RISCV/condbinops.ll
M llvm/test/CodeGen/RISCV/condops.ll
M llvm/test/CodeGen/RISCV/select-binop-identity.ll
M llvm/test/CodeGen/RISCV/select.ll
M llvm/test/CodeGen/RISCV/short-forward-branch-opt.ll
M llvm/test/CodeGen/RISCV/xaluo.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-i8-default-element-type.ll
A llvm/test/CodeGen/SPIRV/pointers/kernel-argument-ptr-no-bitcast.ll
A llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-i8-ptr-as-value-operand.ll
A llvm/test/CodeGen/SPIRV/pointers/store-kernel-arg-ptr-as-value-operand.ll
M llvm/test/CodeGen/X86/anyext.ll
M llvm/test/CodeGen/X86/fast-isel-store.ll
M llvm/test/CodeGen/X86/fixup-bw-copy.ll
M llvm/test/CodeGen/X86/mul-i1024.ll
M llvm/test/CodeGen/X86/mul-i256.ll
M llvm/test/CodeGen/X86/mul-i512.ll
M llvm/test/CodeGen/X86/mul64.ll
M llvm/test/CodeGen/X86/pmovsx-inreg.ll
M llvm/test/CodeGen/X86/sext-i1.ll
M llvm/test/CodeGen/X86/shift-amount-mod.ll
M llvm/test/CodeGen/X86/shift-and.ll
M llvm/test/CodeGen/X86/shift-combine.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/MC/AArch64/neon-diagnostics.s
M llvm/test/MC/AArch64/neon-scalar-shift-imm.s
M llvm/test/MC/Disassembler/AArch64/neon-instructions.txt
M llvm/test/MC/RISCV/rv32zicond-invalid.s
M llvm/test/MC/RISCV/rv32zicond-valid.s
A llvm/test/TableGen/trydecode-emission4.td
A llvm/test/Transforms/BDCE/binops-multiuse.ll
M llvm/test/Transforms/BDCE/dead-uses.ll
M llvm/tools/llvm-profdata/llvm-profdata.cpp
M llvm/unittests/Support/RISCVISAInfoTest.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
M llvm/utils/TableGen/AsmMatcherEmitter.cpp
M llvm/utils/TableGen/DXILEmitter.cpp
M llvm/utils/TableGen/DecoderEmitter.cpp
M mlir/docs/Dialects/Linalg/OpDSL.md
M mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td
M mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td
M mlir/include/mlir/IR/Dialect.h
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py
M mlir/test/Dialect/LLVMIR/invalid.mlir
M mlir/test/Dialect/LLVMIR/roundtrip.mlir
M mlir/test/Dialect/OpenACC/invalid.mlir
M mlir/test/Dialect/OpenACC/ops.mlir
M mlir/test/Dialect/Vector/vector-transfer-collapse-inner-most-dims.mlir
M mlir/unittests/Dialect/OpenACC/OpenACCOpsTest.cpp
M openmp/libomptarget/DeviceRTL/src/Parallelism.cpp
Log Message:
-----------
improve comments. update description (mention Efficient Test Coverage Measurement for MC/DC)
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/1d2470c2d676...e27ec318dab2
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