[all-commits] [llvm/llvm-project] ce72f7: [AMDGPU] Fix mul combine for MUL24 (#79110)

[Pierre van Houtryve via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: ce72f78f37199d693a65b6c7c1d637fafbb13727
      https://github.com/llvm/llvm-project/commit/ce72f78f37199d693a65b6c7c1d637fafbb13727
  Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
  Date:   2024-01-29 (Mon, 29 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
    M llvm/test/CodeGen/AMDGPU/reassoc-mul-add-1-to-mad.ll

  Log Message:
  -----------
  [AMDGPU] Fix mul combine for MUL24 (#79110)

MUL24 can now return a i64 for i32 operands, but the combine was never
updated to handle this case. Extend the operand when rewriting the ADD
to handle it.

Fixes SWDEV-436654