[all-commits] [llvm/llvm-project] d407e6: [RISCV] Add test to showcase miscompile from #79072

[Luke Lau via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: d407e6ca61a422f25841674d8f0b5ea0dbec85f8
      https://github.com/llvm/llvm-project/commit/d407e6ca61a422f25841674d8f0b5ea0dbec85f8
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll

  Log Message:
  -----------
  [RISCV] Add test to showcase miscompile from #79072


  Commit: 5cf9f2cd9888feea23a624c1de3cc37ce8ce8112
      https://github.com/llvm/llvm-project/commit/5cf9f2cd9888feea23a624c1de3cc37ce8ce8112
  Author: Luke Lau <luke at igalia.com>
  Date:   2024-01-26 (Fri, 26 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll

  Log Message:
  -----------
  [RISCV] Fix M1 shuffle on wrong SrcVec in lowerShuffleViaVRegSplitting

This fixes a miscompile from #79072 where we were taking the wrong SrcVec to do
the M1 shuffle. E.g. if the SrcVecIdx was 2 and we had 2 VRegsPerSrc, we ended
up taking it from V1 instead of V2.


Compare: https://github.com/llvm/llvm-project/compare/731c2049a4fa...5cf9f2cd9888