[all-commits] [llvm/llvm-project] df0835: [RISCV] Implement foward inserting save/restore FR...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Thu Jan 25 10:47:46 PST 2024
Branch: refs/heads/users/MaskRay/spr/elf-implement-r_riscv_tlsdesc-for-risc-v
Home: https://github.com/llvm/llvm-project
Commit: df08350dcfc515c5a7c08e1e08047467263cb701
https://github.com/llvm/llvm-project/commit/df08350dcfc515c5a7c08e1e08047467263cb701
Author: Yeting Kuo <46629943+yetingk at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
A llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
Log Message:
-----------
[RISCV] Implement foward inserting save/restore FRM instructions. (#77744)
Previously, RISCVInsertReadWriteCSR inserted an FRM swap for any value
other than 7 and restored the original value right after the vector
instruction. This is inefficient if multiple vector instructions use the
same rounding mode if the next vector instruction uses a different
explicit rounding mode.
This patch implements a local optimization to solve the above problem.
We assume the starting rounding mode of the basic block is "dynamic."
When iterating through a basic block and encountering an instruction
whose rounding mode is not the same as the current rounding mode, we
change the current rounding mode and save the current rounding mode if
needed. And we may need to restore FRM when encountering function call,
inline asm and some uses of FRM.
The advanced version of this is to perform cross basic block analysis
for the starting rounding mode of each basic block.
Commit: 90c326b198080c5c208f62f6755d54d7b69b291d
https://github.com/llvm/llvm-project/commit/90c326b198080c5c208f62f6755d54d7b69b291d
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
Log Message:
-----------
[AArch64] Fix gcc warning about mix of enumeral and non-enumeral types [NFC]
Change the return type of
findScratchNonCalleeSaveRegister
to Register instead of unsigned.
Every place the function is called we already put the returned value in a
Register variable or compare it with another Register.
This fixes some gcc warnings:
../lib/Target/AArch64/AArch64FrameLowering.cpp:744: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
743 | Register TargetReg = RealignmentPadding
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
744 | ? findScratchNonCalleeSaveRegister(&MBB)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
745 | : AArch64::SP;
|
../lib/Target/AArch64/AArch64FrameLowering.cpp:803: warning: enumeral and non-enumeral type in conditional expression [-Wextra]
802 | Register ScratchReg = RealignmentPadding
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
803 | ? findScratchNonCalleeSaveRegister(&MBB)
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
804 | : AArch64::SP;
|
Commit: 664a0faac464708fc061d12e5cd492fcbfea979a
https://github.com/llvm/llvm-project/commit/664a0faac464708fc061d12e5cd492fcbfea979a
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/Target/TargetInstrPredicate.td
M llvm/utils/TableGen/PredicateExpander.cpp
M llvm/utils/TableGen/PredicateExpander.h
Log Message:
-----------
[TableGen] Add predicates for immediates comparison (#76004)
These predicates can be used to represent `<`, `<=`, `>`, `>=`.
And a predicate for `in range` is added.
Commit: 7cedbfc31c332fa022bf2e1b0d72e5a9b6669ad3
https://github.com/llvm/llvm-project/commit/7cedbfc31c332fa022bf2e1b0d72e5a9b6669ad3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
Log Message:
-----------
[RISCV] Reformat riscv-target-features.c. NFC (#79409)
Indent line continuations by 2 spaces.
Drop -x c
Commit: f7a615a7d5a3a01d7d0ca46f8481248ef587cfe2
https://github.com/llvm/llvm-project/commit/f7a615a7d5a3a01d7d0ca46f8481248ef587cfe2
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll
Log Message:
-----------
ValueTracking: Use correct compare type in test
Commit: 122ed552fc5d5807f2a96b8456b42f5114cd1a79
https://github.com/llvm/llvm-project/commit/122ed552fc5d5807f2a96b8456b42f5114cd1a79
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachinePassManager.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/unittests/MIR/PassBuilderCallbacksTest.cpp
Log Message:
-----------
[CodeGen] Remove MachinePassKey (#79406)
We now use PassT::name to distinguish Passes.
Commit: 45d2d7757feb386186f69af6ef57bde7b5adc2db
https://github.com/llvm/llvm-project/commit/45d2d7757feb386186f69af6ef57bde7b5adc2db
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
Log Message:
-----------
[AMDGPU] New llvm.amdgcn.wave.id intrinsic (#79325)
This is only valid on targets with architected SGPRs.
Commit: e390c229a438ed1eb3396df8fbeeda89c49474e6
https://github.com/llvm/llvm-project/commit/e390c229a438ed1eb3396df8fbeeda89c49474e6
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lld/test/ELF/lto/ltopasses-custom.ll
M llvm/docs/Passes.rst
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CallBrPrepare.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Transforms/Scalar/FlattenCFGPass.cpp
M llvm/lib/Transforms/Scalar/LowerAtomicPass.cpp
M llvm/lib/Transforms/Utils/FlattenCFG.cpp
M llvm/lib/Transforms/Utils/LowerInvoke.cpp
M llvm/test/CodeGen/AArch64/callbr-prepare.ll
M llvm/test/Feature/optnone-opt.ll
M llvm/test/Other/new-pass-manager.ll
M llvm/test/ThinLTO/X86/cache-config.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/IndVarSimplify/X86/iv-widen.ll
M llvm/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
M llvm/test/Transforms/IndVarSimplify/sharpen-range.ll
M llvm/test/Transforms/LICM/argmemonly-call.ll
M llvm/test/Transforms/LICM/assume.ll
M llvm/test/Transforms/LICM/basictest.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/crash.ll
M llvm/test/Transforms/LICM/dbg-value-sink.ll
M llvm/test/Transforms/LICM/debug-value.ll
M llvm/test/Transforms/LICM/extra-copies.ll
M llvm/test/Transforms/LICM/fence.ll
M llvm/test/Transforms/LICM/funclet.ll
M llvm/test/Transforms/LICM/guards.ll
M llvm/test/Transforms/LICM/hoist-round.ll
M llvm/test/Transforms/LICM/invariant.start.ll
M llvm/test/Transforms/LICM/lcssa-ssa-promoter.ll
M llvm/test/Transforms/LICM/no-preheader-test.ll
M llvm/test/Transforms/LICM/opt-remarks-conditional-load.ll
M llvm/test/Transforms/LICM/opt-remarks-intervening-store.ll
M llvm/test/Transforms/LICM/opt-remarks.ll
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/promote-order.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
M llvm/test/Transforms/LICM/scalar-promote-memmodel.ll
M llvm/test/Transforms/LICM/scalar-promote-unwind.ll
M llvm/test/Transforms/LICM/scalar-promote.ll
M llvm/test/Transforms/LICM/speculate.ll
M llvm/test/Transforms/LICM/store-hoisting.ll
M llvm/test/Transforms/LICM/volatile-alias.ll
M llvm/test/Transforms/LoopIdiom/nontemporal_store.ll
M llvm/test/Transforms/LoopRotate/RISCV/invalid-cost.ll
M llvm/test/Transforms/LoopRotate/basic.ll
M llvm/test/Transforms/LoopRotate/call-prepare-for-lto.ll
M llvm/test/Transforms/LoopRotate/noalias.ll
M llvm/test/Transforms/LoopStrengthReduce/ivchain.ll
M llvm/test/Transforms/LowerAtomic/atomic-load.ll
M llvm/test/Transforms/LowerAtomic/atomic-swap.ll
M llvm/test/Transforms/LowerAtomic/barrier.ll
M llvm/test/Transforms/LowerInvoke/2003-12-10-Crash.ll
M llvm/test/Transforms/LowerInvoke/lowerinvoke.ll
M llvm/test/Transforms/LowerSwitch/2003-05-01-PHIProblem.ll
M llvm/test/Transforms/LowerSwitch/2003-08-23-EmptySwitch.ll
M llvm/test/Transforms/LowerSwitch/2004-03-13-SwitchIsDefaultCrash.ll
M llvm/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll
M llvm/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll
M llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll
M llvm/test/Transforms/LowerSwitch/condition-phi-unreachable-default.ll
M llvm/test/Transforms/LowerSwitch/delete-default-block-crash.ll
M llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll
M llvm/test/Transforms/LowerSwitch/feature.ll
M llvm/test/Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll
M llvm/test/Transforms/LowerSwitch/phi-in-dead-block.ll
M llvm/test/Transforms/LowerSwitch/pr59316.ll
M llvm/test/Transforms/StructurizeCFG/switch.ll
M llvm/test/Transforms/UnifyFunctionExitNodes/unreachable-blocks-status.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
A llvm/test/Transforms/Util/flatten-cfg.ll
R llvm/test/Transforms/Util/flattencfg.ll
M llvm/test/Transforms/Util/lowerinvoke-funclet.ll
M llvm/test/Transforms/Util/lowerswitch.ll
M llvm/test/tools/llvm-lto2/X86/pipeline.ll
Log Message:
-----------
[Pass] Add hyphen to some pass names (#74287)
Here is the list of the renamed passes:
- `callbrprepare` -> `callbr-prepare`
- `dwarfehprepare` -> `dwarf-eh-prepare`
- `flattencfg` -> `flatten-cfg`
- `loweratomic` -> `lower-atomic`
- `lowerinvoke` -> `lower-invoke`
- `lowerswitch` -> `lower-switch`
- `winehprepare` -> `win-eh-prepare`
- `targetir` -> `target-ir`
- `targetlibinfo` -> `target-lib-info`
Legacy passes are not affected.
Commit: a46422a77668be6ce10d229480c720035056f4b3
https://github.com/llvm/llvm-project/commit/a46422a77668be6ce10d229480c720035056f4b3
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll
M llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll
Log Message:
-----------
Reapply "ValueTracking: Identify implied fp classes by general fcmp (#66505)"
This reverts commit 0d0c2298552222b049fa3b8db5efef4b161e51e9.
Includes a bug fix for fcmp one handling, as well as for positive constants.
Commit: 2c49586e1b9ab917877a6af8e1669854899687d3
https://github.com/llvm/llvm-project/commit/2c49586e1b9ab917877a6af8e1669854899687d3
Author: David Green <david.green at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
Log Message:
-----------
[ARM] Fix MVEFloatOps check on creating VCVTN (#79291)
In the past PerformSplittingToNarrowingStores handled both int and float
ops, but since the introduction of MVETRUNC now only operates on float
operations, creating VCVTN nodes. It should be guarded by hasMVEFloatOps
to prevent a failure to select.
Commit: 41fe98a6e7e5cdcab4a4e9e0d09339231f480c01
https://github.com/llvm/llvm-project/commit/41fe98a6e7e5cdcab4a4e9e0d09339231f480c01
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/test/TableGen/address-space-patfrags.td
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
Log Message:
-----------
[TableGen] Use MapVector to remove non-determinism
This fixes found non-determinism when `LLVM_REVERSE_ITERATION`
option is `ON`.
Fixes #79420.
Reviewers: ilovepi, MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/79411
Commit: fa13c3eea7fbc34310f2fb602aa7f0983d5a0ea4
https://github.com/llvm/llvm-project/commit/fa13c3eea7fbc34310f2fb602aa7f0983d5a0ea4
Author: Guray Ozen <guray.ozen at gmail.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
Log Message:
-----------
[mlir][nvgpu] Fix `transposeB` in `nvgpu.warpgroup.mma` (#79271)
The #76150 fixed meaning of `transposeB` in NVVM dialect which was
initially implemented with opposite meaning.
This PR fixes the lowering of `nvgpu.warpgroup.mma` to NVVM dialect.
This will fix two integration tests:
gemm_f32_f16_f16_128x128x128.mlir
gemm_pred_f32_f16_f16_128x128x128.mlir
Commit: d5c9d402f07e7448cd46870a59d981f582682548
https://github.com/llvm/llvm-project/commit/d5c9d402f07e7448cd46870a59d981f582682548
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
Log Message:
-----------
[AMDGPU] Fix warnings about unused variables [NFC]
Without this gcc warned like
../lib/Target/AMDGPU/GCNDPPCombine.cpp:371: warning: unused variable 'OpSelOpr' [-Wunused-variable]
371 | if (auto *OpSelOpr =
|
../lib/Target/AMDGPU/GCNDPPCombine.cpp:388: warning: unused variable 'OpSelHiOpr' [-Wunused-variable]
388 | if (auto *OpSelHiOpr =
|
Remove the unused variables.
Commit: a15ebe0246c75faedfe9cb2fbc6ea7b62e265026
https://github.com/llvm/llvm-project/commit/a15ebe0246c75faedfe9cb2fbc6ea7b62e265026
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/test/Fir/boxproc-2.fir
Log Message:
-----------
[flang] fix procedure fir.box_addr identification in boxed-procedure (#79290)
The pass was mistakenly identifying a fir.box_addr on a
fir.box/fir.class of a derived type with procedure pointer components as
being a fir.box_addr on a procedure.
Simply check if the input type is a fir.box_proc or function type (if
input already rewritten) and insert convert only in this case.
This caused "invalid fir.convert" internal error.
Commit: 1a14c446dd800b1d79fed1735c48e392d06e495d
https://github.com/llvm/llvm-project/commit/1a14c446dd800b1d79fed1735c48e392d06e495d
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32zaamo-invalid.s
M llvm/test/MC/RISCV/rv32zaamo-valid.s
M llvm/test/MC/RISCV/rv32zalrsc-invalid.s
M llvm/test/MC/RISCV/rv32zalrsc-valid.s
M llvm/test/MC/RISCV/rv64zaamo-invalid.s
M llvm/test/MC/RISCV/rv64zaamo-valid.s
M llvm/test/MC/RISCV/rv64zalrsc-invalid.s
M llvm/test/MC/RISCV/rv64zalrsc-valid.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV][MC] Add experimental support of Zaamo and Zalrsc
`A` extension has been split into two parts: Zaamo (Atomic Memory
Operations) and Zalrsc (Load-Reserved/Store-Conditional). See also
https://github.com/riscv/riscv-zaamo-zalrsc.
This patch adds the MC support.
Reviewers: dtcxzyw, topperc, kito-cheng
Reviewed By: topperc
Pull Request: https://github.com/llvm/llvm-project/pull/78970
Commit: 3fdb431b636975f2062b1931158aa4dfce6a3ff1
https://github.com/llvm/llvm-project/commit/3fdb431b636975f2062b1931158aa4dfce6a3ff1
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
R llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
R llvm/lib/Target/RISCV/RISCVMacroFusion.h
A llvm/lib/Target/RISCV/RISCVMacroFusion.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
Log Message:
-----------
[RISCV] Use TableGen-based macro fusion (#72224)
We convert existed macro fusions to TableGen.
Bacause `Fusion` depend on `Instruction` definitions which is defined
below `RISCVFeatures.td`, so we recommend user to add fusion features
when defining new processor.
Commit: 50cc07f1bc3e4527a51b0aed6cf0479e87d61f37
https://github.com/llvm/llvm-project/commit/50cc07f1bc3e4527a51b0aed6cf0479e87d61f37
Author: Danial Klimkin <dklimkin at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
Log Message:
-----------
Fix bazel build past 72ce6294157964042b7ed5576ce2c99257eeea9d (#79424)
Commit: 12a8bc09ca4fa975d3e79a05e1fb14f03b23e3d5
https://github.com/llvm/llvm-project/commit/12a8bc09ca4fa975d3e79a05e1fb14f03b23e3d5
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
A llvm/include/llvm/CodeGen/FreeMachineFunction.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/lib/CodeGen/CMakeLists.txt
A llvm/lib/CodeGen/FreeMachineFunction.cpp
M llvm/lib/CodeGen/MachinePassManager.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/tools/llc/NewPMDriver.cpp
Log Message:
-----------
[CodeGen] Port FreeMachineFunction to new pass manager (#79421)
This pass should be the last machine function pass in pipeline, also
ignore `PI.runAfterPass(*P, MF, PassPA);` to avoid accessing a dangling
reference.
Commit: 03cf0e9354e7e56ff794e9efb682ed2971bc91ec
https://github.com/llvm/llvm-project/commit/03cf0e9354e7e56ff794e9efb682ed2971bc91ec
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/test/Driver/fveclib.c
Log Message:
-----------
[LTO] Fix Veclib flags correctly pass to LTO flags (#78749)
Flags `-fveclib=name` were not passed to LTO flags.
This pass fixes that by converting the `-fveclib` flags to their
relevant names for opt's `-vector-lib=name` flags.
For example:
`-fveclib=SLEEF` would become `-vector-library=sleefgnuabi` and passed
through the `-plugin-opt` flag.
Commit: f9dc0b6c8a6804a78e88c44018d6148bdf4c64c3
https://github.com/llvm/llvm-project/commit/f9dc0b6c8a6804a78e88c44018d6148bdf4c64c3
Author: Danial Klimkin <dklimkin at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Fix bazel build past 3fdb431b636975f2062b1931158aa4dfce6a3ff1 (#79429)
Commit: 45fec0c110cccd5e0c9b60d51bc2ffc1645c9a40
https://github.com/llvm/llvm-project/commit/45fec0c110cccd5e0c9b60d51bc2ffc1645c9a40
Author: Daniil Dudkin <unterumarmung at yandex.ru>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang-tools-extra/clang-apply-replacements/lib/Tooling/ApplyReplacements.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/yml-basic/basic.h
A clang-tools-extra/test/clang-apply-replacements/Inputs/yml-basic/file1.yml
A clang-tools-extra/test/clang-apply-replacements/Inputs/yml-basic/file2.yml
A clang-tools-extra/test/clang-apply-replacements/yml-basic.cpp
Log Message:
-----------
[clang-apply-replacements] Add support for the `.yml` file extension (#78842)
The `.yml` file extension is a valid extension for the YAML files, but
it was not previously supported by the Clang Apply Replacements tool.
This commit adds support for processing `.yml` files. Without this
change, running the tool on a folder containing `.yml` files generated
by clang-tidy would have no effect.
Commit: 5cc0f76d34c7d00fa3e4ff01efe24d5de592e82c
https://github.com/llvm/llvm-project/commit/5cc0f76d34c7d00fa3e4ff01efe24d5de592e82c
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
M mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/lib/IR/TestClone.cpp
M mlir/test/lib/Transforms/TestConstantFold.cpp
Log Message:
-----------
[mlir][IR] Add rewriter API for moving operations (#78988)
The pattern rewriter documentation states that "*all* IR mutations [...]
are required to be performed via the `PatternRewriter`." This commit
adds two functions that were missing from the rewriter API:
`moveOpBefore` and `moveOpAfter`.
After an operation was moved, the `notifyOperationInserted` callback is
triggered. This allows listeners such as the greedy pattern rewrite
driver to react to IR changes.
This commit narrows the discrepancy between the kind of IR modification
that can be performed and the kind of IR modifications that can be
listened to.
Commit: bcd14b099dd3d0b9c9336e5cdf7e35279c5cc33b
https://github.com/llvm/llvm-project/commit/bcd14b099dd3d0b9c9336e5cdf7e35279c5cc33b
Author: Kohei Yamaguchi <fix7211 at gmail.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/test/Dialect/Bufferization/canonicalize.mlir
Log Message:
-----------
[mlir][bufferization] Fix SimplifyClones with dealloc before cloneOp (#79098)
The SimplifyClones pass relies on the assumption that the deallocOp
follows the cloneOp. However, a crash occurs when there is a
redundantDealloc preceding the cloneOp. This PR addresses the issue by
ensuring the presence of deallocOp after cloneOp. The verification is
performed by checking if the loop of the sub sequent node of cloneOp
reaches the tail of the list.
Fix #74306
Commit: e4375bf47fafb0cfcb2288ecfad94dfe63ca994c
https://github.com/llvm/llvm-project/commit/e4375bf47fafb0cfcb2288ecfad94dfe63ca994c
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
Log Message:
-----------
[X86] Fix warning about unused variable [NFC]
Without this gcc complains like
../lib/Target/X86/X86FixupVectorConstants.cpp:70:13: warning: unused variable 'CUndef' [-Wunused-variable]
70 | if (auto *CUndef = dyn_cast<UndefValue>(C))
| ^~~~~~
Remove the unused variable and change dyn_cast to isa.
Commit: 2aa8945d5957b25473c42e9edc6788ae54bb1f2f
https://github.com/llvm/llvm-project/commit/2aa8945d5957b25473c42e9edc6788ae54bb1f2f
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU][NFC] Use templates to decode AV operands. (#79313)
Eliminates the need to define them manually.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Commit: 4b8e55cb04e68053a80f4ee26f4efbf08fe30b02
https://github.com/llvm/llvm-project/commit/4b8e55cb04e68053a80f4ee26f4efbf08fe30b02
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSDIRInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VINTERPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
Log Message:
-----------
[AMDGPU][AsmParser][NFC] Rename integer modifier operands to follow the convention. (#79284)
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Commit: 223d3dabc8b75a75276ef0544132ba0df4498fb3
https://github.com/llvm/llvm-project/commit/223d3dabc8b75a75276ef0544132ba0df4498fb3
Author: David Green <david.green at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/Utils.h
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
A flang/test/HLFIR/minloc-elemental.fir
M flang/test/Transforms/simplifyintrinsics.fir
Log Message:
-----------
[Flang] Minloc elemental intrinsic lowering (#74828)
Currently the lowering of a minloc intrinsic with a mask will look something
like:
%e = hlfir.elemental %shape ({
...
})
%m = hlfir.minloc %array mask %e
hlfir.assign %m to %result
hlfir.destroy %m
The elemental will be expanded into a temporary+loop, the minloc into a
FortranAMinloc call (which hopefully gets simplified to a specialized call that
can be inlined at the call site), and the assign might get expanded to a
FortranAAssign. It would be better to generate the entire construct as single
loop if we can - one that performs the minloc calculation with the mask
elemental computed inline.
This patch attempt to do that, adding a hlfir version of the expansion code
from SimplifyIntrinsics that turns an minloc+elemental into a single combined
loop nest. It attempts to reuse the methods in genMinlocReductionLoop for
constructing the loop with a modified loop body. The declaration for the
function is currently in Optimizer/Support/Utils.h, but there might be a better
place for it.
It is added as part of the OptimizedBufferizationPass, like the
similar count/any/all that have been added recently.
Commit: f4ed7f8d0a3830d05e53476fc64966e871bf9454
https://github.com/llvm/llvm-project/commit/f4ed7f8d0a3830d05e53476fc64966e871bf9454
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
Log Message:
-----------
[clang][Parse][NFC] Make a local variable const
Commit: a04f6152914ea21f3068aaba9d8fc21d2e703d3e
https://github.com/llvm/llvm-project/commit/a04f6152914ea21f3068aaba9d8fc21d2e703d3e
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Transforms/LoopVectorize/vplan-native-inner-loop-only.ll
Log Message:
-----------
[LV] Check for innermost loop instead of EnableVPlanNativePath in CM.
Replace EnableVPlanNativePath checks in the cost-model by assertions
that the code is only called for innermost loops. This ensures that the
cost model isn't used in the VPlanNativePath, which is only used for
outer-loop vectorization.
Even with EnableVPlanNativePath, inner loops are processed by the
inner loop vectorization path, not the native path, so checking for
EnableVPlanNativePath may impact decisions for inner loops and can
cause crashes, like in the attached test case.
Commit: e5e1a8931044fe384f222fe0af4a1de595b941a3
https://github.com/llvm/llvm-project/commit/e5e1a8931044fe384f222fe0af4a1de595b941a3
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
Log Message:
-----------
[gn] port 12a8bc09ca4f
Commit: 8252137b9a6b909c308123f64a41d1fff6fdcbca
https://github.com/llvm/llvm-project/commit/8252137b9a6b909c308123f64a41d1fff6fdcbca
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/test/Lower/structure-constructors-alloc-comp.f90
Log Message:
-----------
[flang] Lower struct ctor with character allocatable components (#79179)
There is no need to gather the length parameters from the parameter
symbols when facing a deferred length allocatable components in a
structure constructor, the length is set as part of the assignment given
the value.
Remove the checks for derived type runtime info symbols, this is not
relevant for what is being tested here.
Commit: 3490f037c3c750416ad224147b32c92bf6c7db0f
https://github.com/llvm/llvm-project/commit/3490f037c3c750416ad224147b32c92bf6c7db0f
Author: Danial Klimkin <dklimkin at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
Log Message:
-----------
More bazel fixes past 72ce6294157964042b7ed5576ce2c99257eeea9d (#79442)
Commit: 47a2e732100c4102a1a5f3243123638f157c9a2a
https://github.com/llvm/llvm-project/commit/47a2e732100c4102a1a5f3243123638f157c9a2a
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/Instruction.h
M llvm/lib/IR/Instruction.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Make getDbgValueRange inlineable (#79331)
`getDbgValueRange` is the replacement of a common LLVM idiom of:
1) Am I currently looking at a `DbgVariableIntrinsic` instruction?
2) Let's do something special with it!
We instead iterate over the range of DPValues attached to an instruction
and do special things with those. Unfortunately in the common case of
"there is no debug-info", this generates a spurious function call that's
paid by non-debug builds.
To get around this, make `getDbgValueRange` inlineable so that the "`if
(DbgMarker)`" test can be inlined and guard the more expensive call. The
false path should be optimisable-awayable to skipping the loop. However,
due to header inclusion order we can't just make
`Instruction::getDbgValueRange` inline because `DPMarker` hasn't been
declared yet. So, define an inlinable function in the llvm:: namespace
and pre-declare it -- the eventual code should be inlineable almost 100%
of the time.
Commit: cd0b0055a730e55f2f14f35172e05dc27642f8ce
https://github.com/llvm/llvm-project/commit/cd0b0055a730e55f2f14f35172e05dc27642f8ce
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp][NFC] Add some working _Complex tests
Commit: 215b8f1e252b4f30cf1b734faa370c0ac4b88659
https://github.com/llvm/llvm-project/commit/215b8f1e252b4f30cf1b734faa370c0ac4b88659
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/LegacyPassManager.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
M llvm/test/LTO/X86/pr38046.ll
M llvm/test/Linker/debug-info-use-before-def.ll
M llvm/test/Linker/thinlto_funcimport_debug.ll
M llvm/test/ThinLTO/X86/debuginfo-cu-import.ll
M llvm/test/ThinLTO/X86/pr35472.ll
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/llvm-lto/llvm-lto.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs] Convert debug-info modes when loading bitcode (#78967)
As part of eliminating debug-intrinsics in LLVM, we'll shortly be
pushing the conversion from "old" dbg.value mode to "new" DPValue mode
out from when the pass manager runs, to when modules are loaded. This
patch adds that conversion process and some (temporary) options to
llvm-lto{,2} to help test it.
Specifically: now whenever we load a bitcode module, consider a flag of
whether to "upgrade" it into the new debug-info mode, and if we're
lazily materializing functions then do that lazily too. Doing this
exposes an error in the IRLinker/materializer handling of DPValues,
where we need to transfer the debug-info format flag correctly, and in
ValueMapper we need to remap the Values that DPValues point at.
I've added some test coverage in the modified tests; these will be
exercised by our llvm-new-debug-iterators buildbot.
This upgrading of debug-info won't be happening for the llvm18 release,
instead we'll turn it on after the branch date, thenbe push the boundary
of where "new" debug-info starts and ends down into the existing
debug-info upgrade path over the course of the next release.
Commit: b0b7be2701845484f92295daa95b80a13e24f9b2
https://github.com/llvm/llvm-project/commit/b0b7be2701845484f92295daa95b80a13e24f9b2
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU][NFC] Rename the reg-or-imm operand predicates to match their class names. (#79439)
No need to have two names for the same thing. Also simplifies operand
definitions.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Commit: 202917f86ebcbed5c8bc10e0cc7cce820747e3cb
https://github.com/llvm/llvm-project/commit/202917f86ebcbed5c8bc10e0cc7cce820747e3cb
Author: David Green <david.green at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M flang/include/flang/Optimizer/Support/Utils.h
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
Log Message:
-----------
[Flang] Move genMinMaxlocReductionLoop to a common location.
The shared library build doesn't like references of genMinMaxlocReductionLoop,
in Optimizer/Transforms, from HLFIR/Optimizer/Transforms. For the moment I've
moved the code to the header file where it can be shared, like other methods in
Utils.h
Commit: 71c52e4236a9eb586a9271240442c5dbfce17488
https://github.com/llvm/llvm-project/commit/71c52e4236a9eb586a9271240442c5dbfce17488
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn build] Port 3fdb431b6369
Commit: 45cc2a19cad7c3b180da67a27199fb5a1e17a71f
https://github.com/llvm/llvm-project/commit/45cc2a19cad7c3b180da67a27199fb5a1e17a71f
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/RISCV/BUILD.gn
Log Message:
-----------
[gn] port 12a8bc0 more
The test reaches into internal headers. Make sure generated files
are ready for that.
(This is the only place. If there were more, we should use public_deps
instead.)
Commit: a04d4a03f7737202b5cd05687e08ed8748ef7352
https://github.com/llvm/llvm-project/commit/a04d4a03f7737202b5cd05687e08ed8748ef7352
Author: John Brawn <john.brawn at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopFlatten.cpp
M llvm/test/Transforms/LoopFlatten/loop-flatten-negative.ll
A llvm/test/Transforms/LoopFlatten/loop-flatten-version.ll
M llvm/test/Transforms/LoopFlatten/widen-iv.ll
Log Message:
-----------
[LoopFlatten] Use loop versioning when overflow can't be disproven (#78576)
Implement the TODO in loop flattening to version the loop when we can't
prove that the trip count calculation won't overflow.
Commit: c3f7fb1421e1dbf2fb1d5594bfa801489bdab421
https://github.com/llvm/llvm-project/commit/c3f7fb1421e1dbf2fb1d5594bfa801489bdab421
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Bitcode/Reader/BitcodeReader.cpp
M llvm/lib/IR/LegacyPassManager.cpp
M llvm/lib/Linker/IRMover.cpp
M llvm/lib/Transforms/Utils/ValueMapper.cpp
M llvm/test/LTO/X86/pr38046.ll
M llvm/test/Linker/debug-info-use-before-def.ll
M llvm/test/Linker/thinlto_funcimport_debug.ll
M llvm/test/ThinLTO/X86/debuginfo-cu-import.ll
M llvm/test/ThinLTO/X86/pr35472.ll
M llvm/tools/llvm-link/llvm-link.cpp
M llvm/tools/llvm-lto/llvm-lto.cpp
M llvm/tools/llvm-lto2/llvm-lto2.cpp
Log Message:
-----------
Revert "[DebugInfo][RemoveDIs] Convert debug-info modes when loading bitcode (#78967)"
This reverts commit 215b8f1e252b4f30cf1b734faa370c0ac4b88659.
Numerous builders exploded from this X_X, for example
https://lab.llvm.org/buildbot/#/builders/46/builds/62657
Commit: 6fe21bc1dac883efa0dfa807f327048ae9969b81
https://github.com/llvm/llvm-project/commit/6fe21bc1dac883efa0dfa807f327048ae9969b81
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
Log Message:
-----------
[SLP]Fix PR79229: Do not erase extractelement, if it used in
multiregister node.
If the node can be span between several registers and same
extractelement instruction is used in several parts, it may be required
to keep such extractelement instruction to avoid compiler crash.
Commit: ee15e2bd32a4677c40d927c732b26d33f88d7865
https://github.com/llvm/llvm-project/commit/ee15e2bd32a4677c40d927c732b26d33f88d7865
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/lib/AST/AttrDocTable.cpp
Log Message:
-----------
[clang] Silence warning when building with MSVC targetting x86
This fixes:
```
[3786/6996] Building CXX object tools\clang\lib\AST\CMakeFiles\obj.clangAST.dir\AttrDocTable.cpp.obj
C:\git\llvm-project\clang\lib\AST\AttrDocTable.cpp(24): warning C4018: '<': signed/unsigned mismatch
```
Commit: 419d6ea135dd205e1eaab368a58ae14f9f52f699
https://github.com/llvm/llvm-project/commit/419d6ea135dd205e1eaab368a58ae14f9f52f699
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/lib/CodeGen/CGExpr.cpp
Log Message:
-----------
[clang] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[3963/6996] Building CXX object tools\clang\lib\CodeGen\CMakeFiles\obj.clangCodeGen.dir\CGExpr.cpp.obj
C:\git\llvm-project\clang\lib\CodeGen\CGExpr.cpp(3808): warning C4018: '<=': signed/unsigned mismatch
```
Commit: f33f5a04e9feeb9b473694825d84da8322f87df9
https://github.com/llvm/llvm-project/commit/f33f5a04e9feeb9b473694825d84da8322f87df9
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang-tools-extra/clangd/InlayHints.cpp
Log Message:
-----------
[clangd] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[5240/6995] Building CXX object tools\clang\tools\extra\clangd\CMakeFiles\obj.clangDaemon.dir\InlayHints.cpp.obj
C:\git\llvm-project\clang-tools-extra\clangd\InlayHints.cpp(1098): warning C4018: '<': signed/unsigned mismatch
```
Commit: 3fec25c55f1890c138e64548dc074b4593e0a26c
https://github.com/llvm/llvm-project/commit/3fec25c55f1890c138e64548dc074b4593e0a26c
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lld/COFF/PDB.cpp
Log Message:
-----------
[LLD] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[5383/6995] Building CXX object tools\lld\COFF\CMakeFiles\lldCOFF.dir\PDB.cpp.obj
C:\git\llvm-project\lld\COFF\PDB.cpp(835): warning C4018: '>=': signed/unsigned mismatch
```
Commit: 452a2c6e3575d56a34c34472b9f829cb17e2b564
https://github.com/llvm/llvm-project/commit/452a2c6e3575d56a34c34472b9f829cb17e2b564
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
Log Message:
-----------
[llvm] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[1614/6998] Building CXX object lib\ExecutionEngine\Orc\CMakeFiles\LLVMOrcJIT.dir\MachOPlatform.cpp.obj
C:\git\llvm-project\llvm\include\llvm/ExecutionEngine/Orc/MachOBuilder.h(367): warning C4334: '<<': result of 32-bit shift implicitly converted to 64 bits (was 64-bit shift intended?)
```
Commit: 3db3e2cea321aba58fcf1905e06a92567e892588
https://github.com/llvm/llvm-project/commit/3db3e2cea321aba58fcf1905e06a92567e892588
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Object/DXContainer.cpp
Log Message:
-----------
[llvm] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[1265/6998] Building CXX object lib\Object\CMakeFiles\LLVMObject.dir\DXContainer.cpp.obj
C:\git\llvm-project\llvm\lib\Object\DXContainer.cpp(344): warning C4018: '<': signed/unsigned mismatch
```
Commit: f42f551d12466c5f17f91cb44592e8dcb4118f07
https://github.com/llvm/llvm-project/commit/f42f551d12466c5f17f91cb44592e8dcb4118f07
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/ObjectYAML/COFFYAML.cpp
Log Message:
-----------
[llvm] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[1304/6998] Building CXX object lib\ObjectYAML\CMakeFiles\LLVMObjectYAML.dir\COFFYAML.cpp.obj
C:\git\llvm-project\llvm\lib\ObjectYAML\COFFYAML.cpp(561): warning C4018: '<': signed/unsigned mismatch
```
Commit: 03e4070ce1f834eb426aa8f8622838c40ff5c710
https://github.com/llvm/llvm-project/commit/03e4070ce1f834eb426aa8f8622838c40ff5c710
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
Log Message:
-----------
[lldb] Silence warning when building with Clang ToT
This fixes:
```
[6331/7452] Building CXX object tools\lldb\source\Plugins\Language\CPlusPlus\CMakeFiles\lldbPluginCPlusPlusLanguage.dir\LibCxx.cpp.obj
C:\git\llvm-project\lldb\source\Plugins\Language\CPlusPlus\LibCxx.cpp(1108,38): warning: format specifies type 'long' but the argument has type 'std::time_t' (aka 'long long') [-Wformat]
1108 | stream.Printf("timestamp=%ld s", seconds);
| ~~~ ^~~~~~~
| %lld
C:\git\llvm-project\lldb\source\Plugins\Language\CPlusPlus\LibCxx.cpp(1116,63): warning: format specifies type 'long' but the argument has type 'std::time_t' (aka 'long long') [-Wformat]
1116 | stream.Printf("date/time=%s timestamp=%ld s", str.data(), seconds);
| ~~~ ^~~~~~~
| %lld
2 warnings generated.
```
Commit: 40dcf24522af91ab22af2e69f28d1f1d2a860f5c
https://github.com/llvm/llvm-project/commit/40dcf24522af91ab22af2e69f28d1f1d2a860f5c
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/tests/sanitizer_bitvector_test.cpp
Log Message:
-----------
[compiler-rt] Silence warning when building with Clang ToT
This fixes:
```
[24/47] Generating SANITIZER_TEST_OBJECTS.sanitizer_bitvector_test.cpp.i386.o
C:/git/llvm-project/compiler-rt/lib/sanitizer_common/tests/sanitizer_bitvector_test.cpp:74:29: warning: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'value_type' (aka 'unsigned long') [-Wformat]
74 | fprintf(stderr, "%zu ", *it);
| ~~~ ^~~
| %lu
1 warning generated.
```
Commit: af263ceb90b9fe39ae1d3458c9f35b6b199d3951
https://github.com/llvm/llvm-project/commit/af263ceb90b9fe39ae1d3458c9f35b6b199d3951
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lld/ELF/MapFile.cpp
Log Message:
-----------
[LLD][ELF] Silence warning when building with Clang ToT
This fixes:
```
[5839/7452] Building CXX object tools\lld\ELF\CMakeFiles\lldELF.dir\MapFile.cpp.obj
C:\git\llvm-project\lld\ELF\MapFile.cpp(124,38): warning: comparison of integers of different signs: 'uint32_t' (aka 'unsigned int') and 'const ssize_t' (aka 'const int') [-Wsign-compare]
124 | last.outputOff + last.size == p.outputOff) {
| ~~~~~~~~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~
1 warning generated.
```
Commit: 43ab40a5baba4945efa6d6050ae34817c8044ebf
https://github.com/llvm/llvm-project/commit/43ab40a5baba4945efa6d6050ae34817c8044ebf
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Object/ELFObjectFile.cpp
Log Message:
-----------
[llvm] Silence warning when building with Clang ToT
This fixes:
```
[1343/7452] Building CXX object lib\Object\CMakeFiles\LLVMObject.dir\ELFObjectFile.cpp.obj
C:\git\llvm-project\llvm\lib\Object\ELFObjectFile.cpp(808,27): warning: comparison of integers of different signs: 'unsigned int' and '_Iter_diff_t<const Elf_Shdr_Impl<ELFType<llvm::endianness::little, false>> *>' (aka 'int') [-Wsign-compare]
808 | if (*TextSectionIndex != std::distance(Sections.begin(), *TextSecOrErr))
| ~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
C:\git\llvm-project\llvm\lib\Object\ELFObjectFile.cpp(913,12): note: in instantiation of function template specialization 'readBBAddrMapImpl<llvm::object::ELFType<llvm::endianness::little, false>>' requested here
913 | return readBBAddrMapImpl(Obj->getELFFile(), TextSectionIndex, PGOAnalyses);
| ^
```
Commit: ca0e2417912d8dea49c053186402aafe1ac8995a
https://github.com/llvm/llvm-project/commit/ca0e2417912d8dea49c053186402aafe1ac8995a
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M openmp/runtime/src/kmp_os.h
Log Message:
-----------
[openmp] Silence warning when compiling with MSVC targetting x86
This fixes:
```
[3593/7449] Building CXX object projects\openmp\runtime\src\CMakeFiles\omp.dir\kmp_debug.cpp.obj
C:\git\llvm-project\openmp\runtime\src\kmp_os.h(471): warning C4163: '_InlineInterlockedExchange64': not available as an intrinsic function
```
Commit: ad3cda7a04d4858816cbf38df63dc86d370c2587
https://github.com/llvm/llvm-project/commit/ad3cda7a04d4858816cbf38df63dc86d370c2587
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp
M mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir
Log Message:
-----------
[mlir][tensor] Enhance SimplifyUnPackToCollapseShape for unit dim cases. (#79262)
Commit: 43e46c546a1f0c7c3e436104a974560c6a2e5188
https://github.com/llvm/llvm-project/commit/43e46c546a1f0c7c3e436104a974560c6a2e5188
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/test/CXX/drs/dr4xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add test for CWG472 (#67948)
https://cplusplus.github.io/CWG/issues/472.html
It has drafting status, but I think CWG has reached consesus on the
behavior.
Related: #16602
Commit: 1f8c3c3ab1321c3e3fb10a5f75851165dfc8c5a5
https://github.com/llvm/llvm-project/commit/1f8c3c3ab1321c3e3fb10a5f75851165dfc8c5a5
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU][NFC] Eliminate unnecessary operand classes. (#79450)
These do not seem to remove many repetitions or add clarity; many of
them are only used once.
Not having them also helps further work getting rid of the decoding
functions defined using macros.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Commit: 8ff16f646f84c20a298374c7fd3d2b7f9fefe776
https://github.com/llvm/llvm-project/commit/8ff16f646f84c20a298374c7fd3d2b7f9fefe776
Author: Benjamin Maxwell <benjamin.maxwell at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
Log Message:
-----------
[mlir][ArmSME] Refactor ArmSMEToSCF to used shared loop-building helper (NFC) (#79172)
This will make fixing a bug (next patch) a change to one place, rather
than fixing three separate rewrites.
Note: `TileLoadOpWithMaskAndPadZeroConversion` has been merged into
`TileLoadOpConversion`, since after this change those two rewrites were
pretty much identical.
Commit: 66c710ec9dcdbdec6cadd89b972d8945983dc92f
https://github.com/llvm/llvm-project/commit/66c710ec9dcdbdec6cadd89b972d8945983dc92f
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Do not bother adding reserved registers to liveins (#79436)
Tweak the implementation of llvm.amdgcn.wave.id to not add TTMP8 to the
function liveins.
Commit: 3f37df5b711773bfd962b703b6d4178e6d16c076
https://github.com/llvm/llvm-project/commit/3f37df5b711773bfd962b703b6d4178e6d16c076
Author: erman-gurses <99776114+erman-gurses at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
A mlir/include/mlir/Dialect/AMDGPU/Transforms/Transforms.h
A mlir/include/mlir/Dialect/AMDGPU/Transforms/Utils.h
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/OptimizeSharedMemory.cpp
A mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp
A mlir/test/Dialect/AMDGPU/optimize_shmem_reads_writes.mlir
Log Message:
-----------
[reland][mlir][amdgpu] Shared memory access optimization pass (#79164)
- Reland: https://github.com/llvm/llvm-project/pull/75627
- Reproduced then fixed the build issue
Commit: f1b1611148fa533fe198fec3fa4ef8139224dc80
https://github.com/llvm/llvm-project/commit/f1b1611148fa533fe198fec3fa4ef8139224dc80
Author: Sean Fertile <35576261+mandlebug at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/test/Driver/fat-lto-objects.c
Log Message:
-----------
[LTO] Fix fat-lto output for -c -emit-llvm. (#79404)
Fix and add a test case for combining '-ffat-lto-objects -c -emit-llvm'
options and fix a spelling mistake in same test.
Commit: 9b71393569ae4508d78b8a21993c21530bfdccc5
https://github.com/llvm/llvm-project/commit/9b71393569ae4508d78b8a21993c21530bfdccc5
Author: NagyDonat <donat.nagy at ericsson.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
Log Message:
-----------
[analyzer] Avoid a crash in a debug printout function (#79446)
Previously the function `RangeConstraintManager::printValue()` crashed
when it encountered an empty rangeset (because `RangeSet::getBitwidth()`
and `RangeSet::isUnsigned()` assert that the rangeset is not empty).
This commit adds a special case that avoids this behavior.
As `printValue()` is only used by the checker debug.ExprInspection (and
during manual debugging), the impacts of this commit are very limited.
---------
Co-authored-by: Balazs Benics <benicsbalazs at gmail.com>
Commit: c5d59fe1b27414387b598e11b9e33d2f13dff87e
https://github.com/llvm/llvm-project/commit/c5d59fe1b27414387b598e11b9e33d2f13dff87e
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
Log Message:
-----------
[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX11.5 (#79460)
The hardware bug only affects GFX11.0.x.
Commit: 1f454ede4660477c3782595975def90c26c19881
https://github.com/llvm/llvm-project/commit/1f454ede4660477c3782595975def90c26c19881
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Log Message:
-----------
[RISCV] Fix TLSDESC comment. NFC (#79403)
Fix comment typos in #66915, and relocation type names related to the
example in the psABI
(https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/420).
Commit: 184ca39529a93e69eb175861d7fff5fc79988e53
https://github.com/llvm/llvm-project/commit/184ca39529a93e69eb175861d7fff5fc79988e53
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CostTable.h
M llvm/include/llvm/CodeGen/FastISel.h
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
R llvm/include/llvm/CodeGen/LowLevelType.h
M llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
M llvm/include/llvm/CodeGen/MachineMemOperand.h
R llvm/include/llvm/CodeGen/MachineValueType.h
M llvm/include/llvm/CodeGen/RegisterBankInfo.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetCallingConv.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/ValueTypes.h
A llvm/include/llvm/CodeGenTypes/LowLevelType.h
A llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/module.modulemap
M llvm/lib/CMakeLists.txt
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
R llvm/lib/CodeGen/LowLevelType.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
A llvm/lib/CodeGenTypes/CMakeLists.txt
A llvm/lib/CodeGenTypes/LowLevelType.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/ARM/ARMCallLowering.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/M68k/M68kMachineFunction.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.h
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/unittests/CodeGen/MachineOperandTest.cpp
M llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
M llvm/utils/TableGen/CodeGenInstruction.h
M llvm/utils/TableGen/CodeGenTarget.h
M llvm/utils/TableGen/DAGISelMatcher.h
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
M llvm/utils/TableGen/InfoByHwMode.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/GlobalISel/BUILD.gn
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
Log Message:
-----------
[llvm] Move CodeGenTypes library to its own directory (#79444)
Finally addresses https://reviews.llvm.org/D148769#4311232 :)
No behavior change.
Commit: 016b7e8bf4df839f4bf84ee615cbe422e75f7868
https://github.com/llvm/llvm-project/commit/016b7e8bf4df839f4bf84ee615cbe422e75f7868
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
A llvm/utils/gn/secondary/llvm/lib/CodeGenTypes/BUILD.gn
Log Message:
-----------
[gn] port 184ca39529a9
Commit: 4a91206359e2f2572e14b754a75c0f7f1aab7346
https://github.com/llvm/llvm-project/commit/4a91206359e2f2572e14b754a75c0f7f1aab7346
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
A llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
R llvm/test/Transforms/LoopVectorize/vplan-native-inner-loop-only.ll
Log Message:
-----------
[llvm][LV] Move new test into X86 subfolder
Added in a04f6152914ea21f3068aaba9d8fc21d2e703d3e.
Failing on our Arm only bots:
https://lab.llvm.org/buildbot/#/builders/245/builds/19684
Commit: b0511419b3fd71fa8f8c3618b7e849aabd2ccf65
https://github.com/llvm/llvm-project/commit/b0511419b3fd71fa8f8c3618b7e849aabd2ccf65
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/AttrDocs.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
M clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
M clang/test/Sema/attr-riscv-rvv-vector-bits.c
Log Message:
-----------
[RISCV] Support __riscv_v_fixed_vlen for vbool types. (#76551)
This adopts a similar behavior to AArch64 SVE, where bool vectors are
represented as a vector of chars with 1/8 the number of elements. This
ensures the vector always occupies a power of 2 number of bytes.
A consequence of this is that vbool64_t, vbool32_t, and vool16_t can
only be used with a vector length that guarantees at least 8 bits.
Commit: a621198a035cdc700f08507879db902f22f8a5e2
https://github.com/llvm/llvm-project/commit/a621198a035cdc700f08507879db902f22f8a5e2
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M libc/config/config.json
M libc/docs/dev/printf_behavior.rst
M libc/src/__support/UInt.h
M libc/src/__support/float_to_string.h
M libc/test/src/stdio/sprintf_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
Log Message:
-----------
[libc] Move printf long double to simple calc (#75414)
The Ryu algorithm is very fast with its table, but that table grows too
large for long doubles. This patch adds a method of calculating the
digits of long doubles using just wide integers and fast modulo
operations. This results in significant performance improvements vs the
previous int calc mode, while taking up a similar amound of peak memory.
It will be slow in some %e/%g cases, but reasonable fast for %f with no
loss of accuracy.
Commit: 51b25bad5e53d5be07b5162e4cebcb7d49a422e7
https://github.com/llvm/llvm-project/commit/51b25bad5e53d5be07b5162e4cebcb7d49a422e7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Type.h
M clang/include/clang/Basic/AttrDocs.td
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ItaniumMangle.cpp
M clang/lib/AST/JSONNodeDumper.cpp
M clang/lib/AST/TextNodeDumper.cpp
M clang/lib/AST/Type.cpp
M clang/lib/AST/TypePrinter.cpp
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaType.cpp
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-call.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-cast.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-codegen.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-globals.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-types.c
M clang/test/CodeGenCXX/riscv-mangle-rvv-fixed-vectors.cpp
M clang/test/Sema/attr-riscv-rvv-vector-bits.c
Log Message:
-----------
Revert "[RISCV] Support __riscv_v_fixed_vlen for vbool types. (#76551)"
This reverts commit b0511419b3fd71fa8f8c3618b7e849aabd2ccf65.
Test failure was reported.
Commit: b9483d30a7d7a0650a0e83c75fcb9ab4932f475a
https://github.com/llvm/llvm-project/commit/b9483d30a7d7a0650a0e83c75fcb9ab4932f475a
Author: Douglas Yung <douglas.yung at sony.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
Log Message:
-----------
Revert "[X86] Fold not(pcmpeq(and(X,CstPow2),0)) -> pcmpeq(and(X,CstPow2),CstPow2)"
This reverts commit 72f10f7eb536da58cb79e13974895cd97d4e1a5f.
This change was causing a miscompile on an internal test and is being reverted at the author's request until it can be fixed.
Commit: 7fdb932c4e78706cec3468a1f149e5a54a865d36
https://github.com/llvm/llvm-project/commit/7fdb932c4e78706cec3468a1f149e5a54a865d36
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/LiveInterval.h
Log Message:
-----------
[CodeGen] Add standard traits for LiveInterval::SingleLinkedListIterator (#79473)
For example this will allow LiveInterval::subranges() to be used in
any_of/all_of/none_of.
Commit: 7f409cd82b322038f08a984a07377758e76b0e4c
https://github.com/llvm/llvm-project/commit/7f409cd82b322038f08a984a07377758e76b0e4c
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lld/wasm/InputChunks.h
M lld/wasm/InputElement.h
M lld/wasm/InputFiles.cpp
M lld/wasm/WriterUtils.cpp
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/Object/Wasm.h
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/WasmYAML.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
A llvm/test/Object/Inputs/WASM/multi-table.wasm
A llvm/test/Object/wasm-obj2yaml-tables.test
Log Message:
-----------
[Object][Wasm] Allow parsing of GC types in type and table sections (#79235)
This change allows a WasmObjectFile to be created from a wasm file even
if it uses typed funcrefs and GC types. It does not significantly change how
lib/Object models its various internal types (e.g. WasmSignature,
WasmElemSegment), so LLVM does not really "support" or understand such
files, but it is sufficient to parse the type, global and element sections, discarding
types that are not understood. This is useful for low-level binary tools such as
nm and objcopy, which use only limited aspects of the binary (such as function
definitions) or deal with sections as opaque blobs.
This is done by allowing `WasmValType` to have a value of `OTHERREF`
(representing any unmodeled reference type), and adding a field to
`WasmSignature` indicating it's a placeholder for an unmodeled reference
type (since there is a 1:1 correspondence between WasmSignature objects
and types in the type section).
Then the object file parsers for the type and element sections are expanded
to parse encoded reference types and discard any unmodeled fields.
Commit: 5aa5a2f1b77d93a9f9ed158172277ee41ac224a9
https://github.com/llvm/llvm-project/commit/5aa5a2f1b77d93a9f9ed158172277ee41ac224a9
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Disable exact VLEN splitting for bitrotate shuffles (#79468)
If we have a bitrotate shuffle, this is also by definition a vreg
splitable shuffle when exact VLEN is known. However, there's no profit
to be had from splitting the wider bitrotate lowering into individual m1
pieces. We'd rather leave it the higher lmul to reduce code size.
This is a general problem for any linear-in-LMUL shuffle expansions when
the vreg splitting still has to do linear work per piece. On first
reflection it seems like element rotation might have the same
interaction, but in that case, splitting can be done via a set of whole
register moves (which may get folded into the consumer depending) which
at least as good as a pair of slideup/slidedown. I think that bitrotate
is the only shuffle expansion we have that actually needs handled here.
Commit: 97ace00a564ac9d2424a9885c2117e475260ac1b
https://github.com/llvm/llvm-project/commit/97ace00a564ac9d2424a9885c2117e475260ac1b
Author: Augie Fackler <augie at google.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
bazel: fix build past 184ca39529a93e69eb175861d7fff5fc79988e53
Commit: ccb99f221422b8de5e1ae04d3427f15878f7cd93
https://github.com/llvm/llvm-project/commit/ccb99f221422b8de5e1ae04d3427f15878f7cd93
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lld/ELF/Arch/RISCV.cpp
Log Message:
-----------
[ELF] Clean up R_RISCV_RELAX code. NFC
Commit: 5377fa72ceff28593cdeec16bfa97c31aa145623
https://github.com/llvm/llvm-project/commit/5377fa72ceff28593cdeec16bfa97c31aa145623
Author: AdityaK <1894981+hiraditya at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/docs/TestingGuide.rst
Log Message:
-----------
[doc] Add special case for unsupported test (#78858)
That helps disable the test for all the targets
Commit: 30279dcf5181c6683ca48bfb169ac9f80e1eb897
https://github.com/llvm/llvm-project/commit/30279dcf5181c6683ca48bfb169ac9f80e1eb897
Author: David Green <david.green at arm.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
A llvm/test/CodeGen/AArch64/pr79100.ll
Log Message:
-----------
[AArch64] Add a test from #79100, showing extra unnecessary movs. NFC
Commit: 849951f8759171cb6c74d3ccbcf154506fc1f0ae
https://github.com/llvm/llvm-project/commit/849951f8759171cb6c74d3ccbcf154506fc1f0ae
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M lld/ELF/Relocations.cpp
Log Message:
-----------
[ELF] Fix terminology: TLS optimizations instead of TLS relaxation. NFC
Commit: 2e2c42f9b9eae643252ed12f3cd413b8d749d75c
https://github.com/llvm/llvm-project/commit/2e2c42f9b9eae643252ed12f3cd413b8d749d75c
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M clang-tools-extra/clang-apply-replacements/lib/Tooling/ApplyReplacements.cpp
M clang-tools-extra/clangd/InlayHints.cpp
A clang-tools-extra/test/clang-apply-replacements/Inputs/yml-basic/basic.h
A clang-tools-extra/test/clang-apply-replacements/Inputs/yml-basic/file1.yml
A clang-tools-extra/test/clang-apply-replacements/Inputs/yml-basic/file2.yml
A clang-tools-extra/test/clang-apply-replacements/yml-basic.cpp
M clang/lib/AST/AttrDocTable.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/StaticAnalyzer/Core/RangeConstraintManager.cpp
M clang/test/AST/Interp/complex.cpp
M clang/test/CXX/drs/dr4xx.cpp
M clang/test/Driver/fat-lto-objects.c
M clang/test/Driver/fveclib.c
M clang/test/Preprocessor/riscv-target-features.c
M clang/www/cxx_dr_status.html
M compiler-rt/lib/sanitizer_common/tests/sanitizer_bitvector_test.cpp
M flang/include/flang/Optimizer/Builder/FIRBuilder.h
M flang/include/flang/Optimizer/Support/Utils.h
M flang/lib/Lower/ConvertExprToHLFIR.cpp
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp
M flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp
M flang/test/Fir/boxproc-2.fir
A flang/test/HLFIR/minloc-elemental.fir
M flang/test/Lower/structure-constructors-alloc-comp.f90
M flang/test/Transforms/simplifyintrinsics.fir
M libc/config/config.json
M libc/docs/dev/printf_behavior.rst
M libc/src/__support/UInt.h
M libc/src/__support/float_to_string.h
M libc/test/src/stdio/sprintf_test.cpp
M lld/COFF/PDB.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/MapFile.cpp
M lld/ELF/Relocations.cpp
M lld/test/ELF/lto/ltopasses-custom.ll
M lld/test/ELF/riscv-tlsdesc-relax.s
M lld/test/ELF/riscv-tlsdesc.s
M lld/wasm/InputChunks.h
M lld/wasm/InputElement.h
M lld/wasm/InputFiles.cpp
M lld/wasm/WriterUtils.cpp
M lldb/source/Plugins/Language/CPlusPlus/LibCxx.cpp
M llvm/docs/Passes.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/TestingGuide.rst
M llvm/include/llvm/Analysis/ValueTracking.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/CodeGen/BasicTTIImpl.h
M llvm/include/llvm/CodeGen/CostTable.h
M llvm/include/llvm/CodeGen/FastISel.h
A llvm/include/llvm/CodeGen/FreeMachineFunction.h
M llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
M llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h
M llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h
M llvm/include/llvm/CodeGen/GlobalISel/LegacyLegalizerInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/LegalizerInfo.h
M llvm/include/llvm/CodeGen/GlobalISel/Utils.h
M llvm/include/llvm/CodeGen/LiveInterval.h
R llvm/include/llvm/CodeGen/LowLevelType.h
M llvm/include/llvm/CodeGen/LowLevelTypeUtils.h
M llvm/include/llvm/CodeGen/MachineMemOperand.h
M llvm/include/llvm/CodeGen/MachinePassManager.h
R llvm/include/llvm/CodeGen/MachineValueType.h
M llvm/include/llvm/CodeGen/RegisterBankInfo.h
M llvm/include/llvm/CodeGen/SelectionDAG.h
M llvm/include/llvm/CodeGen/SelectionDAGNodes.h
M llvm/include/llvm/CodeGen/TargetCallingConv.h
M llvm/include/llvm/CodeGen/TargetLowering.h
M llvm/include/llvm/CodeGen/ValueTypes.h
A llvm/include/llvm/CodeGenTypes/LowLevelType.h
A llvm/include/llvm/CodeGenTypes/MachineValueType.h
M llvm/include/llvm/ExecutionEngine/Orc/MachOBuilder.h
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/Instruction.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/Object/Wasm.h
M llvm/include/llvm/Passes/CodeGenPassBuilder.h
M llvm/include/llvm/Passes/MachinePassRegistry.def
M llvm/include/llvm/Target/TargetInstrPredicate.td
M llvm/include/module.modulemap
M llvm/lib/Analysis/ValueTracking.cpp
M llvm/lib/CMakeLists.txt
M llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp
M llvm/lib/CodeGen/CMakeLists.txt
M llvm/lib/CodeGen/CallBrPrepare.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
A llvm/lib/CodeGen/FreeMachineFunction.cpp
M llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerInfo.cpp
R llvm/lib/CodeGen/LowLevelType.cpp
M llvm/lib/CodeGen/MIRParser/MIParser.cpp
M llvm/lib/CodeGen/MIRPrinter.cpp
M llvm/lib/CodeGen/MachineInstr.cpp
M llvm/lib/CodeGen/MachinePassManager.cpp
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/MachineVerifier.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/FastISel.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
M llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
M llvm/lib/CodeGen/SelectionDAG/StatepointLowering.cpp
M llvm/lib/CodeGen/TargetLoweringBase.cpp
M llvm/lib/CodeGen/TargetRegisterInfo.cpp
A llvm/lib/CodeGenTypes/CMakeLists.txt
A llvm/lib/CodeGenTypes/LowLevelType.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Object/DXContainer.cpp
M llvm/lib/Object/ELFObjectFile.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/ObjectYAML/COFFYAML.cpp
M llvm/lib/ObjectYAML/WasmYAML.cpp
M llvm/lib/Passes/CodeGenPassBuilder.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/AArch64/AArch64FastISel.cpp
M llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelUtils.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.h
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSDIRInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VINTERPInstructions.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/ARM/ARMCallLowering.cpp
M llvm/lib/Target/ARM/ARMFastISel.cpp
M llvm/lib/Target/ARM/ARMISelLowering.cpp
M llvm/lib/Target/ARM/ARMISelLowering.h
M llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
M llvm/lib/Target/Hexagon/HexagonInstrInfo.h
M llvm/lib/Target/Lanai/LanaiISelLowering.cpp
M llvm/lib/Target/M68k/M68kMachineFunction.h
M llvm/lib/Target/Mips/MCTargetDesc/MipsABIInfo.cpp
M llvm/lib/Target/Mips/MipsFastISel.cpp
M llvm/lib/Target/Mips/MipsISelLowering.cpp
M llvm/lib/Target/Mips/MipsISelLowering.h
M llvm/lib/Target/Mips/MipsOptimizePICCall.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.cpp
M llvm/lib/Target/Mips/MipsSEISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.cpp
M llvm/lib/Target/PowerPC/PPCISelLowering.h
M llvm/lib/Target/RISCV/CMakeLists.txt
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoA.td
R llvm/lib/Target/RISCV/RISCVMacroFusion.cpp
R llvm/lib/Target/RISCV/RISCVMacroFusion.h
A llvm/lib/Target/RISCV/RISCVMacroFusion.td
M llvm/lib/Target/RISCV/RISCVSubtarget.cpp
M llvm/lib/Target/RISCV/RISCVSubtarget.h
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.h
M llvm/lib/Target/WebAssembly/MCTargetDesc/WebAssemblyTargetStreamer.h
M llvm/lib/Target/WebAssembly/Utils/WebAssemblyTypeUtilities.h
M llvm/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
M llvm/lib/Target/X86/GISel/X86CallLowering.cpp
M llvm/lib/Target/X86/GISel/X86InstructionSelector.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InterleavedAccess.cpp
M llvm/lib/Transforms/Scalar/FlattenCFGPass.cpp
M llvm/lib/Transforms/Scalar/LoopFlatten.cpp
M llvm/lib/Transforms/Scalar/LowerAtomicPass.cpp
M llvm/lib/Transforms/Utils/FlattenCFG.cpp
M llvm/lib/Transforms/Utils/LowerInvoke.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/test/CodeGen/AArch64/callbr-prepare.ll
A llvm/test/CodeGen/AArch64/pr79100.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.wave.id.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
A llvm/test/CodeGen/RISCV/rvv/frm-insert.ll
M llvm/test/CodeGen/Thumb2/mve-vcvt16.ll
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/Feature/optnone-opt.ll
M llvm/test/MC/RISCV/rv32i-invalid.s
M llvm/test/MC/RISCV/rv32zaamo-invalid.s
M llvm/test/MC/RISCV/rv32zaamo-valid.s
M llvm/test/MC/RISCV/rv32zalrsc-invalid.s
M llvm/test/MC/RISCV/rv32zalrsc-valid.s
M llvm/test/MC/RISCV/rv64zaamo-invalid.s
M llvm/test/MC/RISCV/rv64zaamo-valid.s
M llvm/test/MC/RISCV/rv64zalrsc-invalid.s
M llvm/test/MC/RISCV/rv64zalrsc-valid.s
A llvm/test/Object/Inputs/WASM/multi-table.wasm
A llvm/test/Object/wasm-obj2yaml-tables.test
M llvm/test/Other/new-pass-manager.ll
M llvm/test/TableGen/address-space-patfrags.td
M llvm/test/ThinLTO/X86/cache-config.ll
M llvm/test/Transforms/Attributor/nofpclass-implied-by-fcmp.ll
M llvm/test/Transforms/FixIrreducible/switch.ll
M llvm/test/Transforms/IndVarSimplify/X86/iv-widen.ll
M llvm/test/Transforms/IndVarSimplify/backedge-on-min-max.ll
M llvm/test/Transforms/IndVarSimplify/sharpen-range.ll
M llvm/test/Transforms/InstSimplify/assume-fcmp-constant-implies-class.ll
M llvm/test/Transforms/LICM/argmemonly-call.ll
M llvm/test/Transforms/LICM/assume.ll
M llvm/test/Transforms/LICM/basictest.ll
M llvm/test/Transforms/LICM/call-hoisting.ll
M llvm/test/Transforms/LICM/crash.ll
M llvm/test/Transforms/LICM/dbg-value-sink.ll
M llvm/test/Transforms/LICM/debug-value.ll
M llvm/test/Transforms/LICM/extra-copies.ll
M llvm/test/Transforms/LICM/fence.ll
M llvm/test/Transforms/LICM/funclet.ll
M llvm/test/Transforms/LICM/guards.ll
M llvm/test/Transforms/LICM/hoist-round.ll
M llvm/test/Transforms/LICM/invariant.start.ll
M llvm/test/Transforms/LICM/lcssa-ssa-promoter.ll
M llvm/test/Transforms/LICM/no-preheader-test.ll
M llvm/test/Transforms/LICM/opt-remarks-conditional-load.ll
M llvm/test/Transforms/LICM/opt-remarks-intervening-store.ll
M llvm/test/Transforms/LICM/opt-remarks.ll
M llvm/test/Transforms/LICM/preheader-safe.ll
M llvm/test/Transforms/LICM/promote-order.ll
M llvm/test/Transforms/LICM/read-only-calls.ll
M llvm/test/Transforms/LICM/scalar-promote-memmodel.ll
M llvm/test/Transforms/LICM/scalar-promote-unwind.ll
M llvm/test/Transforms/LICM/scalar-promote.ll
M llvm/test/Transforms/LICM/speculate.ll
M llvm/test/Transforms/LICM/store-hoisting.ll
M llvm/test/Transforms/LICM/volatile-alias.ll
M llvm/test/Transforms/LoopFlatten/loop-flatten-negative.ll
A llvm/test/Transforms/LoopFlatten/loop-flatten-version.ll
M llvm/test/Transforms/LoopFlatten/widen-iv.ll
M llvm/test/Transforms/LoopIdiom/nontemporal_store.ll
M llvm/test/Transforms/LoopRotate/RISCV/invalid-cost.ll
M llvm/test/Transforms/LoopRotate/basic.ll
M llvm/test/Transforms/LoopRotate/call-prepare-for-lto.ll
M llvm/test/Transforms/LoopRotate/noalias.ll
M llvm/test/Transforms/LoopStrengthReduce/ivchain.ll
A llvm/test/Transforms/LoopVectorize/X86/vplan-native-inner-loop-only.ll
M llvm/test/Transforms/LowerAtomic/atomic-load.ll
M llvm/test/Transforms/LowerAtomic/atomic-swap.ll
M llvm/test/Transforms/LowerAtomic/barrier.ll
M llvm/test/Transforms/LowerInvoke/2003-12-10-Crash.ll
M llvm/test/Transforms/LowerInvoke/lowerinvoke.ll
M llvm/test/Transforms/LowerSwitch/2003-05-01-PHIProblem.ll
M llvm/test/Transforms/LowerSwitch/2003-08-23-EmptySwitch.ll
M llvm/test/Transforms/LowerSwitch/2004-03-13-SwitchIsDefaultCrash.ll
M llvm/test/Transforms/LowerSwitch/2014-06-10-SwitchContiguousOpt.ll
M llvm/test/Transforms/LowerSwitch/2014-06-11-SwitchDefaultUnreachableOpt.ll
M llvm/test/Transforms/LowerSwitch/2014-06-23-PHIlowering.ll
M llvm/test/Transforms/LowerSwitch/condition-phi-unreachable-default.ll
M llvm/test/Transforms/LowerSwitch/delete-default-block-crash.ll
M llvm/test/Transforms/LowerSwitch/do-not-handle-impossible-values.ll
M llvm/test/Transforms/LowerSwitch/feature.ll
M llvm/test/Transforms/LowerSwitch/fold-popular-case-to-unreachable-default.ll
M llvm/test/Transforms/LowerSwitch/phi-in-dead-block.ll
M llvm/test/Transforms/LowerSwitch/pr59316.ll
A llvm/test/Transforms/SLPVectorizer/X86/extractelement-multi-register-use.ll
M llvm/test/Transforms/StructurizeCFG/switch.ll
M llvm/test/Transforms/UnifyFunctionExitNodes/unreachable-blocks-status.ll
M llvm/test/Transforms/UnifyLoopExits/basic.ll
M llvm/test/Transforms/UnifyLoopExits/nested.ll
M llvm/test/Transforms/UnifyLoopExits/restore-ssa.ll
M llvm/test/Transforms/UnifyLoopExits/switch.ll
A llvm/test/Transforms/Util/flatten-cfg.ll
R llvm/test/Transforms/Util/flattencfg.ll
M llvm/test/Transforms/Util/lowerinvoke-funclet.ll
M llvm/test/Transforms/Util/lowerswitch.ll
M llvm/test/tools/llvm-lto2/X86/pipeline.ll
M llvm/tools/llc/NewPMDriver.cpp
M llvm/unittests/CodeGen/MachineOperandTest.cpp
M llvm/unittests/CodeGen/ScalableVectorMVTsTest.cpp
M llvm/unittests/MIR/PassBuilderCallbacksTest.cpp
M llvm/unittests/Support/RISCVISAInfoTest.cpp
M llvm/utils/TableGen/CodeGenInstruction.h
M llvm/utils/TableGen/CodeGenTarget.h
M llvm/utils/TableGen/DAGISelMatcher.h
M llvm/utils/TableGen/DAGISelMatcherEmitter.cpp
M llvm/utils/TableGen/GlobalISelEmitter.cpp
M llvm/utils/TableGen/GlobalISelMatchTable.h
M llvm/utils/TableGen/InfoByHwMode.h
M llvm/utils/TableGen/PredicateExpander.cpp
M llvm/utils/TableGen/PredicateExpander.h
M llvm/utils/TableGen/RegisterInfoEmitter.cpp
M llvm/utils/gn/secondary/llvm/lib/CodeGen/BUILD.gn
A llvm/utils/gn/secondary/llvm/lib/CodeGenTypes/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Target/RISCV/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn
M llvm/utils/gn/secondary/llvm/utils/TableGen/GlobalISel/BUILD.gn
M mlir/include/mlir/Dialect/AMDGPU/IR/AMDGPU.td
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.h
M mlir/include/mlir/Dialect/AMDGPU/Transforms/Passes.td
A mlir/include/mlir/Dialect/AMDGPU/Transforms/Transforms.h
A mlir/include/mlir/Dialect/AMDGPU/Transforms/Utils.h
M mlir/include/mlir/IR/Builders.h
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/ArmSMEToSCF/ArmSMEToSCF.cpp
M mlir/lib/Conversion/NVGPUToNVVM/NVGPUToNVVM.cpp
M mlir/lib/Dialect/AMDGPU/IR/AMDGPUDialect.cpp
M mlir/lib/Dialect/AMDGPU/Transforms/CMakeLists.txt
A mlir/lib/Dialect/AMDGPU/Transforms/OptimizeSharedMemory.cpp
A mlir/lib/Dialect/AMDGPU/Transforms/Utils.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncParallelFor.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/Tensor/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp
M mlir/lib/IR/Builders.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
M mlir/lib/Transforms/Utils/LoopInvariantCodeMotionUtils.cpp
M mlir/test/Conversion/ArmSMEToSCF/arm-sme-to-scf.mlir
M mlir/test/Conversion/NVGPUToNVVM/nvgpu-to-nvvm.mlir
A mlir/test/Dialect/AMDGPU/optimize_shmem_reads_writes.mlir
M mlir/test/Dialect/Bufferization/canonicalize.mlir
M mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir
M mlir/test/lib/Dialect/SCF/TestSCFUtils.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
M mlir/test/lib/IR/TestClone.cpp
M mlir/test/lib/Transforms/TestConstantFold.cpp
M mlir/tools/mlir-tblgen/LLVMIRIntrinsicGen.cpp
M openmp/runtime/src/kmp_os.h
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/test/src/stdlib/BUILD.bazel
M utils/bazel/llvm-project-overlay/libc/utils/MPFRWrapper/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
rebase on simplification. only check R_RISCV_RELAX for R_RISCV_TLSDESC_HI20
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/e984f0f6f497...2e2c42f9b9ea
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