[all-commits] [llvm/llvm-project] 5aa5a2: [RISCV] Disable exact VLEN splitting for bitrotate...

[Philip Reames via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 5aa5a2f1b77d93a9f9ed158172277ee41ac224a9
      https://github.com/llvm/llvm-project/commit/5aa5a2f1b77d93a9f9ed158172277ee41ac224a9
  Author: Philip Reames <preames at rivosinc.com>
  Date:   2024-01-25 (Thu, 25 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll

  Log Message:
  -----------
  [RISCV] Disable exact VLEN splitting for bitrotate shuffles (#79468)

If we have a bitrotate shuffle, this is also by definition a vreg
splitable shuffle when exact VLEN is known. However, there's no profit
to be had from splitting the wider bitrotate lowering into individual m1
pieces. We'd rather leave it the higher lmul to reduce code size.

This is a general problem for any linear-in-LMUL shuffle expansions when
the vreg splitting still has to do linear work per piece. On first
reflection it seems like element rotation might have the same
interaction, but in that case, splitting can be done via a set of whole
register moves (which may get folded into the consumer depending) which
at least as good as a pair of slideup/slidedown. I think that bitrotate
is the only shuffle expansion we have that actually needs handled here.