[all-commits] [llvm/llvm-project] 549bee: Revert "[Modules] [HeaderSearch] Don't reenter hea...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Wed Jan 24 22:11:03 PST 2024
Branch: refs/heads/users/MaskRay/spr/elf-implement-r_riscv_tlsdesc-for-risc-v
Home: https://github.com/llvm/llvm-project
Commit: 549bee8a55b0abb1232411d1c23d595f605ae1ee
https://github.com/llvm/llvm-project/commit/549bee8a55b0abb1232411d1c23d595f605ae1ee
Author: gulfemsavrun <gulfem at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
R clang/test/Modules/pr73023.cpp
Log Message:
-----------
Revert "[Modules] [HeaderSearch] Don't reenter headers if it is pragm… (#79396)
…a once (#76119)"
This reverts commit f0c387038854d61a632520a4073d1b6ebf4997ed because it
causes an lldb test to fail on a missing import on Mac.
https://logs.chromium.org/logs/fuchsia/buildbucket/cr-buildbucket/8758053465398947297/+/u/lldb/test/stdout
Commit: 28db4017b0b12eb9cf9bbe85afe46a9cf783d2c2
https://github.com/llvm/llvm-project/commit/28db4017b0b12eb9cf9bbe85afe46a9cf783d2c2
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
Log Message:
-----------
[RISCV] Add test coverage for bad interaction of exact vlen and rotate shuffles
Commit: a7395891a797b3cf61a136aea9a82c4c2325b2b3
https://github.com/llvm/llvm-project/commit/a7395891a797b3cf61a136aea9a82c4c2325b2b3
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[MemProf][NFC] remove unneeded TypeSize in InterestingMemoryAccess (#79244)
Unlike ASan, MemProf uses the same memory access callback(inline
sequence) for different size memory access, remove unneeded TypeSize
stored in InterestingMemoryAccess.
Commit: f8262cae69a616b98774d4c669e11246fe3a9a05
https://github.com/llvm/llvm-project/commit/f8262cae69a616b98774d4c669e11246fe3a9a05
Author: Enna1 <xumingjie.enna1 at bytedance.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[MemProf][NFC] remove unneeded sized memory access callback (#79260)
As discussed in https://github.com/llvm/llvm-project/pull/79244, the
sized memory access callback is leftover stuff carried over from Asan,
can removed from the instrumentation.
Commit: a6161a2524c5146a982abc4d580a61f95344edbf
https://github.com/llvm/llvm-project/commit/a6161a2524c5146a982abc4d580a61f95344edbf
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
Log Message:
-----------
[Instrumentation] Remove unused variable 'DL' in MemProfiler.cpp (NFC)
llvm-project/llvm/lib/Transforms/Instrumentation/MemProfiler.cpp:375:21:
error: unused variable 'DL' [-Werror,-Wunused-variable]
const DataLayout &DL = I->getModule()->getDataLayout();
^
1 error generated.
Commit: 816cc9d24b8716367e85d582c7afdfb1cdfcdbf3
https://github.com/llvm/llvm-project/commit/816cc9d24b8716367e85d582c7afdfb1cdfcdbf3
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/test/MC/Disassembler/X86/apx/andn.txt
M llvm/test/MC/Disassembler/X86/apx/bextr.txt
M llvm/test/MC/Disassembler/X86/apx/blsi.txt
M llvm/test/MC/Disassembler/X86/apx/blsmsk.txt
M llvm/test/MC/Disassembler/X86/apx/blsr.txt
M llvm/test/MC/Disassembler/X86/apx/bzhi.txt
M llvm/test/MC/X86/apx/andn-att.s
M llvm/test/MC/X86/apx/andn-intel.s
M llvm/test/MC/X86/apx/bextr-att.s
M llvm/test/MC/X86/apx/bextr-intel.s
M llvm/test/MC/X86/apx/blsi-att.s
M llvm/test/MC/X86/apx/blsi-intel.s
M llvm/test/MC/X86/apx/blsmsk-att.s
M llvm/test/MC/X86/apx/blsmsk-intel.s
M llvm/test/MC/X86/apx/blsr-att.s
M llvm/test/MC/X86/apx/blsr-intel.s
M llvm/test/MC/X86/apx/bzhi-att.s
M llvm/test/MC/X86/apx/bzhi-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
Log Message:
-----------
[X86][MC] Support Enc/Dec for NF BMI instructions (#76709)
Promoted BMI instructions were supported in #73899
Commit: f59eef6515433577d757cf64d2d2f402d95a689e
https://github.com/llvm/llvm-project/commit/f59eef6515433577d757cf64d2d2f402d95a689e
Author: Han-Chung Wang <hanhan0912 at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp
M mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir
Log Message:
-----------
[mlir][tensor] Enhance SimplifyPackToExpandShape for unit dim cases. (#79247)
Progress on https://github.com/openxla/iree/issues/16181
Commit: 84be954cb26ebde58d4ddd2255dfd99904d9ae1b
https://github.com/llvm/llvm-project/commit/84be954cb26ebde58d4ddd2255dfd99904d9ae1b
Author: Shih-Po Hung <shihpo.hung at sifive.com>
Date: 2024-01-25 (Thu, 25 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-and.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-or.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
Log Message:
-----------
[RISCV][CostModel] Refine Arithmetic reduction costs (#79103)
This patch is split off from #77342
- Correct for CodeSize cost that 1 instruction is not included. 3 is
from {VMV.S, ReductionOp, VMV.X}
- Add SplitCost
Unordered reduction chain a series of VADD/VFADD/... which scales with
LMUL.
Ordered reductions chain a series of VFREDOSUMs.
- Use MVT to estimate VL.
Commit: 65e0dc68f5add3579b4a582ca03755cd28d38d09
https://github.com/llvm/llvm-project/commit/65e0dc68f5add3579b4a582ca03755cd28d38d09
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/atomic-signext.ll
Log Message:
-----------
[RISCV] Add test cases showing missed opportunity to remove sext.w after amocas.w. NFC
Commit: 5446902cf2cda4fb17078d04207d2544518a49be
https://github.com/llvm/llvm-project/commit/5446902cf2cda4fb17078d04207d2544518a49be
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/test/CodeGen/RISCV/atomic-signext.ll
Log Message:
-----------
[RISCV] Add IsSignExtendingOpW to amocas.w. (#79351)
Commit: aa64a8277366973705b748e532bfae694b4262aa
https://github.com/llvm/llvm-project/commit/aa64a8277366973705b748e532bfae694b4262aa
Author: Changpeng Fang <changpeng.fang at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
Log Message:
-----------
[AMDGPU] Rename AMDGPULoadTr intrinsic class. NFC. (#79394)
This class is not specific to "Tr"(Transpose). It is
just for a normal load.
Commit: 96ec447a6ae39edff92674e9849de2bf21bfd430
https://github.com/llvm/llvm-project/commit/96ec447a6ae39edff92674e9849de2bf21bfd430
Author: Jordan Rupprecht <rupprecht at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/abseil/Inputs/absl/external-file.h
M clang-tools-extra/test/clang-tidy/checkers/abseil/faster-strsplit-delimiter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/concat-nested-namespaces.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugContainerModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugIteratorModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/InvalidatedIteratorChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/IteratorRangeChecker.cpp
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p3-2a.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_hash.h
M llvm/lib/ExecutionEngine/IntelJITEvents/IntelJITEventsWrapper.h
Log Message:
-----------
[NFC] Fix various unintentional `//namespace` formatting
Commit: 29c9009d23de1a2a395995d559c08c102fa46f48
https://github.com/llvm/llvm-project/commit/29c9009d23de1a2a395995d559c08c102fa46f48
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/docs/RISCVUsage.rst
Log Message:
-----------
[Docs] Capitalize the first letter of Zi* extensions in RISCVUsage.rst. NFC
Commit: de407fd241fe3d17edc09b8121e36ae804daec8a
https://github.com/llvm/llvm-project/commit/de407fd241fe3d17edc09b8121e36ae804daec8a
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang-tools-extra/test/clang-tidy/checkers/abseil/Inputs/absl/external-file.h
M clang-tools-extra/test/clang-tidy/checkers/abseil/faster-strsplit-delimiter.cpp
M clang-tools-extra/test/clang-tidy/checkers/modernize/concat-nested-namespaces.cpp
M clang/lib/Lex/HeaderSearch.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugContainerModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/DebugIteratorModeling.cpp
M clang/lib/StaticAnalyzer/Checkers/InvalidatedIteratorChecker.cpp
M clang/lib/StaticAnalyzer/Checkers/IteratorRangeChecker.cpp
M clang/test/CXX/drs/dr23xx.cpp
M clang/test/CXX/over/over.match/over.match.funcs/over.match.oper/p3-2a.cpp
R clang/test/Modules/pr73023.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_hash.h
M lld/ELF/Arch/RISCV.cpp
M lld/test/ELF/riscv-tlsdesc-relax.s
M lld/test/ELF/riscv-tlsdesc.s
M llvm/docs/RISCVUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/ExecutionEngine/IntelJITEvents/IntelJITEventsWrapper.h
M llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/X86/Disassembler/X86Disassembler.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Transforms/Instrumentation/MemProfiler.cpp
M llvm/test/Analysis/CostModel/RISCV/reduce-add.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-and.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-fadd.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-or.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-fp.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-scalable-int.ll
M llvm/test/Analysis/CostModel/RISCV/reduce-xor.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-intrinsics.ll
M llvm/test/CodeGen/RISCV/atomic-signext.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-rotate.ll
M llvm/test/MC/Disassembler/X86/apx/andn.txt
M llvm/test/MC/Disassembler/X86/apx/bextr.txt
M llvm/test/MC/Disassembler/X86/apx/blsi.txt
M llvm/test/MC/Disassembler/X86/apx/blsmsk.txt
M llvm/test/MC/Disassembler/X86/apx/blsr.txt
M llvm/test/MC/Disassembler/X86/apx/bzhi.txt
M llvm/test/MC/X86/apx/andn-att.s
M llvm/test/MC/X86/apx/andn-intel.s
M llvm/test/MC/X86/apx/bextr-att.s
M llvm/test/MC/X86/apx/bextr-intel.s
M llvm/test/MC/X86/apx/blsi-att.s
M llvm/test/MC/X86/apx/blsi-intel.s
M llvm/test/MC/X86/apx/blsmsk-att.s
M llvm/test/MC/X86/apx/blsmsk-intel.s
M llvm/test/MC/X86/apx/blsr-att.s
M llvm/test/MC/X86/apx/blsr-intel.s
M llvm/test/MC/X86/apx/bzhi-att.s
M llvm/test/MC/X86/apx/bzhi-intel.s
M llvm/test/TableGen/x86-fold-tables.inc
M mlir/lib/Dialect/Tensor/Transforms/PackAndUnpackPatterns.cpp
M mlir/test/Dialect/Tensor/simplify-pack-unpack.mlir
Log Message:
-----------
.
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/c52f753bd79d...de407fd241fe
More information about the All-commits
mailing list