[all-commits] [llvm/llvm-project] bae1ad: [docs] [C++20] [Modules] Document how to import mo...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Wed Jan 24 08:52:08 PST 2024
Branch: refs/heads/users/MaskRay/spr/elf-dont-resolve-relocations-referencing-shn_abs-to-tombstone-in-non-shf_alloc-sections
Home: https://github.com/llvm/llvm-project
Commit: bae1adae1c7cdf3b0bd618fc9cd5af251dc901ed
https://github.com/llvm/llvm-project/commit/bae1adae1c7cdf3b0bd618fc9cd5af251dc901ed
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/docs/StandardCPlusPlusModules.rst
Log Message:
-----------
[docs] [C++20] [Modules] Document how to import modules in clang-repl
We support to import C++20 named modules now in in clang-repl in
https://github.com/llvm/llvm-project/commit/dd3e6c87f3f4affd17d05a4d25fa77d224a98d94.
Then we should document how can we do that.
Commit: d50705ed5d482ccd9b9afabea2b6358d056b7543
https://github.com/llvm/llvm-project/commit/d50705ed5d482ccd9b9afabea2b6358d056b7543
Author: Andrzej Warzyński <andrzej.warzynski at arm.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/Vector/canonicalize.mlir
Log Message:
-----------
[mlir][vector] Support scalable vec in `TransferReadAfterWriteToBroadcast` (#79162)
Makes `TransferReadAfterWriteToBroadcast` correctly propagate
scalability flags.
Commit: f3b495f5842bd3c8a5433ba4b784d49c663f84af
https://github.com/llvm/llvm-project/commit/f3b495f5842bd3c8a5433ba4b784d49c663f84af
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
Log Message:
-----------
[RISCV] Add tests for reverse shuffles of i1 vectors. NFC
This is to add test coverage for a change in #73342
Commit: 34466019e74fe455f6c67bab1d48222a08bede4d
https://github.com/llvm/llvm-project/commit/34466019e74fe455f6c67bab1d48222a08bede4d
Author: Adrian Kuegel <akuegel at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
[mlir][Bazel] Add missing dependency after 750e90e4403df23d6b271afb90e6b4d463739965
Commit: 5404a3792ed58b94b938bbf5cfe6eeb23c664efc
https://github.com/llvm/llvm-project/commit/5404a3792ed58b94b938bbf5cfe6eeb23c664efc
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
Log Message:
-----------
[Driver] Use StringRef::consume_front (NFC)
Commit: 873a7bb12949709ea406c8adc82cd69fc372527d
https://github.com/llvm/llvm-project/commit/873a7bb12949709ea406c8adc82cd69fc372527d
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
Log Message:
-----------
[Transforms] Use llvm::pred_size and llvm::predecessors (NFC)
Commit: 18a3c7a01ed983d19e47a03e664200ffff53689c
https://github.com/llvm/llvm-project/commit/18a3c7a01ed983d19e47a03e664200ffff53689c
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUImageIntrinsicOptimizer.cpp
Log Message:
-----------
[AMDGPU] Use llvm::none_of (NFC)
Commit: b0763a1ae940d60d8f558f85216382bc6695a1e3
https://github.com/llvm/llvm-project/commit/b0763a1ae940d60d8f558f85216382bc6695a1e3
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp
Log Message:
-----------
[DebugInfo] Use std::size (NFC)
Commit: 33ecef9812e2c9bfadef035b8e34a949acae2abc
https://github.com/llvm/llvm-project/commit/33ecef9812e2c9bfadef035b8e34a949acae2abc
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/test/CodeGen/X86/commute-blend-avx2.ll
Log Message:
-----------
[X86][CodeGen] Fix crash when commute operands of Instruction for code size (#79245)
Reported in 134fcc62786d31ab73439201dce2d73808d1785a
Incorrect opcode is used b/c there is a `[[fallthrough]]` at line 2386.
Commit: a7a1b8b17e264fb0f2d2b4165cf9a7f5094b08b3
https://github.com/llvm/llvm-project/commit/a7a1b8b17e264fb0f2d2b4165cf9a7f5094b08b3
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll
Log Message:
-----------
[MSSAUpdater] Handle simplified accesses when updating phis (#78272)
This is a followup to #76819. After those changes, we can still run into
an assertion failure for a slight variation of the test case: When
fixing up MemoryPhis, we map the incoming access to the access of the
cloned instruction -- which may now no longer exist.
Fix this by reusing the getNewDefiningAccessForClone() helper, which
will look upwards for a new defining access in that case.
Commit: 303e64826b79af0c0e67ba06d5d8e1385adc32b5
https://github.com/llvm/llvm-project/commit/303e64826b79af0c0e67ba06d5d8e1385adc32b5
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
Log Message:
-----------
[X86][NFC] Remove dead code for "_REV" instructions
ADC/SBB with reverse encoding is never emitted by compiler before
encoding optimization, which is called after flag-copy lowering.
This is a partial reland for 8bbf100799a97f8342bf1a8409c6fb48f03e837f
Commit: 543cf08636f3a3bb55dddba2e8cad787601647ba
https://github.com/llvm/llvm-project/commit/543cf08636f3a3bb55dddba2e8cad787601647ba
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
A llvm/test/Transforms/PhaseOrdering/X86/loop-vectorizer-noalias.ll
Log Message:
-----------
[PhaseOrdering] Add additional test for #79161 (NFC)
Commit: cd7ea4ea657ea41b42fcbd0e6b33faa46608d18e
https://github.com/llvm/llvm-project/commit/cd7ea4ea657ea41b42fcbd0e6b33faa46608d18e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
M llvm/test/Transforms/PhaseOrdering/X86/loop-vectorizer-noalias.ll
Log Message:
-----------
[LAA] Drop alias scope metadata that is not valid across iterations (#79161)
LAA currently adds memory locations with their original AATags to AST.
However, scoped alias AATags may be valid only within one loop
iteration, while LAA reasons across iterations.
Fix this by determining which alias scopes are defined inside the loop,
and drop AATags that reference these scopes.
Fixes https://github.com/llvm/llvm-project/issues/79137.
Commit: 4a582845597e97d245e8ffdc14281f922b835e56
https://github.com/llvm/llvm-project/commit/4a582845597e97d245e8ffdc14281f922b835e56
Author: Nikolas Klauser <nikolasklauser at berlin.de>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.def
M clang/include/clang/Basic/Builtins.h
A clang/include/clang/Basic/Builtins.td
R clang/include/clang/Basic/BuiltinsBPF.def
A clang/include/clang/Basic/BuiltinsBPF.td
A clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/module.modulemap
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/Sema/OpenCLBuiltins.td
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/test/Analysis/bstring.c
M clang/test/CodeGen/callback_pthread_create.c
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
Log Message:
-----------
[clang] Refactor Builtins.def to be a tablegen file (#68324)
This makes the builtins list quite a bit more verbose, but IMO this is a
huge win in terms of readability.
Commit: 416b079336c6d6e48858f951cd494a7a3577deb8
https://github.com/llvm/llvm-project/commit/416b079336c6d6e48858f951cd494a7a3577deb8
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M .github/workflows/issue-release-workflow.yml
M llvm/utils/git/github-automation.py
Log Message:
-----------
Fix release issue workflow (#79268)
Remove the `--phab-token` argument (which currently eats the subsequent
"auto" as the token no longer exists) and related code.
I think this will fix the workflow failure in
https://github.com/llvm/llvm-project/issues/79253#issuecomment-1907679229.
Commit: fe0e632b00e63bda75155a8d1aa16d271d4af728
https://github.com/llvm/llvm-project/commit/fe0e632b00e63bda75155a8d1aa16d271d4af728
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] Support DPValues in HWAsan (#78731)
This patch extends HWASAN to support maintenance of debug-info that
isn't stored as intrinsics, but is instead in a DPValue object. This is
straight-forwards: we collect any such objects in StackInfoBuilder, and
apply the same operations to them as we would to dbg.value and similar
intrinsics.
I've also replaced some calls to getNextNode with debug-info skipping
next calls, and use iterators for instruction insertion rather than
instruction pointers. This avoids any difference in output between
intrinsic / non-intrinsic debug-info, but also means that any debug-info
comes before code inserted by HWAsan, rather than afterwards. See the
test modifications, where the variable assignment (presented as a
dbg.value) jumps up over all the code inserted by HWAsan. Seeing how the
code inserted by HWAsan is always (AFAIUI) given the source-location of
the instruction being instrumented, I don't believe this will have any
effect on which lines variable assignments become visible on; it may
extend the number of instructions covered by the assignments though.
Commit: fb9a82b0235713782c1cf9d1eba20ce8d95766f7
https://github.com/llvm/llvm-project/commit/fb9a82b0235713782c1cf9d1eba20ce8d95766f7
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/tools/clang-repl/CMakeLists.txt
Log Message:
-----------
[clang-repl] Refine fix for linker error: PLT offset too large
This is a follow-up improvement after the discussion in #78959
Commit: 383d488b0bd68f1abd58c2d0114f82c54ee286d1
https://github.com/llvm/llvm-project/commit/383d488b0bd68f1abd58c2d0114f82c54ee286d1
Author: Kareem Ergawy <kareem.ergawy at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M openmp/libomptarget/test/offloading/fortran/target_map_common_block1.f90
Log Message:
-----------
[openmp][flang][offloading] Do not use fixed device IDs in checks (#78973)
Fixes a small issues in an offloading test where the test dependec on
the host and device being assigned certains numeric IDs. This however is
not stable and fails in situations where any of the devices is assigned
an ID different from the expected value. The fix just checks that
offloading succeeded by making sure the IDs are different.
The test was failing locally for me.
Commit: 91ddcba83ae4385fe771e918c096e6074b411de3
https://github.com/llvm/llvm-project/commit/91ddcba83ae4385fe771e918c096e6074b411de3
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
Log Message:
-----------
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#78482)
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.
TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.
patch 3 from: https://github.com/llvm/llvm-project/pull/73337
Commit: 149ed9d2c58095f87745f8696ef96b5076c91fca
https://github.com/llvm/llvm-project/commit/149ed9d2c58095f87745f8696ef96b5076c91fca
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
Log Message:
-----------
AMDGPU: update GFX11 wmma hazards (#76143)
One V_NOP or unrelated VALU instruction in between is required for
correctness when matrix A or B of current WMMA instruction overlaps with
matrix D of previous WMMA instruction.
Remaining cases of WMMA operand overlaps are handled by the hardware and
do not require handling in hazard recognizer.
Hardware may stall in cases where:
- matrix C of current WMMA instruction overlaps with matrix D of
previous WMMA instruction
- VALU instruction reads matrix D of previous WMMA instruction
- matrix A,B or C of WMMA instruction reads result of previous VALU
instruction
Commit: 9dddb3d5f3bf323b7b7f8281bb848731f69fddfa
https://github.com/llvm/llvm-project/commit/9dddb3d5f3bf323b7b7f8281bb848731f69fddfa
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/Sema/SemaCoroutine.cpp
M clang/test/AST/ast-dump-coroutine.cpp
Log Message:
-----------
[AST] Mark the fallthrough coreturn statement implicit. (#77465)
This is a followup of #77311.
Commit: c46109d0d78863ff5e4e23c8f9fd85eb1220a42e
https://github.com/llvm/llvm-project/commit/c46109d0d78863ff5e4e23c8f9fd85eb1220a42e
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineRegisterInfo.h
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/lib/CodeGen/MachineRegisterInfo.cpp
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-reg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
Log Message:
-----------
Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#79274)
Reverts llvm/llvm-project#78482
Commit: cfddb59be2124f7ec615f48a2d0395c6fdb1bb56
https://github.com/llvm/llvm-project/commit/cfddb59be2124f7ec615f48a2d0395c6fdb1bb56
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
Log Message:
-----------
[AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… (#78414)
…bf8 instructions
Add VOP1, VOP1_DPP8, VOP1_DPP16, VOP3, VOP3_DPP8, VOP3_DPP16
instructions that were supported on GFX940 (MI300):
- V_CVT_F32_FP8
- V_CVT_F32_BF8
- V_CVT_PK_F32_FP8
- V_CVT_PK_F32_BF8
- V_CVT_PK_FP8_F32
- V_CVT_PK_BF8_F32
- V_CVT_SR_FP8_F32
- V_CVT_SR_BF8_F32
---------
Co-authored-by: Mateja Marjanovic <mateja.marjanovic at amd.com>
Co-authored-by: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Commit: 78d8ce316ff6f06f58a7f3eb7f633c4bf3bf3285
https://github.com/llvm/llvm-project/commit/78d8ce316ff6f06f58a7f3eb7f633c4bf3bf3285
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
Log Message:
-----------
[AMDGPU] Require explicit immediate offsets for SGPR+IMM SMEM instructions. (#79131)
As otherwise SGPR+IMM instructions are not distinguishable to SGPR-only
ones in AsmParser, leading to ambiguities.
GFX12 doesn't have special SGPR-only variants, so we still allow
optional immediate offsets for the subtarget.
Also rename the offset operand classes while there.
Part of <https://github.com/llvm/llvm-project/issues/69256>.
Commit: c83180c1248615cf6ea8842eb4e0cebebba4ab57
https://github.com/llvm/llvm-project/commit/c83180c1248615cf6ea8842eb4e0cebebba4ab57
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
A llvm/test/Transforms/ConstraintElimination/umin-result-may-be-poison.ll
Log Message:
-----------
[ConstraintElim] Add tests for #78621.
Tests with umin where the result may be poison for
https://github.com/llvm/llvm-project/issues/78621.
Commit: dee02ee9f8ffc74fea6c54f4c00df16e7ca4c8a1
https://github.com/llvm/llvm-project/commit/dee02ee9f8ffc74fea6c54f4c00df16e7ca4c8a1
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
Log Message:
-----------
[clang][Interp][NFC] Complex elements can only be primitives
So, return a PrimType directly from classifyComplexElementType().
Commit: 17cfc15d6b9b3773db8353937aac9878d7777b21
https://github.com/llvm/llvm-project/commit/17cfc15d6b9b3773db8353937aac9878d7777b21
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
Log Message:
-----------
Fix spelling typo. NFC
commutatvity -> commutativity
Commit: 6255bae6c9afe89470f264f903051f64bc15135f
https://github.com/llvm/llvm-project/commit/6255bae6c9afe89470f264f903051f64bc15135f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
A llvm/test/CodeGen/X86/icmp-pow2-mask.ll
Log Message:
-----------
[X86] Add test coverage based on #78888
Commit: 72f10f7eb536da58cb79e13974895cd97d4e1a5f
https://github.com/llvm/llvm-project/commit/72f10f7eb536da58cb79e13974895cd97d4e1a5f
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
Log Message:
-----------
[X86] Fold not(pcmpeq(and(X,CstPow2),0)) -> pcmpeq(and(X,CstPow2),CstPow2)
Fixes #78888
Commit: 27cfe7a07fc858bd890f2e0980f530a8573748b0
https://github.com/llvm/llvm-project/commit/27cfe7a07fc858bd890f2e0980f530a8573748b0
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
R flang/include/flang/Optimizer/Builder/Array.h
M flang/include/flang/Optimizer/Builder/BoxValue.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Optimizer/Builder/BoxValue.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
A flang/test/Lower/HLFIR/assumed-size-cray-pointee.f90
M flang/test/Lower/HLFIR/cray-pointers.f90
M flang/test/Lower/Intrinsics/lbound.f90
M flang/test/Lower/Intrinsics/ubound.f90
M flang/test/Lower/array-expression-assumed-size.f90
M flang/test/Lower/cray-pointer.f90
Log Message:
-----------
[flang] Set assumed-size last extent to -1 (#79156)
Currently lowering sets the extents of assumed-size array to "undef"
which was OK as long as the value was not expected to be read.
But when interfacing with the runtime and when passing assumed-size to
assumed-rank, this last extent may be read and must be -1 as specified
in the BIND(C) case in 18.5.3 point 5.
Set this value to -1, and update all the lowering code that was looking
for an undef defining op to identify assumed-size: much safer to
propagate and use semantic info here, the previous check actually did
not work if the array was used in an internal procedure (defining op not
visible anymore).
@clementval and @agozillon, I left assumed-size extent to zero in the
acc/omp bounds op as it was, please double check that is what you want
(I can imagine -1 may create troubles here, and 0 makes some sense as it
would lead to no data transfer).
This also allows removing special cases in UBOUND/LBOUND lowering.
Also disable allocation of cray pointee. This was never intended and
would now lead to crashes with the -1 value for assumed-size cray
pointee.
Commit: 7fdf608cefa0d9051eb3146ee19c3750e237c799
https://github.com/llvm/llvm-project/commit/7fdf608cefa0d9051eb3146ee19c3750e237c799
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/lib/CodeGen/CGBuiltin.cpp
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-wmma-w32.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-wmma-w64.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-w32.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-w64.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64.cl
A cross-project-tests/amdgpu/builtins-amdgcn-gfx12-wmma-w32.cl
A cross-project-tests/amdgpu/builtins-amdgcn-gfx12-wmma-w64.cl
A cross-project-tests/amdgpu/builtins-amdgcn-swmmac-w32.cl
A cross-project-tests/amdgpu/builtins-amdgcn-swmmac-w64.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
A llvm/test/MC/AMDGPU/gfx12_asm_wmma_w32.s
A llvm/test/MC/AMDGPU/gfx12_asm_wmma_w64.s
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w32.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w64.txt
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/test/Target/LLVMIR/rocdl.mlir
Log Message:
-----------
[AMDGPU] Add GFX12 WMMA and SWMMAC instructions (#77795)
Co-authored-by: Petar Avramovic <Petar.Avramovic at amd.com>
Co-authored-by: Piotr Sobczak <piotr.sobczak at amd.com>
Commit: 89dae798cc77789a43e9a60173f647dae03a65fe
https://github.com/llvm/llvm-project/commit/89dae798cc77789a43e9a60173f647dae03a65fe
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/Loads.h
M llvm/lib/Analysis/Lint.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
Log Message:
-----------
[Loads] Use BatchAAResults for available value APIs (NFCI)
This allows caching AA queries both within and across the calls,
and enables us to use a custom AAQI configuration.
Commit: d1b473c7956c080fe4d784bb89f720fbd28024a6
https://github.com/llvm/llvm-project/commit/d1b473c7956c080fe4d784bb89f720fbd28024a6
Author: Danial Klimkin <dklimkin at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Fix bazel build past 7251243315ef66f9b3f32e6f8e9536f701aa0d0a (#79282)
Fix bazel build past 7251243315ef66f9b3f32e6f8e9536f701aa0d0a
Commit: 5469010ba73701d47498576a433aea5c6e16ba2c
https://github.com/llvm/llvm-project/commit/5469010ba73701d47498576a433aea5c6e16ba2c
Author: ostannard <oliver.stannard at arm.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64.td
M llvm/test/MC/AArch64/armv8.1a-rdma.s
M llvm/test/MC/AArch64/armv8.2a-dotprod-errors.s
M llvm/test/MC/AArch64/armv8.2a-dotprod.s
M llvm/test/MC/AArch64/armv8r-sysreg.s
M llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt
M llvm/test/MC/Disassembler/AArch64/armv8.3a-js.txt
Log Message:
-----------
[AArch64] FP/SIMD is not mandatory for v8-R (#79004)
The FP/SIMD instructions are optional for v8-R, so they should not be
marked as a dependency of HasV8_0rOps. This had the effect of disabling
some v8R-specific system registers when any of these features was
disabled.
I've moved these features to be enabled by default for Cortex-R82
(currently the only v8-R AArch64 core), matching the previous behavior,
and clang's default.
Based on a patch by Simi Pallipurath <simi.pallipurath at arm.com>
Commit: 182ab1c7034b951433fb8831b67e7758fe61d4e8
https://github.com/llvm/llvm-project/commit/182ab1c7034b951433fb8831b67e7758fe61d4e8
Author: Rainer Orth <ro at gcc.gnu.org>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Support/BLAKE3/blake3_avx2_x86-64_unix.S
M llvm/lib/Support/BLAKE3/blake3_avx512_x86-64_unix.S
M llvm/lib/Support/BLAKE3/blake3_sse2_x86-64_unix.S
M llvm/lib/Support/BLAKE3/blake3_sse41_x86-64_unix.S
Log Message:
-----------
[Support] Adjust .note.GNU-stack guard in Support/BLAKE3/blake3_*_x86-64_unix.S (#76229)
When using GNU ld 2.41 on FreeBSD 14.0/amd64, there are linker warnings
like
```
/vol/gcc/bin/gld-2.41: warning: blake3_avx512_x86-64_unix.S.o: missing .note.GNU-stack section implies executable stack
/vol/gcc/bin/gld-2.41: NOTE: This behaviour is deprecated and will be removed in a future version of the linker
```
This can be fixed by adjusting the guard of the `.note.GNU-stack`
sections in `blake3_*_x86-64_unix.S` to match `llvm/lib/MC/MCAsmInfoELF.cpp:MCAsmInfoELF::getNonexecutableStackSection` which emits the section on all ELF targets
but Solaris.
Tested on `amd64-pc-freebsd14.0`.
Commit: 8b43c1be23119c1024bed0a8ce392bc73727e2e2
https://github.com/llvm/llvm-project/commit/8b43c1be23119c1024bed0a8ce392bc73727e2e2
Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avx-load-store.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx512-shuffles/shuffle-chained-bf16.ll
M llvm/test/CodeGen/X86/bitreverse.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-subo.ll
M llvm/test/CodeGen/X86/constant-pool-sharing.ll
M llvm/test/CodeGen/X86/dpbusd.ll
M llvm/test/CodeGen/X86/dpbusd_const.ll
M llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
M llvm/test/CodeGen/X86/fcmp-constant.ll
M llvm/test/CodeGen/X86/fold-vector-sext-zext.ll
M llvm/test/CodeGen/X86/half.ll
M llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-ones.ll
M llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
M llvm/test/CodeGen/X86/memcmp.ll
M llvm/test/CodeGen/X86/pmaddubsw.ll
M llvm/test/CodeGen/X86/pr46532.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
M llvm/test/CodeGen/X86/pshufb-mask-comments.ll
M llvm/test/CodeGen/X86/ret-mmx.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shrink_vmul.ll
M llvm/test/CodeGen/X86/shuffle-half.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/vec_anyext.ll
M llvm/test/CodeGen/X86/vec_fp_to_int.ll
M llvm/test/CodeGen/X86/vec_set-A.ll
M llvm/test/CodeGen/X86/vector-blend.ll
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-lzcnt-256.ll
M llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-post-combine.ll
M llvm/test/CodeGen/X86/widen_bitcnt.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
Log Message:
-----------
[X86] X86FixupVectorConstants - shrink vector load to movsd/movsd/movd/movq 'zero upper' instructions (#79000)
If we're loading a vector constant that is known to be zero in the upper elements, then attempt to shrink the constant and just scalar load the lower 32/64 bits.
Always chose the vzload/broadcast with the smallest constant load, and prefer vzload over broadcasts for same bitwidth to avoid domain flips (mainly a AVX1 issue).
Fixes #73783
Commit: 7143b451d71fe314730f7610d7908e3b9611815c
https://github.com/llvm/llvm-project/commit/7143b451d71fe314730f7610d7908e3b9611815c
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
A llvm/test/Transforms/JumpThreading/pr79175.ll
Log Message:
-----------
[JumpThreading] Add test for #79175 (NFC)
Commit: c3e77070489979788788ef479f8932ac460b675b
https://github.com/llvm/llvm-project/commit/c3e77070489979788788ef479f8932ac460b675b
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/AST/ExprCXX.cpp
Log Message:
-----------
[clang][AST][NFC] Turn a isa<> + cast<> into dynamic_cast<>
Commit: 98509c7f9792c79b05a41b95c24607f6dd489c5a
https://github.com/llvm/llvm-project/commit/98509c7f9792c79b05a41b95c24607f6dd489c5a
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
Log Message:
-----------
[AArch64] Add vec3 tests with different load/store alignments.
Add extra tests with different load/store alignments for
https://github.com/llvm/llvm-project/pull/78637.
Commit: 90ba33099cbb17e7c159e9ebc5a512037db99d6d
https://github.com/llvm/llvm-project/commit/90ba33099cbb17e7c159e9ebc5a512037db99d6d
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma.c
M clang/test/CodeGen/aarch64-ls64-inline-asm.c
M clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
M clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
M clang/test/CodeGen/cleanup-destslot-simple.c
M clang/test/CodeGen/hexagon-brev-ld-ptr-incdec.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGen/nofpclass.c
M clang/test/CodeGen/union-tbaa1.c
M clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp
M clang/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp
M clang/test/CodeGenCXX/microsoft-abi-typeid.cpp
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjCXX/arc-cxx11-init-list.mm
M clang/test/Headers/__clang_hip_math.hip
M clang/test/OpenMP/bug57757.cpp
M flang/test/HLFIR/no-block-merging.fir
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Analysis/BasicAA/featuretest.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll
M llvm/test/Transforms/Coroutines/coro-async.ll
M llvm/test/Transforms/Coroutines/coro-retcon-alloca-opaque-ptr.ll
M llvm/test/Transforms/Coroutines/coro-retcon-alloca.ll
M llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll
M llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll
M llvm/test/Transforms/Coroutines/coro-swifterror.ll
M llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
M llvm/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll
M llvm/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll
M llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-addsub.ll
M llvm/test/Transforms/InstCombine/add3.ll
M llvm/test/Transforms/InstCombine/array.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/cast_phi.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/compare-alloca.ll
M llvm/test/Transforms/InstCombine/extractvalue.ll
M llvm/test/Transforms/InstCombine/gep-addrspace.ll
M llvm/test/Transforms/InstCombine/gep-canonicalize-constant-indices.ll
M llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
M llvm/test/Transforms/InstCombine/gep-custom-dl.ll
M llvm/test/Transforms/InstCombine/gep-merge-constant-indices.ll
M llvm/test/Transforms/InstCombine/gep-vector-indices.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepphigep.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-custom-dl.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
M llvm/test/Transforms/InstCombine/intptr1.ll
M llvm/test/Transforms/InstCombine/intptr2.ll
M llvm/test/Transforms/InstCombine/intptr3.ll
M llvm/test/Transforms/InstCombine/intptr4.ll
M llvm/test/Transforms/InstCombine/intptr5.ll
M llvm/test/Transforms/InstCombine/intptr7.ll
M llvm/test/Transforms/InstCombine/load-store-forward.ll
M llvm/test/Transforms/InstCombine/load.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/memchr-5.ll
M llvm/test/Transforms/InstCombine/memchr-9.ll
M llvm/test/Transforms/InstCombine/memcmp-3.ll
M llvm/test/Transforms/InstCombine/memcmp-4.ll
M llvm/test/Transforms/InstCombine/memcmp-5.ll
M llvm/test/Transforms/InstCombine/memcmp-6.ll
M llvm/test/Transforms/InstCombine/memcmp-7.ll
M llvm/test/Transforms/InstCombine/memcpy_alloca.ll
M llvm/test/Transforms/InstCombine/memrchr-5.ll
M llvm/test/Transforms/InstCombine/memset2.ll
M llvm/test/Transforms/InstCombine/multi-size-address-space-pointer.ll
M llvm/test/Transforms/InstCombine/non-integral-pointers.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
M llvm/test/Transforms/InstCombine/phi-timeout.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/pr39908.ll
M llvm/test/Transforms/InstCombine/pr44242.ll
M llvm/test/Transforms/InstCombine/pr58901.ll
M llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
M llvm/test/Transforms/InstCombine/select-cmp-br.ll
M llvm/test/Transforms/InstCombine/select-gep.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll
M llvm/test/Transforms/InstCombine/sprintf-2.ll
M llvm/test/Transforms/InstCombine/statepoint-cleanup.ll
M llvm/test/Transforms/InstCombine/str-int-3.ll
M llvm/test/Transforms/InstCombine/str-int-4.ll
M llvm/test/Transforms/InstCombine/str-int-5.ll
M llvm/test/Transforms/InstCombine/str-int.ll
M llvm/test/Transforms/InstCombine/strcall-bad-sig.ll
M llvm/test/Transforms/InstCombine/strcall-no-nul.ll
M llvm/test/Transforms/InstCombine/strlen-7.ll
M llvm/test/Transforms/InstCombine/strlen-9.ll
M llvm/test/Transforms/InstCombine/strncmp-4.ll
M llvm/test/Transforms/InstCombine/strncmp-5.ll
M llvm/test/Transforms/InstCombine/strncmp-6.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/InstCombine/unpack-fca.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/InstCombine/wcslen-5.ll
M llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
M llvm/test/Transforms/LoopUnroll/peel-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-multiple-blocks.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-minimal.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sinking-vs-if-conversion.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
M llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
M llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
M llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
M llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll
M llvm/test/Transforms/PhaseOrdering/basic.ll
M llvm/test/Transforms/PhaseOrdering/loop-access-checks.ll
M llvm/test/Transforms/PhaseOrdering/pr39282.ll
M llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll
M llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/WebAssembly/no-vectorize-rotate.ll
M llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/opt.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-instcombine.ll
M llvm/test/Transforms/Util/strip-gc-relocates.ll
Log Message:
-----------
[InstCombine] Canonicalize constant GEPs to i8 source element type (#68882)
This patch canonicalizes getelementptr instructions with constant
indices to use the `i8` source element type. This makes it easier for
optimizations to recognize that two GEPs are identical, because they
don't need to see past many different ways to express the same offset.
This is a first step towards
https://discourse.llvm.org/t/rfc-replacing-getelementptr-with-ptradd/68699.
This is limited to constant GEPs only for now, as they have a clear
canonical form, while we're not yet sure how exactly to deal with
variable indices.
The test llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll gives
two representative examples of the kind of optimization improvement we
expect from this change. In the first test SimplifyCFG can now realize
that all switch branches are actually the same. In the second test it
can convert it into simple arithmetic. These are representative of
common optimization failures we see in Rust.
Fixes https://github.com/llvm/llvm-project/issues/69841.
Commit: 3d91d9613e294b242d853039209b40a0cb7853f2
https://github.com/llvm/llvm-project/commit/3d91d9613e294b242d853039209b40a0cb7853f2
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/test/Transforms/ConstraintElimination/minmax.ll
M llvm/test/Transforms/ConstraintElimination/umin-result-may-be-poison.ll
Log Message:
-----------
[ConstraintElim] Make sure min/max intrinsic results are not poison.
The result of umin may be poison and in that case the added constraints
are not be valid in contexts where poison doesn't cause UB. Only queue
facts for min/max intrinsics if the result is guaranteed to not be
poison.
This could be improved in the future, by only adding the fact when
solving conditions using the result value.
Fixes https://github.com/llvm/llvm-project/issues/78621.
Commit: 382f70a877f00ab71f3cb5ba461b52e1b59cd292
https://github.com/llvm/llvm-project/commit/382f70a877f00ab71f3cb5ba461b52e1b59cd292
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M libcxx/include/string
Log Message:
-----------
[libc++][NFC] Rewrite function call on two lines for clarity (#79141)
Previously, there was a ternary conditional with a less-than comparison
appearing inside a template argument, which was really confusing because
of the <...> of the function template. This patch rewrites the same
statement on two lines for clarity.
Commit: 03a9f07e189db792b001c4001981d6e2da880221
https://github.com/llvm/llvm-project/commit/03a9f07e189db792b001c4001981d6e2da880221
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M libcxx/include/__algorithm/ranges_max.h
M libcxx/include/__algorithm/ranges_min.h
Log Message:
-----------
[libc++][NFC] Fix leftover && in comment
Commit: 5db2e5801dfec79bad3c804da0f53871a2664373
https://github.com/llvm/llvm-project/commit/5db2e5801dfec79bad3c804da0f53871a2664373
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M .github/workflows/issue-release-workflow.yml
Log Message:
-----------
Add necessary permissions to release issue workflow (#79272)
The `/cherry-pick` command needs `issues: write` to post a comment on
the issue. The `/branch` command also posts a comment, and also needs
`pull-requests: write` to open a PR.
This should fix the failure encountered at
https://github.com/llvm/llvm-project/issues/79253#issuecomment-1907850027.
Commit: 380ac53dfa05792c6f9fd0a4aba542f8c7e5e17c
https://github.com/llvm/llvm-project/commit/380ac53dfa05792c6f9fd0a4aba542f8c7e5e17c
Author: Felipe de Azevedo Piovezan <fpiovezan at apple.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
A llvm/test/CodeGen/X86/dwarf-headers.o
M llvm/test/DebugInfo/Generic/debug-names-one-cu.ll
M llvm/test/DebugInfo/X86/debug-names-dwarf64.ll
M llvm/test/DebugInfo/X86/debug-names-parents-same-offset.ll
M llvm/test/DebugInfo/X86/debug-names-types.ll
M llvm/test/tools/dsymutil/ARM/accel-imported-declarations.test
Log Message:
-----------
[DebugNames] Implement Entry::GetParentEntry query (#78760)
This commit introduces a helper function to DWARFAcceleratorTable::Entry
which follows DW_IDX_Parent attributes to returns the corresponding
parent Entry in the table.
It is tested by enhancing dwarfdump so that it now prints:
1. When data is corrupt.
2. When parent information is present, but the parent is not indexed.
3. The parent entry offset, when the parent is present and indexed. This
is printed in terms a real entry offset (the same that gets printed at
the start of each entry: "Entry @ 0x..."), instead of the encoded number
in the table (which is an offset from the start off the Entry list).
This makes it easy to visually inspect the dwarfdump and check what the
parent is.
Commit: f03a60d4d2fc687059c8bb667d1de37713a5a64b
https://github.com/llvm/llvm-project/commit/f03a60d4d2fc687059c8bb667d1de37713a5a64b
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M .github/workflows/issue-release-workflow.yml
Log Message:
-----------
Use correct tokens in release issue workflow (#79300)
We should use the normal github.token for interacting with issues/PRs on
the repo, and separately pass the `--branch-repo-token` for creating the
branch in the llvmbot repo.
Commit: 70fc9703788e8965813c5b677a85cb84b66671b6
https://github.com/llvm/llvm-project/commit/70fc9703788e8965813c5b677a85cb84b66671b6
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
A llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
A llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
R llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
Log Message:
-----------
[AMDGPU] Move architected SGPR implementation into isel (#79120)
Commit: aaa93ce7323332d8290b8f563d4d71689c1094c5
https://github.com/llvm/llvm-project/commit/aaa93ce7323332d8290b8f563d4d71689c1094c5
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
compiler-rt: Fix FLOAT16 feature detection
CMAKE_TRY_COMPILE_TARGET_TYPE defaults to EXECUTABLE, which causes
any feature detection code snippet without a main function to fail,
so we need to make sure it gets explicitly set to STATIC_LIBRARY.
Bug: https://github.com/ROCm/rocFFT/issues/439
Bug: https://github.com/ROCm/rocBLAS/issues/1350
Bug: https://bugs.gentoo.org/916069
Closes: https://github.com/llvm/llvm-project/pull/69842
Reviewed by: thesamesam, mgorny
Commit: 777eb35614eff30f8fe8ca7729b9c04846a09476
https://github.com/llvm/llvm-project/commit/777eb35614eff30f8fe8ca7729b9c04846a09476
Author: felixh5678 <157516335+felixh5678 at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/sqrtf128.cpp
A libc/src/math/sqrtf128.h
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/generic_sqrtf128_test.cpp
A libc/test/src/math/smoke/sqrtf128_test.cpp
Log Message:
-----------
[libc] Add sqrtf128 implementation for Linux x86_64. (#79195)
Co-authored-by: Tue Ly <lntue at google.com>
Co-authored-by: Felix <felix at Dirks-MacBook-Pro.local>
Commit: 9fc890b5a06c5e4a014951a1dd7ad7ba592ceaaf
https://github.com/llvm/llvm-project/commit/9fc890b5a06c5e4a014951a1dd7ad7ba592ceaaf
Author: Timm Bäder <tbaeder at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/Parse/ParseDeclCXX.cpp
Log Message:
-----------
[clang][Parse][NFC] Make a local variable const
Commit: 0065d06760c0fba786b7b5ff061b3b3efa08bfbc
https://github.com/llvm/llvm-project/commit/0065d06760c0fba786b7b5ff061b3b3efa08bfbc
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
Log Message:
-----------
[NFC][DebugInfo] Maintain RemoveDIs flag when attributor creates functions (#79143)
We're using this flag (IsNewDbgInfoFormat) to detect the boundaries in
LLVM of what's treating debug-info as intrinsics (i.e. dbg.value), and
what's using DPValue objects (the non-intrinsic replacement). The
attributor tends to create new wrapper functions and doesn't insert them
into Modules in the usual way, thus we have to manually update that flag
to signal what debug-info mode it's using.
I've added some --try-experimental-debuginfo-iterators RUN lines to
tests that would otherwise crash because of this, so that they're
exercised by our new-debuginfo-iterators buildbot.
NB: there's an attributor test with a dbg.value in it, however
attributes re-order themselves in RemoveDIs mode for various reasons, so
we're going to address that in a different patch.
Commit: dc5b4daae7077b644753e53f175d0f5785fede49
https://github.com/llvm/llvm-project/commit/dc5b4daae7077b644753e53f175d0f5785fede49
Author: quic-asaravan <156995626+quic-asaravan at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
A llvm/test/CodeGen/Hexagon/inline-division-space.ll
A llvm/test/CodeGen/Hexagon/inline-division.ll
Log Message:
-----------
[HEXAGON] Inlining Division (#79021)
This patch inlines float division function calls for hexagon.
Co-authored-by: Awanish Pandey <awanpand at codeaurora.org>
Commit: 31f41f0984303655acf4eaa8d09643a624b1ccb0
https://github.com/llvm/llvm-project/commit/31f41f0984303655acf4eaa8d09643a624b1ccb0
Author: Christian Sigg <csigg at google.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[clang][bazel] Fix BUILD after 4a582845597e97d245e8ffdc14281f922b835e56.
Commit: 2e81ac25b4e2bfdc71aac19a911525a7f35680be
https://github.com/llvm/llvm-project/commit/2e81ac25b4e2bfdc71aac19a911525a7f35680be
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
Log Message:
-----------
[AMDGPU][NFC] Simplify AGPR/VGPR load/store operand definitions. (#79289)
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Commit: ca8605a78b8dd531c164f6a48a180ccf2770d042
https://github.com/llvm/llvm-project/commit/ca8605a78b8dd531c164f6a48a180ccf2770d042
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M .ci/generate-buildkite-pipeline-premerge
Log Message:
-----------
[ci] Remove bits that are unused since we stopped using Phabricator
Commit: 17db9efe9274e72f42e7e68103dab920ee494ac8
https://github.com/llvm/llvm-project/commit/17db9efe9274e72f42e7e68103dab920ee494ac8
Author: Jan Leyonberg <jan_sjodin at yahoo.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
Log Message:
-----------
[OpenMP][MLIR] Add omp.distribute op to the OMP dialect (#67720)
This patch adds the omp.distribute operation to the OMP dialect. The
purpose is to be able to represent the distribute construct in OpenMP
with the associated clauses. The effect of the operation is to
distributes the loop iterations of the loop(s) contained inside the
region across multiple teams.
Commit: 8d43dad9b86ad0f72100b6f75450f2982f2663b9
https://github.com/llvm/llvm-project/commit/8d43dad9b86ad0f72100b6f75450f2982f2663b9
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[clang][bazel] Fix BUILD after 4a582845597e97d245e8ffdc14281f922b835e56.
Commit: 6a0118cec079f5963dc5a7a3d9423c55f08b6dad
https://github.com/llvm/llvm-project/commit/6a0118cec079f5963dc5a7a3d9423c55f08b6dad
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M libcxx/docs/index.rst
Log Message:
-----------
[libc++][docs] Remove mention of Phabricator on the landing page
Commit: fc364e26845ce5529caf9f88abcc5a5531d1f59f
https://github.com/llvm/llvm-project/commit/fc364e26845ce5529caf9f88abcc5a5531d1f59f
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M libunwind/docs/index.rst
Log Message:
-----------
[libunwind][doc] Remove reference to Phabricator from the landing page
Commit: 56aa77e1193b7abe65bf3ec16e0f37972345b9f2
https://github.com/llvm/llvm-project/commit/56aa77e1193b7abe65bf3ec16e0f37972345b9f2
Author: Danial Klimkin <dklimkin at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
Fix bazel build past 4a582845597e97d245e8ffdc14281f922b835e56 (#79318)
and keep things sorted.
Commit: 396b6bbc5ecef93fce09d6463f47b44dc501d2aa
https://github.com/llvm/llvm-project/commit/396b6bbc5ecef93fce09d6463f47b44dc501d2aa
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
Log Message:
-----------
[RISCV] Recurse on second operand of two operand shuffles (#79197)
This builds on bdc41106ee48dce59c500c9a3957af947f30c8c3.
This change completes the migration to a recursive shuffle lowering
strategy where when we encounter an unknown two argument shuffle, we
lower each operand as a single source permute, and then use a vselect
(i.e. a vmerge) to combine the results. This relies for code quality on
the post-isel combine which will aggressively fold that vmerge back into
the materialization of the second operand if possible.
Note: The change includes only the most immediately obvious of the
stylistic cleanup. There's a bunch of code movement that this enables
that I'll do as a separate patch as rolling it into this creates an
unreadable diff.
Commit: 611843d24bd1cfa8b6bf62b48635dbd3a6281759
https://github.com/llvm/llvm-project/commit/611843d24bd1cfa8b6bf62b48635dbd3a6281759
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[llvm][bazel] Fix BUILD.
Commit: 4079aab8d80233586a9cd3f7be27bece4c21ea16
https://github.com/llvm/llvm-project/commit/4079aab8d80233586a9cd3f7be27bece4c21ea16
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[llvm][bazel] Fix BUILD
Commit: 56444d5687818938a6ce798e7221aa920c54098e
https://github.com/llvm/llvm-project/commit/56444d5687818938a6ce798e7221aa920c54098e
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/utils/git/github-automation.py
Log Message:
-----------
Remove fork handling from release issue workflow (#79310)
This is currently broken, because the check is performed on the wrong
repository. repo here is llvm/llvm-project, which is not a fork (so this
will always trigger), then we'll push a new branch to
llvmbot/llvm-project, and then again set the wrong owner, so we'll look
for the branch in llvm/llvm-project rather than llvmbot/llvm-project.
Rather than fixing this, I'm removing the code entirely, as it shouldn't
be needed anymore (llvmbot/llvm-project is a fork of llvm/llvm-project).
Commit: 6c1dbd5359c4336d03b11faeaea8459b421f2c5c
https://github.com/llvm/llvm-project/commit/6c1dbd5359c4336d03b11faeaea8459b421f2c5c
Author: Jan Svoboda <jan_svoboda at apple.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/include/clang/Basic/DirectoryEntry.h
M clang/include/clang/Basic/FileEntry.h
M clang/lib/Basic/FileManager.cpp
M clang/unittests/Basic/FileManagerTest.cpp
M llvm/include/llvm/Support/VirtualFileSystem.h
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/unittests/Support/VirtualFileSystemTest.cpp
Log Message:
-----------
[clang] NFC: Remove `{File,Directory}Entry::getName()` (#74910)
The files and directories that Clang accesses are uniqued by their
inode. For each inode `FileManager` will create exactly one `FileEntry`
or `DirectoryEntry` object, which makes answering the question _"Are
these two files/directories the same?"_ a simple pointer equality check.
However, since the same inode can be accessed through multiple different
paths, asking the `FileEntry` or `DirectoryEntry` object _"What is your
name?"_ doesn't have clear semantics. In c0ff9908 we started reporting
the most recent name used to access the entry, which turned out to be
necessary for Clang modules. However, the long-term solution has always
been to explicitly track the as-requested name. This has been
implemented in 4dc5573a as `FileEntryRef` and `DirectoryEntryRef`.
The `DirectoryEntry::getName()` interface has been deprecated since the
Clang 17 release and `FileEntry::getName()` since Clang 18. We have
replaced uses of these deprecated APIs in `main` with
`DirectoryEntryRef::getName()` and `FileEntryRef::getName()`
respectively.
This makes it possible to remove `{File,Directory}Entry::getName()` for
good along with the `FileManager` code that implements them.
Commit: 14fab6137399a57f911c48e49449fdb79db4c269
https://github.com/llvm/llvm-project/commit/14fab6137399a57f911c48e49449fdb79db4c269
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M .ci/generate-buildkite-pipeline-premerge
M .github/workflows/issue-release-workflow.yml
M clang/docs/StandardCPlusPlusModules.rst
M clang/include/clang/AST/Expr.h
M clang/include/clang/Basic/Builtins.def
M clang/include/clang/Basic/Builtins.h
A clang/include/clang/Basic/Builtins.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
R clang/include/clang/Basic/BuiltinsBPF.def
A clang/include/clang/Basic/BuiltinsBPF.td
A clang/include/clang/Basic/BuiltinsBase.td
M clang/include/clang/Basic/CMakeLists.txt
M clang/include/clang/Basic/DirectoryEntry.h
M clang/include/clang/Basic/FileEntry.h
M clang/include/clang/Basic/TargetBuiltins.h
M clang/include/module.modulemap
M clang/lib/AST/ExprCXX.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/StmtPrinter.cpp
M clang/lib/Basic/Builtins.cpp
M clang/lib/Basic/FileManager.cpp
M clang/lib/Basic/Targets/BPF.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/CommonArgs.cpp
M clang/lib/Driver/ToolChains/Hexagon.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Sema/OpenCLBuiltins.td
M clang/lib/Sema/SemaChecking.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/test/AST/ast-dump-coroutine.cpp
M clang/test/Analysis/bstring.c
M clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma.c
M clang/test/CodeGen/aarch64-ls64-inline-asm.c
M clang/test/CodeGen/attr-arm-sve-vector-bits-bitcast.c
M clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/attr-riscv-rvv-vector-bits-bitcast.c
M clang/test/CodeGen/callback_pthread_create.c
M clang/test/CodeGen/cleanup-destslot-simple.c
M clang/test/CodeGen/hexagon-brev-ld-ptr-incdec.c
M clang/test/CodeGen/ms-intrinsics.c
M clang/test/CodeGen/nofpclass.c
M clang/test/CodeGen/union-tbaa1.c
M clang/test/CodeGenCXX/RelativeVTablesABI/dynamic-cast.cpp
M clang/test/CodeGenCXX/RelativeVTablesABI/type-info.cpp
M clang/test/CodeGenCXX/microsoft-abi-dynamic-cast.cpp
M clang/test/CodeGenCXX/microsoft-abi-typeid.cpp
M clang/test/CodeGenObjC/arc-foreach.m
M clang/test/CodeGenObjCXX/arc-cxx11-init-list.mm
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-fp8.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-wmma-w32.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12-wmma-w64.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-w32.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-swmmac-w64.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32-gfx10-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w32.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-wmma-w64.cl
M clang/test/Headers/__clang_hip_math.hip
M clang/test/OpenMP/bug57757.cpp
M clang/tools/clang-repl/CMakeLists.txt
M clang/unittests/Basic/FileManagerTest.cpp
M clang/utils/TableGen/CMakeLists.txt
A clang/utils/TableGen/ClangBuiltinsEmitter.cpp
M clang/utils/TableGen/MveEmitter.cpp
M clang/utils/TableGen/TableGen.cpp
M clang/utils/TableGen/TableGenBackends.h
M compiler-rt/lib/builtins/CMakeLists.txt
A cross-project-tests/amdgpu/builtins-amdgcn-gfx12-wmma-w32.cl
A cross-project-tests/amdgpu/builtins-amdgcn-gfx12-wmma-w64.cl
A cross-project-tests/amdgpu/builtins-amdgcn-swmmac-w32.cl
A cross-project-tests/amdgpu/builtins-amdgcn-swmmac-w64.cl
R flang/include/flang/Optimizer/Builder/Array.h
M flang/include/flang/Optimizer/Builder/BoxValue.h
M flang/lib/Lower/ConvertVariable.cpp
M flang/lib/Lower/DirectivesCommon.h
M flang/lib/Lower/OpenMP.cpp
M flang/lib/Optimizer/Builder/BoxValue.cpp
M flang/lib/Optimizer/Builder/IntrinsicCall.cpp
M flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp
M flang/test/HLFIR/no-block-merging.fir
A flang/test/Lower/HLFIR/assumed-size-cray-pointee.f90
M flang/test/Lower/HLFIR/cray-pointers.f90
M flang/test/Lower/Intrinsics/lbound.f90
M flang/test/Lower/Intrinsics/ubound.f90
M flang/test/Lower/array-expression-assumed-size.f90
M flang/test/Lower/cray-pointer.f90
M libc/config/linux/x86_64/entrypoints.txt
M libc/docs/math/index.rst
M libc/spec/stdc.td
M libc/src/math/CMakeLists.txt
M libc/src/math/generic/CMakeLists.txt
A libc/src/math/generic/sqrtf128.cpp
A libc/src/math/sqrtf128.h
M libc/test/src/math/smoke/CMakeLists.txt
A libc/test/src/math/smoke/generic_sqrtf128_test.cpp
A libc/test/src/math/smoke/sqrtf128_test.cpp
M libcxx/docs/index.rst
M libcxx/include/__algorithm/ranges_max.h
M libcxx/include/__algorithm/ranges_min.h
M libcxx/include/string
M libunwind/docs/index.rst
M llvm/include/llvm/Analysis/Loads.h
M llvm/include/llvm/DebugInfo/DWARF/DWARFAcceleratorTable.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/Support/VirtualFileSystem.h
M llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h
M llvm/lib/Analysis/Lint.cpp
M llvm/lib/Analysis/Loads.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/MemorySSAUpdater.cpp
M llvm/lib/DebugInfo/DWARF/DWARFAcceleratorTable.cpp
M llvm/lib/DebugInfo/DWARF/DWARFFormValue.cpp
M llvm/lib/Support/BLAKE3/blake3_avx2_x86-64_unix.S
M llvm/lib/Support/BLAKE3/blake3_avx512_x86-64_unix.S
M llvm/lib/Support/BLAKE3/blake3_sse2_x86-64_unix.S
M llvm/lib/Support/BLAKE3/blake3_sse41_x86-64_unix.S
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/lib/Target/AArch64/AArch64.td
M llvm/lib/Target/AArch64/AArch64StackTagging.cpp
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
M llvm/lib/Target/AMDGPU/AMDGPUImageIntrinsicOptimizer.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrFormats.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp
M llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.h
M llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
M llvm/lib/Target/Hexagon/HexagonISelLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86FlagsCopyLowering.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/Transforms/IPO/Attributor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp
M llvm/lib/Transforms/Scalar/ConstraintElimination.cpp
M llvm/lib/Transforms/Scalar/JumpThreading.cpp
M llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp
M llvm/test/Analysis/BasicAA/featuretest.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-reverse.ll
M llvm/test/Analysis/LoopAccessAnalysis/noalias-scope-decl.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/intrinsics.ll
M llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-imm.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w32.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-imm.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/GlobalISel/wmma-gfx12-w64.ll
M llvm/test/CodeGen/AMDGPU/indirect-call-known-callees.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.mir
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll
A llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-hsa.ll
A llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll
R llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/vector-alloca-bitcast.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-imm.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-imm.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-iu-modifiers.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64-swmmac-index_key.ll
A llvm/test/CodeGen/AMDGPU/wmma-gfx12-w64.ll
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w32.mir
A llvm/test/CodeGen/AMDGPU/wmma-hazards-gfx12-w64.mir
M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
M llvm/test/CodeGen/AMDGPU/workgroup-id-in-arch-sgprs.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/load-inline.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll-inline.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/load-unroll.ll
M llvm/test/CodeGen/BPF/preserve-static-offset/store-unroll-inline.ll
M llvm/test/CodeGen/Hexagon/autohvx/vector-align-tbaa.ll
A llvm/test/CodeGen/Hexagon/inline-division-space.ll
A llvm/test/CodeGen/Hexagon/inline-division.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-exact-vlen.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-transpose.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll
M llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll
M llvm/test/CodeGen/X86/2011-20-21-zext-ui2fp.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/CodeGen/X86/avx-load-store.ll
M llvm/test/CodeGen/X86/avx2-arith.ll
M llvm/test/CodeGen/X86/avx512-shuffles/shuffle-chained-bf16.ll
M llvm/test/CodeGen/X86/bitreverse.ll
M llvm/test/CodeGen/X86/combine-srl.ll
M llvm/test/CodeGen/X86/combine-subo.ll
M llvm/test/CodeGen/X86/commute-blend-avx2.ll
M llvm/test/CodeGen/X86/constant-pool-sharing.ll
M llvm/test/CodeGen/X86/dpbusd.ll
M llvm/test/CodeGen/X86/dpbusd_const.ll
A llvm/test/CodeGen/X86/dwarf-headers.o
M llvm/test/CodeGen/X86/expand-vp-cast-intrinsics.ll
M llvm/test/CodeGen/X86/fcmp-constant.ll
M llvm/test/CodeGen/X86/fold-vector-sext-zext.ll
M llvm/test/CodeGen/X86/half.ll
A llvm/test/CodeGen/X86/icmp-pow2-mask.ll
M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
M llvm/test/CodeGen/X86/insertelement-ones.ll
M llvm/test/CodeGen/X86/masked_gather_scatter_widen.ll
M llvm/test/CodeGen/X86/masked_store_trunc.ll
M llvm/test/CodeGen/X86/memcmp-more-load-pairs.ll
M llvm/test/CodeGen/X86/memcmp.ll
M llvm/test/CodeGen/X86/pmaddubsw.ll
M llvm/test/CodeGen/X86/pr46532.ll
M llvm/test/CodeGen/X86/pr63108.ll
M llvm/test/CodeGen/X86/pr74736.ll
M llvm/test/CodeGen/X86/prefer-avx256-lzcnt.ll
M llvm/test/CodeGen/X86/pshufb-mask-comments.ll
M llvm/test/CodeGen/X86/ret-mmx.ll
M llvm/test/CodeGen/X86/sad.ll
M llvm/test/CodeGen/X86/sext-vsetcc.ll
M llvm/test/CodeGen/X86/shrink_vmul.ll
M llvm/test/CodeGen/X86/shuffle-half.ll
M llvm/test/CodeGen/X86/shuffle-strided-with-offset-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-256.ll
M llvm/test/CodeGen/X86/shuffle-vs-trunc-512.ll
M llvm/test/CodeGen/X86/sse2-intrinsics-x86.ll
M llvm/test/CodeGen/X86/vec_anyext.ll
M llvm/test/CodeGen/X86/vec_fp_to_int.ll
M llvm/test/CodeGen/X86/vec_set-A.ll
M llvm/test/CodeGen/X86/vector-blend.ll
M llvm/test/CodeGen/X86/vector-constrained-fp-intrinsics.ll
M llvm/test/CodeGen/X86/vector-fshl-128.ll
M llvm/test/CodeGen/X86/vector-fshl-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshl-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshl-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-128.ll
M llvm/test/CodeGen/X86/vector-fshr-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-128.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-256.ll
M llvm/test/CodeGen/X86/vector-fshr-rot-sub128.ll
M llvm/test/CodeGen/X86/vector-fshr-sub128.ll
M llvm/test/CodeGen/X86/vector-half-conversions.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-2.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
M llvm/test/CodeGen/X86/vector-lzcnt-128.ll
M llvm/test/CodeGen/X86/vector-lzcnt-256.ll
M llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
M llvm/test/CodeGen/X86/vector-rotate-128.ll
M llvm/test/CodeGen/X86/vector-rotate-256.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-sub128.ll
M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
M llvm/test/CodeGen/X86/vector-trunc.ll
M llvm/test/CodeGen/X86/vector-tzcnt-128.ll
M llvm/test/CodeGen/X86/vselect-constants.ll
M llvm/test/CodeGen/X86/vselect-post-combine.ll
M llvm/test/CodeGen/X86/widen_bitcnt.ll
M llvm/test/CodeGen/X86/x86-interleaved-access.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll
M llvm/test/DebugInfo/Generic/debug-names-one-cu.ll
M llvm/test/DebugInfo/X86/debug-names-dwarf64.ll
M llvm/test/DebugInfo/X86/debug-names-parents-same-offset.ll
M llvm/test/DebugInfo/X86/debug-names-types.ll
M llvm/test/Instrumentation/HWAddressSanitizer/RISCV/alloca.ll
M llvm/test/Instrumentation/HWAddressSanitizer/alloca.ll
M llvm/test/MC/AArch64/armv8.1a-rdma.s
M llvm/test/MC/AArch64/armv8.2a-dotprod-errors.s
M llvm/test/MC/AArch64/armv8.2a-dotprod.s
M llvm/test/MC/AArch64/armv8r-sysreg.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3_from_vop1_dpp8.s
A llvm/test/MC/AMDGPU/gfx12_asm_wmma_w32.s
A llvm/test/MC/AMDGPU/gfx12_asm_wmma_w64.s
M llvm/test/MC/Disassembler/AArch64/armv8.3a-complex.txt
M llvm/test/MC/Disassembler/AArch64/armv8.3a-js.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop1_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_from_vop1_dpp8.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w32.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_wmma_w64.txt
M llvm/test/Transforms/Attributor/ArgumentPromotion/alignment.ll
M llvm/test/Transforms/ConstraintElimination/minmax.ll
A llvm/test/Transforms/ConstraintElimination/umin-result-may-be-poison.ll
M llvm/test/Transforms/Coroutines/coro-async.ll
M llvm/test/Transforms/Coroutines/coro-retcon-alloca-opaque-ptr.ll
M llvm/test/Transforms/Coroutines/coro-retcon-alloca.ll
M llvm/test/Transforms/Coroutines/coro-retcon-once-value.ll
M llvm/test/Transforms/Coroutines/coro-retcon-resume-values.ll
M llvm/test/Transforms/Coroutines/coro-swifterror.ll
M llvm/test/Transforms/InstCombine/2007-03-25-BadShiftMask.ll
M llvm/test/Transforms/InstCombine/2009-01-08-AlignAlloca.ll
M llvm/test/Transforms/InstCombine/2009-02-20-InstCombine-SROA.ll
M llvm/test/Transforms/InstCombine/X86/x86-addsub-inseltpoison.ll
M llvm/test/Transforms/InstCombine/X86/x86-addsub.ll
M llvm/test/Transforms/InstCombine/add3.ll
M llvm/test/Transforms/InstCombine/array.ll
M llvm/test/Transforms/InstCombine/assume.ll
M llvm/test/Transforms/InstCombine/cast_phi.ll
M llvm/test/Transforms/InstCombine/catchswitch-phi.ll
M llvm/test/Transforms/InstCombine/compare-alloca.ll
M llvm/test/Transforms/InstCombine/extractvalue.ll
M llvm/test/Transforms/InstCombine/gep-addrspace.ll
M llvm/test/Transforms/InstCombine/gep-canonicalize-constant-indices.ll
M llvm/test/Transforms/InstCombine/gep-combine-loop-invariant.ll
M llvm/test/Transforms/InstCombine/gep-custom-dl.ll
M llvm/test/Transforms/InstCombine/gep-merge-constant-indices.ll
M llvm/test/Transforms/InstCombine/gep-vector-indices.ll
M llvm/test/Transforms/InstCombine/gep-vector.ll
M llvm/test/Transforms/InstCombine/gepphigep.ll
M llvm/test/Transforms/InstCombine/getelementptr.ll
M llvm/test/Transforms/InstCombine/icmp-custom-dl.ll
M llvm/test/Transforms/InstCombine/icmp-gep.ll
M llvm/test/Transforms/InstCombine/indexed-gep-compares.ll
M llvm/test/Transforms/InstCombine/intptr1.ll
M llvm/test/Transforms/InstCombine/intptr2.ll
M llvm/test/Transforms/InstCombine/intptr3.ll
M llvm/test/Transforms/InstCombine/intptr4.ll
M llvm/test/Transforms/InstCombine/intptr5.ll
M llvm/test/Transforms/InstCombine/intptr7.ll
M llvm/test/Transforms/InstCombine/load-store-forward.ll
M llvm/test/Transforms/InstCombine/load.ll
M llvm/test/Transforms/InstCombine/loadstore-metadata.ll
M llvm/test/Transforms/InstCombine/memchr-5.ll
M llvm/test/Transforms/InstCombine/memchr-9.ll
M llvm/test/Transforms/InstCombine/memcmp-3.ll
M llvm/test/Transforms/InstCombine/memcmp-4.ll
M llvm/test/Transforms/InstCombine/memcmp-5.ll
M llvm/test/Transforms/InstCombine/memcmp-6.ll
M llvm/test/Transforms/InstCombine/memcmp-7.ll
M llvm/test/Transforms/InstCombine/memcpy_alloca.ll
M llvm/test/Transforms/InstCombine/memrchr-5.ll
M llvm/test/Transforms/InstCombine/memset2.ll
M llvm/test/Transforms/InstCombine/multi-size-address-space-pointer.ll
M llvm/test/Transforms/InstCombine/non-integral-pointers.ll
M llvm/test/Transforms/InstCombine/opaque-ptr.ll
M llvm/test/Transforms/InstCombine/phi-equal-incoming-pointers.ll
M llvm/test/Transforms/InstCombine/phi-timeout.ll
M llvm/test/Transforms/InstCombine/phi.ll
M llvm/test/Transforms/InstCombine/pr39908.ll
M llvm/test/Transforms/InstCombine/pr44242.ll
M llvm/test/Transforms/InstCombine/pr58901.ll
M llvm/test/Transforms/InstCombine/ptr-replace-alloca.ll
M llvm/test/Transforms/InstCombine/select-cmp-br.ll
M llvm/test/Transforms/InstCombine/select-gep.ll
M llvm/test/Transforms/InstCombine/shift.ll
M llvm/test/Transforms/InstCombine/sink_sideeffecting_instruction.ll
M llvm/test/Transforms/InstCombine/sprintf-2.ll
M llvm/test/Transforms/InstCombine/statepoint-cleanup.ll
M llvm/test/Transforms/InstCombine/str-int-3.ll
M llvm/test/Transforms/InstCombine/str-int-4.ll
M llvm/test/Transforms/InstCombine/str-int-5.ll
M llvm/test/Transforms/InstCombine/str-int.ll
M llvm/test/Transforms/InstCombine/strcall-bad-sig.ll
M llvm/test/Transforms/InstCombine/strcall-no-nul.ll
M llvm/test/Transforms/InstCombine/strlen-7.ll
M llvm/test/Transforms/InstCombine/strlen-9.ll
M llvm/test/Transforms/InstCombine/strncmp-4.ll
M llvm/test/Transforms/InstCombine/strncmp-5.ll
M llvm/test/Transforms/InstCombine/strncmp-6.ll
M llvm/test/Transforms/InstCombine/sub.ll
M llvm/test/Transforms/InstCombine/unpack-fca.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_demanded_elts.ll
M llvm/test/Transforms/InstCombine/vec_gep_scalar_arg-inseltpoison.ll
M llvm/test/Transforms/InstCombine/vec_gep_scalar_arg.ll
M llvm/test/Transforms/InstCombine/vscale_gep.ll
M llvm/test/Transforms/InstCombine/wcslen-5.ll
A llvm/test/Transforms/JumpThreading/pr79175.ll
M llvm/test/Transforms/LoopUnroll/ARM/upperbound.ll
M llvm/test/Transforms/LoopUnroll/peel-loop.ll
M llvm/test/Transforms/LoopVectorize/AArch64/deterministic-type-shrinkage.ll
M llvm/test/Transforms/LoopVectorize/AArch64/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-cond-inv-loads.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll
M llvm/test/Transforms/LoopVectorize/AArch64/vector-reverse-mask4.ll
M llvm/test/Transforms/LoopVectorize/AMDGPU/packed-math.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-qabs.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-reductions.ll
M llvm/test/Transforms/LoopVectorize/ARM/mve-selectandorcost.ll
M llvm/test/Transforms/LoopVectorize/ARM/pointer_iv.ll
M llvm/test/Transforms/LoopVectorize/X86/float-induction-x86.ll
M llvm/test/Transforms/LoopVectorize/X86/interleaving.ll
M llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
M llvm/test/Transforms/LoopVectorize/X86/invariant-store-vectorization.ll
M llvm/test/Transforms/LoopVectorize/X86/metadata-enable.ll
M llvm/test/Transforms/LoopVectorize/X86/pr23997.ll
M llvm/test/Transforms/LoopVectorize/X86/small-size.ll
M llvm/test/Transforms/LoopVectorize/X86/x86-interleaved-store-accesses-with-gaps.ll
M llvm/test/Transforms/LoopVectorize/consecutive-ptr-uniforms.ll
M llvm/test/Transforms/LoopVectorize/extract-last-veclane.ll
M llvm/test/Transforms/LoopVectorize/float-induction.ll
M llvm/test/Transforms/LoopVectorize/induction.ll
M llvm/test/Transforms/LoopVectorize/interleaved-accesses.ll
M llvm/test/Transforms/LoopVectorize/reduction-inloop-uf4.ll
M llvm/test/Transforms/LoopVectorize/runtime-check.ll
M llvm/test/Transforms/LoopVectorize/scalar_after_vectorization.ll
M llvm/test/Transforms/LoopVectorize/vector-geps.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-dominance.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-loops.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused-multiple-blocks.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-fused.ll
M llvm/test/Transforms/LowerMatrixIntrinsics/multiply-minimal.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/hoisting-sinking-required-for-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/peel-multiple-unreachable-exits-for-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/quant_4x4.ll
M llvm/test/Transforms/PhaseOrdering/AArch64/sinking-vs-if-conversion.ll
M llvm/test/Transforms/PhaseOrdering/ARM/arm_mult_q15.ll
M llvm/test/Transforms/PhaseOrdering/X86/excessive-unrolling.ll
M llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll
A llvm/test/Transforms/PhaseOrdering/X86/loop-vectorizer-noalias.ll
M llvm/test/Transforms/PhaseOrdering/X86/pixel-splat.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr48844-br-to-switch-vectorization.ll
M llvm/test/Transforms/PhaseOrdering/X86/pr50555.ll
M llvm/test/Transforms/PhaseOrdering/X86/speculation-vs-tbaa.ll
M llvm/test/Transforms/PhaseOrdering/X86/spurious-peeling.ll
M llvm/test/Transforms/PhaseOrdering/X86/vdiv.ll
M llvm/test/Transforms/PhaseOrdering/X86/vec-shift.ll
M llvm/test/Transforms/PhaseOrdering/basic.ll
M llvm/test/Transforms/PhaseOrdering/loop-access-checks.ll
M llvm/test/Transforms/PhaseOrdering/pr39282.ll
M llvm/test/Transforms/PhaseOrdering/simplifycfg-options.ll
M llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-cost.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/gather-reduce.ll
M llvm/test/Transforms/SLPVectorizer/AArch64/loadorder.ll
M llvm/test/Transforms/SLPVectorizer/WebAssembly/no-vectorize-rotate.ll
M llvm/test/Transforms/SLPVectorizer/X86/operandorder.ll
M llvm/test/Transforms/SLPVectorizer/X86/opt.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629-inseltpoison.ll
M llvm/test/Transforms/SLPVectorizer/X86/pr47629.ll
M llvm/test/Transforms/SampleProfile/pseudo-probe-instcombine.ll
M llvm/test/Transforms/SimpleLoopUnswitch/memssa-readnone-access.ll
M llvm/test/Transforms/Util/strip-gc-relocates.ll
M llvm/test/tools/dsymutil/ARM/accel-imported-declarations.test
M llvm/unittests/Support/VirtualFileSystemTest.cpp
M llvm/utils/git/github-automation.py
M mlir/include/mlir/Dialect/LLVMIR/ROCDLOps.td
M mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td
M mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/test/Dialect/OpenMP/invalid.mlir
M mlir/test/Dialect/OpenMP/ops.mlir
M mlir/test/Dialect/Vector/canonicalize.mlir
M mlir/test/Target/LLVMIR/rocdl.mlir
M openmp/libomptarget/test/offloading/fortran/target_map_common_block1.f90
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
M utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
Log Message:
-----------
fix typo. clarify .debug_addr
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/5296604ff5f9...14fab6137399
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