[all-commits] [llvm/llvm-project] 33d804: [RISCV] Allow VCIX with SE to reorder (#77049)

[Brandon Wu via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 33d804c6c2786cbbbc13743060f08d679941e0a4
      https://github.com/llvm/llvm-project/commit/33d804c6c2786cbbbc13743060f08d679941e0a4
  Author: Brandon Wu <brandon.wu at sifive.com>
  Date:   2024-01-24 (Wed, 24 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    M llvm/lib/Target/RISCV/RISCVISelLowering.h
    M llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
    M llvm/lib/Target/RISCV/RISCVRegisterInfo.td
    M llvm/test/CodeGen/RISCV/pr69586.ll

  Log Message:
  -----------
  [RISCV] Allow VCIX with SE to reorder (#77049)

This patch allows VCIX instructions that have side effect to be
reordered
with memory and other side effecting instructions. However we don't want
VCIX instructions to be reordered with each other, so we propose a dummy
register called VCIX_STATE and make these instructions implicitly define
and use
it.