[all-commits] [llvm/llvm-project] c28ab6: [NFCI] Move SANITIZER_WEAK_IMPORT to sanitizer_com...
Fangrui Song via All-commits
all-commits at lists.llvm.org
Tue Jan 23 18:57:41 PST 2024
Branch: refs/heads/users/MaskRay/spr/driver-test-ignored-target-specific-options-for-amdgpunvptx
Home: https://github.com/llvm/llvm-project
Commit: c28ab6274322da693ea41a49e301c15b551c974a
https://github.com/llvm/llvm-project/commit/c28ab6274322da693ea41a49e301c15b551c974a
Author: Chris Apple <14171107+cjappl at users.noreply.github.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
M compiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h
Log Message:
-----------
[NFCI] Move SANITIZER_WEAK_IMPORT to sanitizer_common (#79208)
SANITIZER_WEAK_IMPORT is useful for any call that needs to be
conditionally linked in. This is currently used for the
tsan_dispatch_interceptors, but can be used for other calls introduced
in newer versions of MacOS. (such as `aligned_alloc` in this PR
https://github.com/llvm/llvm-project/pull/79198).
This PR moves the definition to a higher level so it can be used in
other sanitizers.
Commit: 575568de4166bf69e0a5bc68978580afbe936878
https://github.com/llvm/llvm-project/commit/575568de4166bf69e0a5bc68978580afbe936878
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir
Log Message:
-----------
[mlir][sparse] adjust compression scheme for example (#79212)
Commit: 750e90e4403df23d6b271afb90e6b4d463739965
https://github.com/llvm/llvm-project/commit/750e90e4403df23d6b271afb90e6b4d463739965
Author: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M mlir/include/mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/ArithToAMDGPU/CMakeLists.txt
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
A mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-floats.mlir
Log Message:
-----------
[mlir][ArithToAMDGPU] Add option for saturating truncation to fp8 (#74153)
Many machine-learning applications (and most software written at AMD)
expect the operation that truncates floats to 8-bit floats to be
saturatinng. That is, they expect `truncf 256.0 : f32 to f8E4M3FNUZ` to
yield `240.0`, not `NaN`, and similarly for negative numbers. However,
the underlying hardware instruction that can be used for this truncation
implements overflow-to-NaN semantics.
To enable handling this usecase, we add the saturate-fp8-truncf option
to ArithToAMDGPU (off by default), which causes the requisite clamping
code to be emitted. Said clamping code ensures that Inf and NaN are
passed through exactly (and thus trancate to NaN).
Per review feedback, this commit efactors
createScalarOrSplatConstant() to the Arith dialect utilities and uses
it in this code. It also fixes naming of existing patterns and
switches from vector.extractelement/insertelement to
vector.extract/insert.
Commit: 7fc25928233c133a4af1dadf0e060fb5d42ebd4e
https://github.com/llvm/llvm-project/commit/7fc25928233c133a4af1dadf0e060fb5d42ebd4e
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/Function.h
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/test/DebugInfo/salvage-limit-expr-size.ll
M llvm/test/Transforms/Util/strip-nonlinetable-debuginfo-localvars.ll
Log Message:
-----------
[DebugInfo][RemoveDIs] "Final" cleanup for non-instr debug-info (#79121)
Here's a raft of minor fixes for the RemoveDIs project that's replacing
dbg.value intrinsics with DPValue objects, all IMO trivial:
* When inserting functions or blocks and calling setIsNewDbgInfoFormat,
do that after setting the Parent pointer, just in case conversion from
(or to) dbg.value mode is triggered.
* When transferring DPValues from an empty range in a splice call, don't
transfer if there are no DPValues attached to the source block at all.
* stripNonLineTableDebugInfo should drop DPValues.
* In insertBefore, don't try to transfer DPValues if there aren't any.
Commit: a16f81f5e3313e88f96de35e5edfe8bee463d308
https://github.com/llvm/llvm-project/commit/a16f81f5e3313e88f96de35e5edfe8bee463d308
Author: Thurston Dang <thurston at google.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M libcxx/include/string
R libcxx/test/libcxx/containers/strings/basic.string/asan_deque_integration.pass.cpp
R libcxx/test/libcxx/containers/strings/basic.string/asan_short.pass.cpp
R libcxx/test/libcxx/containers/strings/basic.string/asan_vector_integration.pass.cpp
M libcxx/test/support/asan_testing.h
Log Message:
-----------
Revert "[ASan][libc++] Turn on ASan annotations for short strings (#79049)"
This reverts commit cb528ec5e6331ce207c7b835d7ab963bd5e13af7.
Reason: buildbot breakage (https://lab.llvm.org/buildbot/#/builders/5/builds/40364):
SUMMARY: AddressSanitizer: container-overflow /b/sanitizer-x86_64-linux-fast/build/libcxx_build_asan_ubsan/include/c++/v1/string:1870:29 in __get_long_pointer
Commit: 22da8096020fcf54bae2f885882bbd088a4dcd9b
https://github.com/llvm/llvm-project/commit/22da8096020fcf54bae2f885882bbd088a4dcd9b
Author: Jeremy Morse <jeremy.morse at sony.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
A llvm/docs/RemoveDIsDebugInfo.md
M llvm/docs/UserGuides.rst
Log Message:
-----------
[Docs][DebugInfo][RemoveDIs] Document some debug-info transition info (#79167)
This is a high level description and FAQ for what we're doing in
RemoveDIs, and how old code should be behave with new debug-info
(exactly the same 99% of the time).
Commit: 6a3ace20c80191159009668fff82fc3feeeca0a6
https://github.com/llvm/llvm-project/commit/6a3ace20c80191159009668fff82fc3feeeca0a6
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
R libc/src/threads/linux/call_once.cpp
R libc/src/threads/linux/thread_start_args.h.def
Log Message:
-----------
[libc] remove redundant call_once (#79226)
Missed cleanup from https://reviews.llvm.org/D134716.
Fixes: #79220
Commit: 2a61be4e4ca481016516403f634b475197221991
https://github.com/llvm/llvm-project/commit/2a61be4e4ca481016516403f634b475197221991
Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
Log Message:
-----------
[SROA] NFC: Extract code to checkVectorTypesForPromotion
Change-Id: Ib6f237cc791a097f8f2411bc1d6502f11d4a748e
Commit: 25e1916d88ebeef786956b678a4eb9a757e219d9
https://github.com/llvm/llvm-project/commit/25e1916d88ebeef786956b678a4eb9a757e219d9
Author: Alan Zhao <alanzhao1 at users.noreply.github.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M clang/test/CodeGenCXX/new-array-init.cpp
Log Message:
-----------
[nfc][clang] Fix test in new-array-init.cpp (#79225)
This test was originally introduced in
https://github.com/llvm/llvm-project/pull/76976, but it incorrectly
tests braced-list initialization instead of parenthesized
initialization.
Commit: d657519838e4b2310e13ec5ff52599e041860825
https://github.com/llvm/llvm-project/commit/d657519838e4b2310e13ec5ff52599e041860825
Author: Pete Lawrence <plawrence at apple.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M lldb/source/Core/ValueObject.cpp
Log Message:
-----------
[lldb] Improve maintainability and readability for ValueObject methods (#75865)
As I worked through changes to another PR
(https://github.com/llvm/llvm-project/pull/74912), I couldn't help but
rewrite a few methods for readability, maintainability, and possibly
some behavior correctness too.
1. Exiting early instead of nested `if`-statements, which:
- Reduces indentation levels for all subsequent lines
- Treats missing pre-conditions similar to an error
- Clearly indicates that the full length of the method is the "happy
path".
2. Explicitly return empty Value Object shared pointers for those error
(like) situations, which
- Reduces the time it takes a maintainer to figure out what the method
actually returns based on those conditions.
3. Converting a mix of `if` and `if`-`else`-statements around an enum
into one `switch` statement, which:
- Consolidates the former branching logic
- Lets the compiler warn you of a (future) missing enum case
- This one may actually change behavior slightly, because what was an
early test for one enum case, now happens later on in the `switch`.
4. Consolidating near-identical, "copy-pasta" logic into one place,
which:
- Separates the common code to the diverging paths.
- Highlights the differences between the code paths.
rdar://119833526
Commit: 03a61d34ebf4f8eeaa6861bec3ab39c75bb41778
https://github.com/llvm/llvm-project/commit/03a61d34ebf4f8eeaa6861bec3ab39c75bb41778
Author: Paul Kirth <paulkirth at google.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/TargetMachine.cpp
M llvm/test/CodeGen/RISCV/tls-models.ll
M llvm/test/MC/RISCV/relocations.s
A llvm/test/MC/RISCV/tlsdesc.s
Log Message:
-----------
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
This patch adds basic TLSDESC support in the RISC-V backend.
Specifically, we add new relocation types for TLSDESC, as prescribed in
https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/373, and add a
new pseudo instruction to simplify code generation.
This patch does not try to optimize the local dynamic case, which can be
improved in separate patches.
Linker side changes will also be handled separately.
The current implementation is only enabled when passing the new
`-enable-tlsdesc` codegen flag.
Commit: df1e01b316b174b5aa10727bd2ee0ec1082a9f65
https://github.com/llvm/llvm-project/commit/df1e01b316b174b5aa10727bd2ee0ec1082a9f65
Author: Jeff Niu <jeff at modular.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M mlir/test/IR/print-attr-type-aliases.mlir
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
Log Message:
-----------
[mlir] Add example of `printAlias` to test dialect (NFC) (#79232)
Follow-up from previous pull request. Motivate the API change with an
attribute that decides between sugaring a sub-attribute or using an
alias
Commit: 766e645d8d1e9e999386b90e3e19554d72324a66
https://github.com/llvm/llvm-project/commit/766e645d8d1e9e999386b90e3e19554d72324a66
Author: Jeffrey Byrnes <Jeffrey.Byrnes at amd.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/test/Transforms/SROA/vector-promotion.ll
Log Message:
-----------
[SROA] NFC: Precommit test for pull/77678
Change-Id: I6b2346301f9bd840a0adceba4a0d03e9932af245
Commit: b1778c7d7b9ec07c075118546b85a7cc9741e1f1
https://github.com/llvm/llvm-project/commit/b1778c7d7b9ec07c075118546b85a7cc9741e1f1
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
R llvm/test/CodeGen/Generic/bb-profile-dump.ll
Log Message:
-----------
[AsmPrinter] Remove mbb-profile-dump flag (#76595)
Now that the work embedding PGO information in SHT_LLVM_BB_ADDR_MAP ELF
sections has landed, there is no longer a need to keep around the
mbb-profile-dump flag.
Commit: c41472dbafd0dcacd943a95a9a099c1942d50394
https://github.com/llvm/llvm-project/commit/c41472dbafd0dcacd943a95a9a099c1942d50394
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M .github/workflows/libclang-python-tests.yml
Log Message:
-----------
[Github] Only run libclang-python-tests on monorepo main
The libclang python binding test CI job currently doesn't have any
restrictions on what branches it will run on when something is pushed
and also isn't restricted to the monorepo. This patch adds a branch
restriction for the push event, only running the CI job when something
is pushed to the main branch (and the path filter is met), and also adds
a filter to ensure that the job comes from a PR against the monorepo or
a push to a branch in the monorepo.
Commit: c51ab483e6c2d991a01179584705b83fbea1940d
https://github.com/llvm/llvm-project/commit/c51ab483e6c2d991a01179584705b83fbea1940d
Author: Jinyang He <hejinyang at loongson.cn>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
A llvm/test/MC/LoongArch/Relocations/align-non-executable.s
M llvm/test/MC/LoongArch/Relocations/relax-addsub.s
A llvm/test/MC/LoongArch/Relocations/relax-align.s
Log Message:
-----------
[LoongArch] Insert nops and emit align reloc when handle alignment directive (#72962)
Refer to RISCV, we will fix up the alignment if linker relaxation
changes code size and breaks alignment. Insert enough Nops and emit
R_LARCH_ALIGN relocation type so that linker could satisfy the alignment
by removing Nops.
It does so only in sections with the SHF_EXECINSTR flag.
In LoongArch psABI v2.30, R_LARCH_ALIGN requires symbol index. The
lowest 8 bits of addend represent alignment and the other bits of addend
represent the maximum number of bytes to emit.
Commit: f709fbb1bb5e6240aad4edeb2f0e417df74cfa27
https://github.com/llvm/llvm-project/commit/f709fbb1bb5e6240aad4edeb2f0e417df74cfa27
Author: Jeffrey Byrnes <jeffrey.byrnes at amd.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/Transforms/SROA/vector-promotion.ll
Log Message:
-----------
[SROA] Only try additional vector type candidates when needed (#77678)
https://github.com/llvm/llvm-project/commit/f9c2a341b94ca71508dcefa109ece843459f7f13
causes regressions when we have a slice with integer vector type that is
the same size as the partition, and a ptr load/store slice that is not
the size of the element type.
Ref `vector-promotion.ll:ptrLoadStoreTys`.
Before the patch, we would only consider `<4 x i32>` as a candidate type
for vector promotion, and would find that it is a viable type for all
the slices.
After the patch, we now add `<2 x ptr>` as a candidate type due to slice
with user `store ptr %val0, ptr %obj, align 8` -- and flag that we
`HaveVecPtrTy`. The pre-existing behavior of this flag results in
removing the viable `<4 x i32>` and keeping only the unviable `<2 x
ptr>`, which results in a failure to promote.
The end result is failing to promote an alloca that was previously
promoted -- this does not appear to be the intent of that patch, which
has the goal of increasing promotions by providing more promotion
opportunities.
This PR preserves this behavior via a simple reorganization of the
implemention: try first the slice types with same size as the partition,
then, if there is no promotable type, try the `LoadStoreTys.`
Commit: c663c8b8839e8a3e780426c1ab4d0005df90a116
https://github.com/llvm/llvm-project/commit/c663c8b8839e8a3e780426c1ab4d0005df90a116
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M lld/test/ELF/dead-reloc-in-nonalloc.s
Log Message:
-----------
[ELF,test] Improve dead-reloc-in-nonalloc.s
Test an absolute relocation referencing a DSO symbol, relocating a
non-SHF_ALLOC section. Also test --gc-sections.
Commit: 7e50f006f7f652b9a5ac5ddd64deba5f1c9388a8
https://github.com/llvm/llvm-project/commit/7e50f006f7f652b9a5ac5ddd64deba5f1c9388a8
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Target/X86/CMakeLists.txt
A llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
A llvm/test/tools/llc/new-pm/lit.local.cfg
A llvm/test/tools/llc/new-pm/option-conflict.ll
A llvm/test/tools/llc/new-pm/pipeline.ll
A llvm/test/tools/llc/new-pm/start-stop.ll
M llvm/tools/llc/CMakeLists.txt
A llvm/tools/llc/NewPMDriver.cpp
A llvm/tools/llc/NewPMDriver.h
M llvm/tools/llc/llc.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
R llvm/unittests/CodeGen/CodeGenPassBuilderTest.cpp
Log Message:
-----------
[NewPM][CodeGen][llc] Add NPM support (#70922)
Add new pass manager support to `llc`. Users can use
`--passes=pass1,pass2...` to run mir passes, and use `--enable-new-pm`
to run default codegen pipeline.
This patch is taken from [D83612](https://reviews.llvm.org/D83612), the
original author is @yuanfang-chen.
---------
Co-authored-by: Yuanfang Chen <455423+yuanfang-chen at users.noreply.github.com>
Commit: 230c13d59d0843c3b738920b85c341cc78a61fa9
https://github.com/llvm/llvm-project/commit/230c13d59d0843c3b738920b85c341cc78a61fa9
Author: Christudasan Devadasan <christudasan.devadasan at amd.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
Log Message:
-----------
[AMDGPU] Pick available high VGPR for CSR SGPR spilling (#78669)
CSR SGPR spilling currently uses the early available physical VGPRs. It
currently imposes a high register pressure while trying to allocate
large VGPR tuples within the default register budget.
This patch changes the spilling strategy by picking the VGPRs in the
reverse order, the highest available VGPR first and later after regalloc
shift them back to the lowest available range. With that, the initial
VGPRs would be available for allocation and possibility
of finding large number of contiguous registers will be more.
Commit: 3dea0aa8f4607888d0c32cd7a691d8090b1b73c7
https://github.com/llvm/llvm-project/commit/3dea0aa8f4607888d0c32cd7a691d8090b1b73c7
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
Log Message:
-----------
[LSR] Fix incorrect comment. NFC (#79207)
Commit: ecde13b1a861696dec5c4ccae792abe25df07db9
https://github.com/llvm/llvm-project/commit/ecde13b1a861696dec5c4ccae792abe25df07db9
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
Log Message:
-----------
[gn build] port 7e50f006f7f6
Commit: f0c387038854d61a632520a4073d1b6ebf4997ed
https://github.com/llvm/llvm-project/commit/f0c387038854d61a632520a4073d1b6ebf4997ed
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M clang/lib/Lex/HeaderSearch.cpp
A clang/test/Modules/pr73023.cpp
Log Message:
-----------
[Modules] [HeaderSearch] Don't reenter headers if it is pragma once (#76119)
Close https://github.com/llvm/llvm-project/issues/73023
The direct issue of https://github.com/llvm/llvm-project/issues/73023 is
that we entered a header which is marked as pragma once since the
compiler think it is OK if there is controlling macro.
It doesn't make sense. I feel like it should be sufficient to skip it
after we see the '#pragma once'.
>From the context, it looks like the workaround is primarily for
ObjectiveC. So we might need reviewers from OC.
Commit: 7bda0ce15a2874ad74fb1a451a174084094ccc34
https://github.com/llvm/llvm-project/commit/7bda0ce15a2874ad74fb1a451a174084094ccc34
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-24 (Wed, 24 Jan 2024)
Changed paths:
M llvm/tools/llc/llc.cpp
Log Message:
-----------
[llc] Remove C backend support (#79237)
C backend is removed in 3.1.
Commit: 63f742c15f01a25c60f0090a3aceb15bb8985e5e
https://github.com/llvm/llvm-project/commit/63f742c15f01a25c60f0090a3aceb15bb8985e5e
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M clang/test/Driver/riscv-cpus.c
M clang/test/Misc/target-invalid-cpu-note.c
M llvm/docs/ReleaseNotes.rst
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add sifive-p670 processor (#79015)
This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.
Scheduler model and other tuning will come in separate patches.
Commit: a8d23defc0a1bed0385746119046cb8395a03c46
https://github.com/llvm/llvm-project/commit/a8d23defc0a1bed0385746119046cb8395a03c46
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-23 (Tue, 23 Jan 2024)
Changed paths:
M .github/workflows/libclang-python-tests.yml
M clang/lib/Lex/HeaderSearch.cpp
M clang/test/CodeGenCXX/new-array-init.cpp
M clang/test/Driver/riscv-cpus.c
M clang/test/Driver/unsupported-option-gpu.c
M clang/test/Misc/target-invalid-cpu-note.c
A clang/test/Modules/pr73023.cpp
M compiler-rt/lib/sanitizer_common/sanitizer_internal_defs.h
M compiler-rt/lib/tsan/rtl/tsan_dispatch_defs.h
R libc/src/threads/linux/call_once.cpp
R libc/src/threads/linux/thread_start_args.h.def
M libcxx/include/string
R libcxx/test/libcxx/containers/strings/basic.string/asan_deque_integration.pass.cpp
R libcxx/test/libcxx/containers/strings/basic.string/asan_short.pass.cpp
R libcxx/test/libcxx/containers/strings/basic.string/asan_vector_integration.pass.cpp
M libcxx/test/support/asan_testing.h
M lld/test/ELF/dead-reloc-in-nonalloc.s
M lldb/source/Core/ValueObject.cpp
M llvm/docs/ReleaseNotes.rst
A llvm/docs/RemoveDIsDebugInfo.md
M llvm/docs/UserGuides.rst
M llvm/include/llvm/BinaryFormat/ELFRelocs/RISCV.def
M llvm/include/llvm/CodeGen/AsmPrinter.h
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
M llvm/include/llvm/CodeGen/CommandFlags.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/include/llvm/IR/Function.h
M llvm/include/llvm/Target/CGPassBuilderOption.h
M llvm/include/llvm/Target/TargetMachine.h
M llvm/include/llvm/Target/TargetOptions.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
M llvm/lib/CodeGen/CommandFlags.cpp
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/IR/BasicBlock.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Instruction.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
M llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchFixupKinds.h
M llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h
M llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
M llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/TargetMachine.cpp
M llvm/lib/Target/X86/CMakeLists.txt
A llvm/lib/Target/X86/X86CodeGenPassBuilder.cpp
M llvm/lib/Target/X86/X86TargetMachine.h
M llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
M llvm/test/CodeGen/AMDGPU/bf16.ll
M llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
M llvm/test/CodeGen/AMDGPU/dwarf-multi-register-use-crash.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-argument-types.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-preserved-registers.ll
M llvm/test/CodeGen/AMDGPU/gfx-callable-return-types.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i32_system.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64_system.ll
M llvm/test/CodeGen/AMDGPU/identical-subrange-spill-infloop.ll
M llvm/test/CodeGen/AMDGPU/indirect-call.ll
M llvm/test/CodeGen/AMDGPU/insert-waitcnts-crash.ll
M llvm/test/CodeGen/AMDGPU/ipra.ll
M llvm/test/CodeGen/AMDGPU/mul24-pass-ordering.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir
M llvm/test/CodeGen/AMDGPU/sgpr-spills-split-regalloc.ll
M llvm/test/CodeGen/AMDGPU/sibling-call.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-csr-live-ins.mir
M llvm/test/CodeGen/AMDGPU/spill-sgpr-to-virtual-vgpr.mir
M llvm/test/CodeGen/AMDGPU/spill_more_than_wavesize_csr_sgprs.ll
M llvm/test/CodeGen/AMDGPU/stacksave_stackrestore.ll
M llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/unstructured-cfg-def-use-issue.ll
M llvm/test/CodeGen/AMDGPU/vgpr-large-tuple-alloc-error.ll
M llvm/test/CodeGen/AMDGPU/vgpr-tuple-allocation.ll
M llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
R llvm/test/CodeGen/Generic/bb-profile-dump.ll
M llvm/test/CodeGen/RISCV/tls-models.ll
M llvm/test/DebugInfo/salvage-limit-expr-size.ll
A llvm/test/MC/LoongArch/Relocations/align-non-executable.s
M llvm/test/MC/LoongArch/Relocations/relax-addsub.s
A llvm/test/MC/LoongArch/Relocations/relax-align.s
M llvm/test/MC/RISCV/relocations.s
A llvm/test/MC/RISCV/tlsdesc.s
M llvm/test/Transforms/SROA/vector-promotion.ll
M llvm/test/Transforms/Util/strip-nonlinetable-debuginfo-localvars.ll
A llvm/test/tools/llc/new-pm/lit.local.cfg
A llvm/test/tools/llc/new-pm/option-conflict.ll
A llvm/test/tools/llc/new-pm/pipeline.ll
A llvm/test/tools/llc/new-pm/start-stop.ll
M llvm/tools/llc/CMakeLists.txt
A llvm/tools/llc/NewPMDriver.cpp
A llvm/tools/llc/NewPMDriver.h
M llvm/tools/llc/llc.cpp
M llvm/unittests/CodeGen/CMakeLists.txt
R llvm/unittests/CodeGen/CodeGenPassBuilderTest.cpp
M llvm/utils/gn/secondary/llvm/lib/Target/X86/BUILD.gn
M llvm/utils/gn/secondary/llvm/tools/llc/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/CodeGen/BUILD.gn
M mlir/include/mlir/Conversion/ArithToAMDGPU/ArithToAMDGPU.h
M mlir/include/mlir/Conversion/Passes.td
M mlir/include/mlir/Dialect/Arith/Utils/Utils.h
M mlir/lib/Conversion/ArithToAMDGPU/ArithToAMDGPU.cpp
M mlir/lib/Conversion/ArithToAMDGPU/CMakeLists.txt
M mlir/lib/Dialect/Arith/Transforms/EmulateWideInt.cpp
M mlir/lib/Dialect/Arith/Utils/Utils.cpp
A mlir/test/Conversion/ArithToAMDGPU/8-bit-float-saturation.mlir
M mlir/test/Conversion/ArithToAMDGPU/8-bit-floats.mlir
M mlir/test/IR/print-attr-type-aliases.mlir
M mlir/test/Integration/Dialect/SparseTensor/CPU/sparse_block3d.mlir
M mlir/test/lib/Dialect/Test/TestAttrDefs.td
M mlir/test/lib/Dialect/Test/TestAttributes.cpp
Log Message:
-----------
simplify. use --offload-arch
Created using spr 1.3.4
Compare: https://github.com/llvm/llvm-project/compare/3a2b2a1110e7...a8d23defc0a1
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