[all-commits] [llvm/llvm-project] 63f742: [RISCV] Add sifive-p670 processor (#79015)

[Michael Maitland via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 63f742c15f01a25c60f0090a3aceb15bb8985e5e
      https://github.com/llvm/llvm-project/commit/63f742c15f01a25c60f0090a3aceb15bb8985e5e
  Author: Michael Maitland <michaeltmaitland at gmail.com>
  Date:   2024-01-23 (Tue, 23 Jan 2024)

  Changed paths:
    M clang/test/Driver/riscv-cpus.c
    M clang/test/Misc/target-invalid-cpu-note.c
    M llvm/docs/ReleaseNotes.rst
    M llvm/lib/Target/RISCV/RISCVProcessors.td

  Log Message:
  -----------
  [RISCV] Add sifive-p670 processor (#79015)

This is an OOO core that has a vector unit. For more information see
https://www.sifive.com/cores/performance-p650-670.

Scheduler model and other tuning will come in separate patches.