[all-commits] [llvm/llvm-project] 4318b0: [MC][X86] Merge lane/element broadcast comment pri...

Tue Jan 23 04:34:04 PST 2024

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4318b033bddc64d5654f3e368fddde859ff4d02e
      https://github.com/llvm/llvm-project/commit/4318b033bddc64d5654f3e368fddde859ff4d02e
  Author: Simon Pilgrim <RKSimon at users.noreply.github.com>
  Date:   2024-01-23 (Tue, 23 Jan 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86MCInstLower.cpp
    M llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
    M llvm/test/CodeGen/X86/2011-10-19-widen_vselect.ll
    M llvm/test/CodeGen/X86/addsub-constant-folding.ll
    M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast.ll
    M llvm/test/CodeGen/X86/any_extend_vector_inreg_of_broadcast_from_memory.ll
    M llvm/test/CodeGen/X86/avx2-fma-fneg-combine.ll
    M llvm/test/CodeGen/X86/avx2-vperm.ll
    M llvm/test/CodeGen/X86/avx512-shuffles/partial_permute.ll
    M llvm/test/CodeGen/X86/bitreverse.ll
    M llvm/test/CodeGen/X86/combine-sdiv.ll
    M llvm/test/CodeGen/X86/combine-subo.ll
    M llvm/test/CodeGen/X86/combine-udiv.ll
    M llvm/test/CodeGen/X86/fma-fneg-combine-2.ll
    M llvm/test/CodeGen/X86/fold-int-pow2-with-fmul-or-fdiv.ll
    M llvm/test/CodeGen/X86/fpclamptosat_vec.ll
    M llvm/test/CodeGen/X86/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll
    M llvm/test/CodeGen/X86/icmp-abs-C-vec.ll
    M llvm/test/CodeGen/X86/insert-into-constant-vector.ll
    M llvm/test/CodeGen/X86/masked_store_trunc.ll
    M llvm/test/CodeGen/X86/matrix-multiply.ll
    M llvm/test/CodeGen/X86/oddshuffles.ll
    M llvm/test/CodeGen/X86/omit-urem-of-power-of-two-or-zero-when-comparing-with-zero.ll
    M llvm/test/CodeGen/X86/peephole-fold-movsd.ll
    M llvm/test/CodeGen/X86/pr63108.ll
    M llvm/test/CodeGen/X86/psubus.ll
    M llvm/test/CodeGen/X86/sext-vsetcc.ll
    M llvm/test/CodeGen/X86/shrink_vmul.ll
    M llvm/test/CodeGen/X86/sink-addsub-of-const.ll
    M llvm/test/CodeGen/X86/slow-pmulld.ll
    M llvm/test/CodeGen/X86/srem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/sse2.ll
    M llvm/test/CodeGen/X86/urem-seteq-illegal-types.ll
    M llvm/test/CodeGen/X86/urem-seteq-vec-nonsplat.ll
    M llvm/test/CodeGen/X86/vec_fp_to_int.ll
    M llvm/test/CodeGen/X86/vector-blend.ll
    M llvm/test/CodeGen/X86/vector-fshl-512.ll
    M llvm/test/CodeGen/X86/vector-fshr-128.ll
    M llvm/test/CodeGen/X86/vector-fshr-512.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-2.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i16-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i32-stride-8.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i64-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-3.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-5.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-7.ll
    M llvm/test/CodeGen/X86/vector-interleaved-store-i8-stride-8.ll
    M llvm/test/CodeGen/X86/vector-mulfix-legalize.ll
    M llvm/test/CodeGen/X86/vector-partial-undef.ll
    M llvm/test/CodeGen/X86/vector-reduce-add-mask.ll
    M llvm/test/CodeGen/X86/vector-replicaton-i1-mask.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-512.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-sub128.ll
    M llvm/test/CodeGen/X86/vector-shuffle-128-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v32.ll
    M llvm/test/CodeGen/X86/vector-shuffle-256-v8.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v16.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v32.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v64.ll
    M llvm/test/CodeGen/X86/vector-shuffle-512-v8.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-avx2.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-sse41.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining-ssse3.ll
    M llvm/test/CodeGen/X86/vector-shuffle-combining.ll
    M llvm/test/CodeGen/X86/vector-shuffle-v1.ll
    M llvm/test/CodeGen/X86/vector-shuffle-v192.ll
    M llvm/test/CodeGen/X86/widen_arith-2.ll
    M llvm/test/CodeGen/X86/widen_arith-4.ll
    M llvm/test/CodeGen/X86/widen_arith-5.ll
    M llvm/test/CodeGen/X86/widen_arith-6.ll
    M llvm/test/CodeGen/X86/x86-interleaved-access.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast.ll
    M llvm/test/CodeGen/X86/zero_extend_vector_inreg_of_broadcast_from_memory.ll

  Log Message:
  -----------
  [MC][X86] Merge lane/element broadcast comment printers. (#79020)

This is /almost/ NFC - the only annoyance is that for some reason we were using "<C1,C2,..>" for ConstantVector types unlike all other cases - these now use the same "[C1,C2,..]" format as the other constant printers.