[all-commits] [llvm/llvm-project] a36961: Fix MSVC "result of 32-bit shift implicitly conver...

[Simon Pilgrim via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: a3696196949ad03de2db266eea257d28d1f35905
      https://github.com/llvm/llvm-project/commit/a3696196949ad03de2db266eea257d28d1f35905
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-01-23 (Tue, 23 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

  Log Message:
  -----------
  Fix MSVC "result of 32-bit shift implicitly converted to 64 bits" warning. NFC.


  Commit: 5c7bbe383bf2de0c1de36c7231bbd7f75bfccb1e
      https://github.com/llvm/llvm-project/commit/5c7bbe383bf2de0c1de36c7231bbd7f75bfccb1e
  Author: Simon Pilgrim <llvm-dev at redking.me.uk>
  Date:   2024-01-23 (Tue, 23 Jan 2024)

  Changed paths:
    M llvm/lib/Target/X86/X86ISelLowering.cpp
    M llvm/test/CodeGen/X86/i64-to-float.ll
    M llvm/test/CodeGen/X86/packus.ll
    M llvm/test/CodeGen/X86/sext-vsetcc.ll
    M llvm/test/CodeGen/X86/test-shrink-bug.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
    M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
    M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
    M llvm/test/CodeGen/X86/vector-shift-shl-256.ll

  Log Message:
  -----------
  [X86] canonicalizeShuffleWithOp - recognise constant vectors with getTargetConstantFromNode

Allows shuffle to fold constant vectors that have already been lowered to constant pool - shuffle combining can then constant fold this.

Noticed while triaging #79100


Compare: https://github.com/llvm/llvm-project/compare/3112578597c0...5c7bbe383bf2