[all-commits] [llvm/llvm-project] 4db4d7: [AMDGPU] SILowerSGPRSpills: do not update MRI rese...

[Carl Ritson via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 4db4d7f282d17634966cdfda8ccecee1bfcfe1ff
      https://github.com/llvm/llvm-project/commit/4db4d7f282d17634966cdfda8ccecee1bfcfe1ff
  Author: Carl Ritson <carl.ritson at amd.com>
  Date:   2024-01-23 (Tue, 23 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp
    M llvm/test/CodeGen/AMDGPU/sgpr-spill-overlap-wwm-reserve.mir

  Log Message:
  -----------
  [AMDGPU] SILowerSGPRSpills: do not update MRI reserve registers (#77888)

VGPRs used for spilling do not require explicit reservation with MRI.
freezeReservedRegs() executed before register allocation ensures these
are placed in the reserve set.

The only pass after SILowerSGPRSpills is SIPreAllocateWWMRegs which
explicitly tests for interference before register allocation so should
not reuse a WWM VGPR holding spill data. reserveReg prevents calculation
of correct liveness for physical registers which could be used to extend
SIPreAllocateWWMRegs.