[all-commits] [llvm/llvm-project] 66cea7: [RISCV] Add test case for #78783. NFC

[Craig Topper via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 66cea7143afd401f9d8c70966d21a6d19c65da9d
      https://github.com/llvm/llvm-project/commit/66cea7143afd401f9d8c70966d21a6d19c65da9d
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-19 (Fri, 19 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll

  Log Message:
  -----------
  [RISCV] Add test case for #78783. NFC


  Commit: 9396891271fd85b4f8922b16dd71e9433dc5fcb3
      https://github.com/llvm/llvm-project/commit/9396891271fd85b4f8922b16dd71e9433dc5fcb3
  Author: Craig Topper <craig.topper at sifive.com>
  Date:   2024-01-19 (Fri, 19 Jan 2024)

  Changed paths:
    M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
    M llvm/test/CodeGen/RISCV/riscv-codegenprepare.ll

  Log Message:
  -----------
  [RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.

We want to know the upper 33 bits of the And Input are zero. SExt
only guarantees they are the same.

We originally checked for SExt or ZExt when we were using
isImpliedByDomCondition because a ZExt may have been changed to SExt
before we visited the And.

We are no longer using isImpliedByDomCondition so we can only look
for zext with the nneg flag.

While here, switch to PatternMatch to simplify the code.

Fixes #78783


Compare: https://github.com/llvm/llvm-project/compare/39e024d9e2ec...9396891271fd