[all-commits] [llvm/llvm-project] c6dfb6: [flang] Support \u Unicode escape sequences (#76757)
Krzysztof Parzyszek via All-commits
all-commits at lists.llvm.org
Thu Jan 18 05:53:32 PST 2024
Branch: refs/heads/users/kparzysz/spr/a05-complete-createBodyOfOp
Home: https://github.com/llvm/llvm-project
Commit: c6dfb62d4df969fc50f42cf2889b10bb82f51b1f
https://github.com/llvm/llvm-project/commit/c6dfb62d4df969fc50f42cf2889b10bb82f51b1f
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/include/flang/Parser/characters.h
M flang/lib/Evaluate/character.h
M flang/lib/Parser/characters.cpp
M flang/runtime/edit-input.cpp
A flang/test/Semantics/modfile60.f90
Log Message:
-----------
[flang] Support \u Unicode escape sequences (#76757)
Support \uNNNN and \uNNNNNNNN escape sequences for CHARACTER(KIND=2) and
CHARACTER(KIND=4) literal constants for better GNU Fortran
compatibility.
Fixes llvm-test-suite/Fortran/gfortran/regression/achar_6.F90 and
.../widechar_1.f90.
Commit: 304119860ac0ded0a126ab1c8cc30367e29ebd01
https://github.com/llvm/llvm-project/commit/304119860ac0ded0a126ab1c8cc30367e29ebd01
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugInfo.h
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
Log Message:
-----------
[DebugInfo][RemoveDIs][NFC] Split findDbgDeclares into two functions (#77478)
This patch follows on from comments on
https://github.com/llvm/llvm-project/pull/73498, implementing the
proposed split of findDbgDeclares into two separate functions for
DbgDeclareInsts and DPVDeclares, which return containers rather than
taking containers by reference.
Commit: 2e08e821b7ea5bf7c0fe0775feb94a7fdb5204c7
https://github.com/llvm/llvm-project/commit/2e08e821b7ea5bf7c0fe0775feb94a7fdb5204c7
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/runtime/edit-input.cpp
Log Message:
-----------
[flang][runtime] Extension: allow a comma to terminate a fixed input … (#76768)
…field
When a comma appears in a fixed-width input field for integer editing,
many compilers accept it without error and interpret the comma as
terminating the field early.
Commit: 22c24be37c806e9295b05a34546b61a3164be267
https://github.com/llvm/llvm-project/commit/22c24be37c806e9295b05a34546b61a3164be267
Author: Tuan Chuong Goh <chuong.goh at arm.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
Log Message:
-----------
[AArch64][GlobalISel] Pre-commit for Combine vecreduce(ext) to {U/S}ADDLV
Commit: f08b55d1a62863f27df51921c1c87125e77a3298
https://github.com/llvm/llvm-project/commit/f08b55d1a62863f27df51921c1c87125e77a3298
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/runtime/namelist.cpp
M flang/unittests/Runtime/Namelist.cpp
Log Message:
-----------
[flang][runtime] Emit leading spaces in NAMELIST output (#76846)
As NAMELIST output is a variant of list-directed output, its editing
must produce leading spaces on (most) output records to effect carriage
control. These spaces are required by the language standard and
implemented by nearly all other Fortran compilers (except GNU).
Fixes https://github.com/llvm/llvm-project/issues/76798.
Commit: e2ce91f48cd606955ce125b009ccc6b5464cb05f
https://github.com/llvm/llvm-project/commit/e2ce91f48cd606955ce125b009ccc6b5464cb05f
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/test/CodeGen/SystemZ/regcoal_undefsrc.mir
Log Message:
-----------
Fix test output for 3b16d8c
Commit: e06b5a2435f2e4d422dfcf099ba5e4b9b2573fa9
https://github.com/llvm/llvm-project/commit/e06b5a2435f2e4d422dfcf099ba5e4b9b2573fa9
Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M clang/lib/Headers/llvm_libc_wrappers/string.h
M clang/test/Analysis/Inputs/system-header-simulator-for-simple-stream.h
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/bsd-string.c
M clang/test/Analysis/string.c
M libc/spec/bsd_ext.td
M libc/src/string/strsep.cpp
M libc/src/string/strsep.h
Log Message:
-----------
[libc] Give more functions restrict qualifiers (NFC) (#78061)
strsep, strtok_r, strlcpy, and strlcat take restricted pointers as
parameters.
Add the restrict qualifiers to them.
Sources:
https://man7.org/linux/man-pages/man3/strsep.3.html
https://man7.org/linux/man-pages/man3/strtok_r.3.html
https://man.freebsd.org/cgi/man.cgi?strlcpy
Commit: 3d6c6855c1f0b8570f280adb9a3dbb1f950b9115
https://github.com/llvm/llvm-project/commit/3d6c6855c1f0b8570f280adb9a3dbb1f950b9115
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/runtime/extrema.cpp
Log Message:
-----------
[flang][runtime] Fix total MAXLOC/MINLOC over CHARACTER data (#76880)
The implementation of MAXLOC/MINLOC without DIM=1 is wrong for CHARACTER
data -- change it to use the character comparator rather than the
numeric comparator.
Fixes llvm-test-suite/Fortran/gfortran/regression/maxloc_string_1.f90.
Commit: 85705bbf1dada62c7ee266bb3071e9c4ab4a4bfb
https://github.com/llvm/llvm-project/commit/85705bbf1dada62c7ee266bb3071e9c4ab4a4bfb
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
Log Message:
-----------
[AMDGPU] Disable hasVALUMaskWriteHazard for GFX12 (#78187)
Commit: ed60cb8fb98bf3cfede8c0912fe2845a4166370b
https://github.com/llvm/llvm-project/commit/ed60cb8fb98bf3cfede8c0912fe2845a4166370b
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/partial-forwarding-hazards.mir
Log Message:
-----------
[AMDGPU] Disable hasVALUPartialForwardingHazard for GFX12 (#78188)
Commit: ba131b7017ce99d56a0584e630ed542d8cd48488
https://github.com/llvm/llvm-project/commit/ba131b7017ce99d56a0584e630ed542d8cd48488
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
Log Message:
-----------
[AMDGPU] Do not generate s_set_inst_prefetch_distance for GFX12 (#78190)
GFX12 can still encode the s_set_inst_prefetch_distance instruction but
it has no effect.
Commit: 927b8a0f4f57a11b245da359b5076b16d969f75d
https://github.com/llvm/llvm-project/commit/927b8a0f4f57a11b245da359b5076b16d969f75d
Author: chuongg3 <chuong.goh at arm.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
Log Message:
-----------
[AArch64][GlobalISel] Combine vecreduce(ext) to {U/S}ADDLV (#75832)
Commit: 82e1e412e3249e15908c3f916eeaa04b96d4b453
https://github.com/llvm/llvm-project/commit/82e1e412e3249e15908c3f916eeaa04b96d4b453
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/lib/Evaluate/fold-character.cpp
M flang/lib/Evaluate/fold-integer.cpp
M flang/lib/Evaluate/fold-logical.cpp
M flang/lib/Evaluate/fold-real.cpp
M flang/lib/Evaluate/fold-reduction.h
M flang/runtime/extrema.cpp
M flang/runtime/reduction-templates.h
M flang/test/Evaluate/fold-findloc.f90
M flang/test/Evaluate/folding20.f90
Log Message:
-----------
[flang][runtime] Treatment of NaN in MAXVAL/MAXLOC/MINVAL/MINLOC (#76999)
Detect NaN elements in data and handle them like gfortran does (at
runtime); namely, NaN can be returned if all the data are NaNs, but any
non-NaN value is preferable. Ensure that folding returns the same
results as runtime computation.
Fixes llvm-test-suite/Fortran/gfortran/regression/maxloc_2.f90 (and
probably others).
Commit: 1d1893097a6319a6402331a54a588b1a5d961808
https://github.com/llvm/llvm-project/commit/1d1893097a6319a6402331a54a588b1a5d961808
Author: Jonas Paulsson <paulson1 at linux.ibm.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZPatterns.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
M llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
M llvm/test/CodeGen/SystemZ/fp-cmp-04.ll
R llvm/test/CodeGen/SystemZ/fp-cmp-07.mir
A llvm/test/CodeGen/SystemZ/fp-cmp-zero.ll
M llvm/test/CodeGen/SystemZ/fp-strict-cmp-04.ll
M llvm/test/CodeGen/SystemZ/tdc-06.ll
M llvm/test/CodeGen/SystemZ/vec-max-05.ll
M llvm/test/CodeGen/SystemZ/vec-min-05.ll
Log Message:
-----------
[SystemZ] Don't use FP Load and Test as comparisons to same reg (#78074)
The usage of FP Load and Test instructions as a comparison against zero
with the assumption that the dest reg will always reflect the source reg is
actually incorrect: Unfortunately, a SNaN will be converted to a QNaN, so the
instruction may actually change the value as opposed to being a pure register
move with a test.
This patch
- changes instruction selection to always emit FP LT with a scratch def
reg, which will typically be allocated to the same reg if dead.
- Removes the conversions into FP LT in SystemZElimcompare.
Commit: add189cdf01e92ca30687291a98e936b7706ee38
https://github.com/llvm/llvm-project/commit/add189cdf01e92ca30687291a98e936b7706ee38
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/runtime/edit-input.cpp
Log Message:
-----------
[flang][runtime] Resume rounding hexadecimal floating-point input (#77006)
This reverts commit cab156c4129e5948a6322054480e66d3ca17b919, and adds
language to Extensions.md documenting the discrepancy with the letter of
the language standard.
Commit: c0944f52c17a30762b81446183967ce3ef6b9aed
https://github.com/llvm/llvm-project/commit/c0944f52c17a30762b81446183967ce3ef6b9aed
Author: Eleanor Bonnici <eleanor.bonnici at arm.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
M llvm/test/MC/ARM/pcrel-global.s
M llvm/test/MC/ARM/pcrel-ldr-relocs.s
A llvm/test/MC/ARM/pcrel-ldrd-diff-section.s
A llvm/test/MC/ARM/pcrel-ldrd-same-section.s
A llvm/test/MC/ARM/pcrel-vldr-diff-section.s
A llvm/test/MC/ARM/pcrel-vldr-same-section.s
Log Message:
-----------
[llvm][MC][ARM] Don't autoresolve fixups (#76574)
Removes logic that caused some fixups to be marked as resolved in the
assembler without actually resolving them. Assembler must either resolve
the fixup, reject the code (error out) or defer the resolution to the
linker. In general assembler can resolve offsets in pcrel instructions
if the symbol referred to is in the same section and it cannot make
assumptions about relative position of sections. For example, when LDRD
instruction in arm mode is encountered, fixup_arm_pcrel_10_unscaled is
raised. Prior to https://github.com/llvm/llvm-project/pull/72873/ the
assembler would always mark it as resolved without generating a
relocation. The resulting code would likely be incorrect whenever the
label referred to is in a different section.
This patch finishes the series to prevent incorrect code being generated
for pcrel instructions referring to labels in different sections. This
kind of assembly code is very rare and most likely a user error, so both
options (relocation or error) are acceptable. In previous patches this
was resolved by adding relocations. Here, for VLDR instructions an error
is generated as relocation does not exist for Thumb mode and we wanted
the tool's behaviour to be consistent across modes. In the LDRD case,
Thumb mode does not have a relocation and errors out, but LDRD in Arm
mode generates R_ARM_LDRS_PC_G0 relocation because its fixup kind is
shared with other instructions.
It also fixed the case when ADR is used in the big-endian mode, which is
not covered by the ADR patch.
Patch series:
https://github.com/llvm/llvm-project/pull/72873 - LDRx
https://github.com/llvm/llvm-project/pull/73834 - ADR
this PR - LDRD and VLDR
Commit: 90828d67ea35c86b76fc8f3dec5da03f645eadaf
https://github.com/llvm/llvm-project/commit/90828d67ea35c86b76fc8f3dec5da03f645eadaf
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/include/flang/Common/Fortran-features.h
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/dosemantics12.f90
M flang/test/Semantics/forall01.f90
M flang/test/Semantics/resolve35.f90
M flang/test/Semantics/resolve99.f90
M flang/test/Semantics/symbol09.f90
Log Message:
-----------
[flang] Weird restrictions on index variables (#77019)
There are some very odd (even for Fortran) rules in F'2023 subclause
19.4 (paras 6 & 8) pertaining to the index variables of FORALL and DO
CONCURRENT constructs/statements, and they are not currently implemented
correctly.
Although these index variables are construct entities, they have
restrictions in the standard that would essentially allow them to also
be variables in their enclosing scopes. If their names are present in
the enclosing scope, and the construct does not have an explicit type
specification for its indices, then the names in the enclosing scope
must either be scalar variables or COMMON blocks, and their type must be
integer.
Reimplement these restrictions largely with portability warnings rather
than hard errors. Retain the semantic interpretation that the type of an
untyped index variable be taken from the type of a variable of the same
name in the enclosing scope, if it exists, although that bit of the
standard could be interpreted otherwise.
Fixes https://github.com/llvm/llvm-project/issues/76978.
Commit: 6719a5a3f6744efdb31095933e272163b294c8f7
https://github.com/llvm/llvm-project/commit/6719a5a3f6744efdb31095933e272163b294c8f7
Author: David Green <david.green at arm.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll
Log Message:
-----------
[ARM] Extra test for MVE gather optimization with commuted phi operands. NFC
Commit: d0708e6285b88510649722fe8e6832ee1d7abfb1
https://github.com/llvm/llvm-project/commit/d0708e6285b88510649722fe8e6832ee1d7abfb1
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/lib/Semantics/mod-file.cpp
A flang/test/Semantics/modfile61.f90
Log Message:
-----------
[flang] Refine IMPORT processing in module file generation (#77133)
Procedure interfaces emitted to module files are including IMPORT
statements for some symbols that don't need to be imported (base types
and procedure interfaces for components of imported derived types) and
omitting others (procedure interfaces for bindings in locally-defined
derived types that are material to the interface).
Commit: f0896911570eae97507f9e3ccf2732182404981e
https://github.com/llvm/llvm-project/commit/f0896911570eae97507f9e3ccf2732182404981e
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/include/flang/Evaluate/real.h
M flang/lib/Evaluate/real.cpp
M flang/runtime/numeric.cpp
M flang/test/Evaluate/fold-mod.f90
Log Message:
-----------
[flang][runtime] Better real MOD/MODULO results (#77167)
The Fortran standard defines real MOD and MODULO with expressions like
MOD(a,p) = a - AINT(a/p)*p. Unfortunately, these definitions have poor
accuracy when a is much larger in magnitude than p, and every Fortran
compiler uses better algorithms instead.
Fixes llvm-test-suite/Fortran/gfortran/regression/mod_large_1.f90.
Commit: f9b089a7c01dd3fe7de3d397520172ec3b8fb9f1
https://github.com/llvm/llvm-project/commit/f9b089a7c01dd3fe7de3d397520172ec3b8fb9f1
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/lib/Evaluate/intrinsics.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Semantics/check-call.cpp
M flang/test/Semantics/move_alloc.f90
Log Message:
-----------
[flang] Fix semantic checks for MOVE_ALLOC (#77362)
The checking of calls to the intrinsic subroutine MOVE_ALLOC is not
insisting that its first two arguments be whole allocatable variables or
components. Fix, move the code into check-calls.cpp (a better home for
such things), and clean up the tests.
Fixes https://github.com/llvm/llvm-project/issues/77230.
Commit: 73863a48352c48b0c37a49c5dcfa521eb0cfcb5b
https://github.com/llvm/llvm-project/commit/73863a48352c48b0c37a49c5dcfa521eb0cfcb5b
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
A llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
Log Message:
-----------
[InstCombine] Add tests for folding `(add/sub/disjoint_or/icmp C, (ctpop (not x)))`; NFC
Commit: 60e8915d2277ab784f4d27139c479868255b22bf
https://github.com/llvm/llvm-project/commit/60e8915d2277ab784f4d27139c479868255b22bf
Author: Noah Goldstein <goldstein.w.n at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll
Log Message:
-----------
[InstCombine] Add folds for `(add/sub/disjoint_or/icmp C, (ctpop (not x)))`
`(ctpop (not x))` <-> `(sub nuw nsw BitWidth(x), (ctpop x))`. The
`sub` expression can sometimes be constant folded depending on the use
case of `(ctpop (not x))`.
This patch adds fold for the following cases:
`(add/sub/disjoint_or C, (ctpop (not x))`
-> `(add/sub/disjoint_or C', (ctpop x))`
`(cmp pred C, (ctpop (not x))`
-> `(cmp swapped_pred C', (ctpop x))`
Where `C'` depends on how we constant fold `C` with `BitWidth(x)` for
the given opcode.
Proofs: https://alive2.llvm.org/ce/z/qUgfF3
Closes #77859
Commit: 7b8012338745ab16a88d78b3772d21dd6f87224b
https://github.com/llvm/llvm-project/commit/7b8012338745ab16a88d78b3772d21dd6f87224b
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/include/flang/Evaluate/tools.h
M flang/include/flang/Semantics/symbol.h
M flang/include/flang/Semantics/tools.h
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Evaluate/shape.cpp
M flang/lib/Evaluate/tools.cpp
M flang/lib/Evaluate/type.cpp
M flang/lib/Semantics/check-declarations.cpp
M flang/lib/Semantics/check-namelist.cpp
Log Message:
-----------
[flang] More support for assumed-size Cray pointees (#77381)
Recognize Cray pointees as such when they are declared as assumed size
arrays, and don't emit a bogus error message about implied shape arrays.
Fixes https://github.com/llvm/llvm-project/issues/77330.
Commit: 9fdd25e18c04f3543f7de9727f11f034498ca07e
https://github.com/llvm/llvm-project/commit/9fdd25e18c04f3543f7de9727f11f034498ca07e
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/runtime/allocatable.cpp
Log Message:
-----------
[flang] Don't change size of allocatable in error situation (#77386)
When an already-allocated allocatable array is about to fail
reallocation, don't allow its size or other characteristics to be
changed.
Fixes
llvm-test-suite/Fortran/gfortran/regression/multiple_allocation_1.f90
and .../multiple_allocation_3.f90.
Commit: f3524e9aebbfabed0c60d0087b39ce14d8f778da
https://github.com/llvm/llvm-project/commit/f3524e9aebbfabed0c60d0087b39ce14d8f778da
Author: Diogo Teles Sant'Anna <diogoteles at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
A .github/dependabot.yml
M .github/workflows/release-binaries.yml
M .github/workflows/release-tasks.yml
A llvm/docs/requirements-hashed.txt
Log Message:
-----------
Hashpin sensitive dependencies and configure dependabot to update them automatically (#75859)
Closes #75620
As I mentioned on the issue, this PR aims to hash-pin the CI
dependencies used on sensitive context -- i.e., they either are called
with write permissions, or are being used to build critical artifacts
like a release. In summary, this PR brings 3 changes:
1. Hash pin GitHub Actions called on sensitive context
2. Hash pin python dependencies used on sensitive context
3. Configure dependabot to automatically update those hashes
I'm further explaining the steps bellow.
The dependencies in format of GitHub Actions, I simply hash-pinned them.
I also made sure to keep the human-readable version as comments at the
same line.
At the
[release-tasks.yml](https://github.com/llvm/llvm-project/blob/main/.github/workflows/release-tasks.yml)
file, I've changed the installation method of some python dependencies
to install them considering their hashpinning. That required the
generation of a requirements file that had all the correct hashes, and
for that I used [pip-tools](https://pypi.org/project/pip-tools/2.0.0/).
While configuring dependabot, I set it to send a monthly PR updating all
the GitHub Actions, and a weekly PR to update any python dependency
required by
[/llvm/docs/requirements.txt](https://github.com/llvm/llvm-project/blob/main/llvm/docs/requirements.txt).
Let me know if you have any questions or concerns, I'd be happy to
clarify and help.
Thanks!
---------
Signed-off-by: Diogo Teles Sant'Anna <diogoteles at google.com>
Commit: 691770ca67986d9450ac2b22335cc9c01c6c27e4
https://github.com/llvm/llvm-project/commit/691770ca67986d9450ac2b22335cc9c01c6c27e4
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
M flang/lib/Semantics/check-declarations.cpp
M flang/test/Semantics/call14.f90
Log Message:
-----------
[flang] Add portability warning for F'2008 feature (#77526)
Using the VALUE attribute for assumed-length CHARACTER dummy arguments
became standard in F'2008 but still lacks widespread implementation;
emit a portability warning when they are enabled.
Resolves llvm-test-suite/Fortran/gfortran/regression/value_5.f90.
Commit: 6e0a2031f09819425480df8d44122530275b2347
https://github.com/llvm/llvm-project/commit/6e0a2031f09819425480df8d44122530275b2347
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/include/flang/Evaluate/characteristics.h
M flang/lib/Evaluate/characteristics.cpp
M flang/lib/Semantics/expression.cpp
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/call24.f90
M flang/test/Semantics/call25.f90
M flang/test/Semantics/local-vs-global.f90
M flang/test/Semantics/reshape.f90
M flang/test/Semantics/resolve09.f90
Log Message:
-----------
[flang] Catch name resolution error due to global scoping (#77683)
In
CALL FOO
PRINT *, ABS(FOO)
we currently resolve the first FOO to a global external subprogram, but
then the second FOO is treated as an implicitly typed local variable.
This happens because the name FOO is not present in the local scope.
Fix by adding FOO to the local scope using a place-holding
HostAssocDetails symbol whose existence prevents the creation of another
FOO in the local scope. The symbol stored in the parser::Name parse tree
nodes or used in typed expressions will all continue to point to the
global external subprogram.
Resolves llvm-test-suite/Fortran/gfortran/regression/pr71859.f90.
Commit: 4fcefbd3a41d77b2471c78c5b2e50d058ee46b97
https://github.com/llvm/llvm-project/commit/4fcefbd3a41d77b2471c78c5b2e50d058ee46b97
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/runtime/io-stmt.cpp
Log Message:
-----------
[flang][runtime] Emit leading space before zero-length list-directed … (#77835)
…character
Don't omit the leading space in list-directed output before a line
comprising only a zero-length character value.
Fixes https://github.com/llvm/llvm-project/issues/77736.
Commit: 92126ca62e5764f9267524c18f78fe0b8c5751c0
https://github.com/llvm/llvm-project/commit/92126ca62e5764f9267524c18f78fe0b8c5751c0
Author: Martin Storsjö <martin at martin.st>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M lld/COFF/Driver.cpp
M lld/test/COFF/print-search-paths.s
Log Message:
-----------
[LLD] [COFF] Prefer paths specified with -libpath: over toolchain paths (#78039)
The main reason for adding the toolchain paths early was to prefer
libraries from the toolchain over ones from MSVC (primarily for
compiler-rt builtins). But if the user specifies a directory explicitly
with the -libpath: option, that should be preferred over the built-in
default paths.
This fixes an issue raised at
https://discourse.llvm.org/t/lld-prefers-system-llvm-libraries-to-user-provided-ones-on-windows/76148.
Commit: 837503023a196fef76abe66102a89ca4dedee039
https://github.com/llvm/llvm-project/commit/837503023a196fef76abe66102a89ca4dedee039
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M compiler-rt/cmake/Modules/AddCompilerRT.cmake
M compiler-rt/lib/sanitizer_common/symbolizer/scripts/build_symbolizer.sh
Log Message:
-----------
[sanitizer] Fix builds after #77991
Commit: c66645da55b9f4c13f4a612392dcc5a84b086ba7
https://github.com/llvm/llvm-project/commit/c66645da55b9f4c13f4a612392dcc5a84b086ba7
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/lib/Semantics/resolve-names.cpp
M flang/test/Semantics/init01.f90
M flang/test/Semantics/pointer01.f90
Log Message:
-----------
[flang] Catch more initialization errors (#77850)
[flang] Catch more initialization errors
Diagnose some error cases related to initialization that are
slipping past semantic checking: don't allow multiple initializations
of the same symbol, and don't allow an object that was initialized
as a scalar to become an array afterward.
Fixes llvm-test-suite/Fortran/gfortran/regression/initialization_17.f90.
Commit: 2bb2a42fa261d728e32ba0b1f9cf27ba7991440f
https://github.com/llvm/llvm-project/commit/2bb2a42fa261d728e32ba0b1f9cf27ba7991440f
Author: Michael Buch <michaelbuch12 at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M lldb/include/lldb/Core/ValueObject.h
M lldb/source/Core/ValueObject.cpp
Log Message:
-----------
[lldb][ValueObject][NFC] Further remove redundant parameters to ReadPointedString (#78029)
We only ever call this function once, without relying on the defaulted
`honor_array` parameter, so make it non-defaulted. Also `max_length` is
always set to `0`, so remove it entirely.
This simplifies some upcoming refactoring.
Commit: 8f3bdea9b4083a7b9a7a4fb79d2d918575d42d57
https://github.com/llvm/llvm-project/commit/8f3bdea9b4083a7b9a7a4fb79d2d918575d42d57
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/docs/Extensions.md
Log Message:
-----------
[flang][NFC] Restore documentation (#78211)
Add a paragraph to Extensions.md that fell out of a recent patch.
Commit: 9fa9d9a7e1cd0a7fd8c35bdfc642793447bf70aa
https://github.com/llvm/llvm-project/commit/9fa9d9a7e1cd0a7fd8c35bdfc642793447bf70aa
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M clang/test/Driver/linker-wrapper-image.c
M clang/tools/clang-linker-wrapper/CMakeLists.txt
M clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp
R clang/tools/clang-linker-wrapper/OffloadWrapper.cpp
R clang/tools/clang-linker-wrapper/OffloadWrapper.h
A llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/lib/Frontend/Offloading/CMakeLists.txt
A llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
Log Message:
-----------
[llvm][frontend][offloading] Move clang-linker-wrapper/OffloadWrapper.* to llvm/Frontend/Offloading (#78057)
This patch moves `clang/tools/clang-linker-wrapper/OffloadWrapper.*` to
`llvm/Frontend/Offloading` allowing them to be re-utilized by other
projects.
Additionally, it makes minor modifications to the API to make it more
flexible.
Concretely:
- The `wrap*` methods now have additional arguments `EntryArray`,
`Suffix` and `EmitSurfacesAndTextures` to specify some additional options.
- The `EntryArray` is now constructed by the caller. This change is needed to
enable JIT compilation, as ORC doesn't fully support `__start_` and `__stop_`
symbols. Thus, to JIT the code, the `EntryArray` has to be constructed explicitly in the IR.
- The `Suffix` field is used when emitting the descriptor, registration
methods, etc, to make them more readable. It is empty by default.
- The `EmitSurfacesAndTextures` field controls whether to emit surface
and texture registration code, as those functions were removed from `CUDART`
in CUDA 12. It is true by default.
- The function `getOffloadingEntryInitializer` was added to help create
the `EntryArray`, as it returns the constant initializer and not a global
variable.
Commit: ab33c0b96e26430b22e152cb6ecbab54dd2cfa41
https://github.com/llvm/llvm-project/commit/ab33c0b96e26430b22e152cb6ecbab54dd2cfa41
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
A llvm/test/Transforms/LoopStrengthReduce/rewrite-to-add-neg-1-expansion-flags.ll
Log Message:
-----------
[LSR] Add test showing incorrectly adding nuw with #77827.
Extra test for https://github.com/llvm/llvm-project/pull/77827, where
NUW gets added the AddRec due to the BTC being 0.
Commit: 8b6b882f27e86bae717ffcbaef6da3f00af86003
https://github.com/llvm/llvm-project/commit/8b6b882f27e86bae717ffcbaef6da3f00af86003
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M flang/runtime/extensions.cpp
M flang/unittests/Runtime/CommandTest.cpp
Log Message:
-----------
[flang] allow _POSIX_SOURCE to be defined without a value (#78179)
The `_POSIX_SOURCE` macro is defined without a value on AIX. Change the check to `defined(_POSIX_SOURCE)`.
Commit: 5b4f2b906ba697c276b3e0940c24ae640cfde695
https://github.com/llvm/llvm-project/commit/5b4f2b906ba697c276b3e0940c24ae640cfde695
Author: Fabian Mora <fmora.dev at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/IR/GPUOps.td
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp
M mlir/test/Dialect/GPU/invalid.mlir
M mlir/test/Dialect/GPU/module-to-binary-nvvm.mlir
M mlir/test/Dialect/GPU/ops.mlir
Log Message:
-----------
[mlir][gpu] Add an offloading handler attribute to `gpu.module` (#78047)
This patch adds an optional offloading handler attribute to
the`gpu.module` op. This attribute will be used during
`gpu-module-to-binary` pass to override the offloading handler used in
the `gpu.binary` op.
Commit: 071207ea415d73844f6d48be3b83a7e010e3759b
https://github.com/llvm/llvm-project/commit/071207ea415d73844f6d48be3b83a7e010e3759b
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Mesh/IR/MeshOps.cpp
Log Message:
-----------
[mlir] Fix -Wsign-compare in MeshOps.cpp (NFC)
llvm-project/mlir/lib/Dialect/Mesh/IR/MeshOps.cpp:204:25:
error: comparison of integers of different signs: 'size_t' (aka 'unsigned long') and 'int64_t' (aka 'long') [-Werror,-Wsign-compare]
if (getShape().size() > rank)
~~~~~~~~~~~~~~~~~ ^ ~~~~
1 error generated.
Commit: 10602c2b4a662872d1aaeda1dbc58e5d6f613fda
https://github.com/llvm/llvm-project/commit/10602c2b4a662872d1aaeda1dbc58e5d6f613fda
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang-tools-extra/clang-tidy/readability/AvoidNestedConditionalOperatorCheck.cpp
Log Message:
-----------
[NFC]add - at the beginning for alignment
Commit: c58bc24fcf678c55b0bf522be89eff070507a005
https://github.com/llvm/llvm-project/commit/c58bc24fcf678c55b0bf522be89eff070507a005
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Sema/SemaOverload.cpp
M clang/test/CXX/over/over.load/p2-0x.cpp
A clang/test/Modules/GH77953.cpp
Log Message:
-----------
[Clang] Only compare template params of potential overload after checking their decl context (#78139)
Fixes a regression from 69066ab3 in which we compared the template lists
of potential overloads before checkings their declaration contexts.
This would cause a crash when doing constraint substitution as part of
that template check, because we would try to refer to not yet
instantiated entities (the underlying cause is unclear).
This patch reorders (again) when we look at template parameter so we
don't do it when checkings friends in different lexical contexts.
Fixes #77953
Fixes #78101
Commit: 89cdd48a22cb7aca1695746b70428ac910396d3e
https://github.com/llvm/llvm-project/commit/89cdd48a22cb7aca1695746b70428ac910396d3e
Author: Joseph Huber <huberjn at outlook.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M openmp/libomptarget/plugins-nextgen/amdgpu/src/rtl.cpp
Log Message:
-----------
[Libomptarget] Remove temporary files in AMDGPU JIT impl (#77980)
Summary:
This patch cleans up some of the JIT handling for AMDGPU as well as
removing its temporary files. Previously these would be left in the
temporary directory after the program was run. This costs some extra
time, but the correct solution to avoid that is to create a sufficient
entrypoint into `ld.lld` that we can simply pass a memory buffer into.
Commit: 2c0fc0f37f29d54e0376a5e1f7cbb386a37a177d
https://github.com/llvm/llvm-project/commit/2c0fc0f37f29d54e0376a5e1f7cbb386a37a177d
Author: XChy <xxs_chy at outlook.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
Log Message:
-----------
[DFAJumpThreading] Handle circular determinator (#78177)
Fixes the buildbot failure in
https://github.com/llvm/llvm-project/pull/78134#issuecomment-1892195197
When we meet the path with single `determinator`, the determinator
actually takes itself as a predecessor. Thus, we need to let `Prev` be
the determinator when `PathBBs` has only one element.
Commit: 58b33d0301a36900fc641b4b0e110b683064bab8
https://github.com/llvm/llvm-project/commit/58b33d0301a36900fc641b4b0e110b683064bab8
Author: SihangZhu <zhusihang at huawei.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libunwind/src/libunwind.cpp
Log Message:
-----------
[libunwind] fix dynamic .eh_frame registration (#77185)
Fix this issue
[#76957](https://github.com/llvm/llvm-project/issues/76957)
Libgcc provides __register_frame to register a dynamic .eh_frame
section, while __unw_add_dynamic_eh_frame_section can be used to do the
same in libunwind. However, the address after dynamic .eh_frame are
padding with 0 value, it will be identified as
legal CIE. And __unw_add_dynamic_eh_frame_section will continue to parse
subsequent addresses until illegal memory or other sections are
accessed.
This patch adds length formal parameter for dynamic registration.
Commit: eb009ed2495d495e0c9bb10c29c484d563bb5cdf
https://github.com/llvm/llvm-project/commit/eb009ed2495d495e0c9bb10c29c484d563bb5cdf
Author: Amara Emerson <amara at apple.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
Log Message:
-----------
[GlobalISel] Fix the select->minmax combine from trying to operate on pointer types.
Commit: a511c1a9eccf93d3c4cbf724864fbc0b86c517f4
https://github.com/llvm/llvm-project/commit/a511c1a9eccf93d3c4cbf724864fbc0b86c517f4
Author: Rashmi Mudduluru <r_mudduluru at apple.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/TypoCorrection.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
R clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/bounds-checking.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
R clang/test/Sema/attr-counted-by.c
Log Message:
-----------
Revert "[Clang] Implement the 'counted_by' attribute (#76348)"
This reverts commit 164f85db876e61cf4a3c34493ed11e8f5820f968.
Commit: eca2529592b59fe2c4b2e06adf15900c7a2ca95f
https://github.com/llvm/llvm-project/commit/eca2529592b59fe2c4b2e06adf15900c7a2ca95f
Author: AtariDreams <83477269+AtariDreams at users.noreply.github.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/include/llvm/Support/MathExtras.h
Log Message:
-----------
Use Log2_64_Ceil to compute PowerOf2Ceil (#67580)
Instead of calling NextPowerOf2, which is only useful for constants,
we should call Log2_64_Ceil, which is faster because it uses compiler
intrinsics where supported.
Commit: 855e863004966e8856c0ab518c08079a1d192df2
https://github.com/llvm/llvm-project/commit/855e863004966e8856c0ab518c08079a1d192df2
Author: Nicholas Mosier <nmosier at stanford.edu>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
Log Message:
-----------
[X86] Add MI-layer routine for getting the index of the first address operand, NFC (#78019)
Add the MI-layer routine X86::getFirstAddrOperandIdx(), which returns
the index of the first address operand of a MachineInstr (or -1 if there
is none).
X86II::getMemoryOperandNo(), the existing MC-layer routine used to
obtain the index of the first address operand in a 5-operand X86 memory
reference, is incomplete: it does not handle pseudo-instructions like
TCRETURNmi, resulting in security holes in the mitigation passes that
use it (e.g., x86-slh and x86-lvi-load).
X86::getFirstAddrOperandIdx() handles both pseudo and real instructions
and is thus more suitable for most use cases than
X86II::getMemoryOperandNo(), especially in mitigation passes like
x86-slh and x86-lvi-load. For this reason, this patch replaces all uses
of X86II::getMemoryOperandNo() with X86::getFirstAddrOperandIdx() in the
aforementioned mitigation passes.
Commit: b6e8f6604c1ca79e01d3db816c16101ae2834f60
https://github.com/llvm/llvm-project/commit/b6e8f6604c1ca79e01d3db816c16101ae2834f60
Author: Mel Chen <mel.chen at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
A llvm/test/Transforms/LoopVectorize/dbg-outer-loop-vect.ll
Log Message:
-----------
[LV] Skipping all debug instructions when native vplan is enabled (#77413)
The following internal error occurred when using native vplan to
vectorize the program with the debug info generation.
Assertion `!isa<DbgInfoIntrinsic>(CI) && "DbgInfoIntrinsic should have been dropped during VPlan construction"' failed.
This patch ignored all debug instructions to fix the error when native
vplan is enabled.
Commit: 3d68217454fe600c492314f458df36f9e26ce475
https://github.com/llvm/llvm-project/commit/3d68217454fe600c492314f458df36f9e26ce475
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/lib/Target/X86/X86InstrUtils.td
Log Message:
-----------
[X86][NFC] Simplify the definitions of rotate instructions
Commit: 1b6c1a3bd73be4dd904230c637d65810cf3334cd
https://github.com/llvm/llvm-project/commit/1b6c1a3bd73be4dd904230c637d65810cf3334cd
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/test/Modules/GH77953.cpp
Log Message:
-----------
[NFC] Improve test for clang/test/Modules/GH77953.cpp
Generally we'll use `-fsyntax-only` when it is sufficient and we'll use
`expected-no-diagnostics` to test the behavior doesn't trigger any
problems. This patch applies these two improvements to
`clang/test/Modules/GH77953.cpp`.
Commit: 59e5cb7b83fbbce2423e0c024861f83c0390670f
https://github.com/llvm/llvm-project/commit/59e5cb7b83fbbce2423e0c024861f83c0390670f
Author: Michal Paszkowski <michal at paszkowski.org>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/test/CodeGen/SPIRV/logical-struct-access.ll
A llvm/test/CodeGen/SPIRV/pointers/getelementptr-bitcast-load.ll
Log Message:
-----------
[SPIR-V] Do not emit spv_ptrcast if GEP result is of expected type (#78122)
Prior to this change spv_ptrcast (and OpBitcast) was never emitted for
GEP resulting pointers. While such SPIR-V was (mostly) accepted by the
NEO GPU driver, the generated SPIR-V was incorrect.
The newly added test (pointers/getelementptr-bitcast-load.ll) verifies
that a correct bitcast is added for more complex cases and passes
spirv-val. The test is based on an OpenCL CTS test (basic/prefetch).
Commit: d338d15243d221198ec35fbe97525ca3b1de1470
https://github.com/llvm/llvm-project/commit/d338d15243d221198ec35fbe97525ca3b1de1470
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
Log Message:
-----------
[X86] Fix -Wunused-variable in X86InstrInfo.cpp (NFC)
llvm-project/llvm/lib/Target/X86/X86InstrInfo.cpp:3467:14:
error: unused variable 'isMemOp' [-Werror,-Wunused-variable]
3467 | const auto isMemOp = [](const MCOperandInfo &OpInfo) -> bool {
| ^~~~~~~
1 error generated.
Commit: d63c2e52e6e2f904e61562a8ebc48faa7195a2de
https://github.com/llvm/llvm-project/commit/d63c2e52e6e2f904e61562a8ebc48faa7195a2de
Author: Shilei Tian <i at tianshilei.me>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/fdot2.ll
M llvm/test/CodeGen/AMDGPU/idot2.ll
M llvm/test/CodeGen/AMDGPU/idot4s.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.sdot4.ll
M llvm/test/MC/Disassembler/AMDGPU/gfx1011-xdl-insts.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx1011_dlops.txt
Log Message:
-----------
[AMDGPU][MC] Remove incorrect `_e32` suffix from `v_dot2c_f32_f16` and `v_dot4c_i32_i8` (#77993)
The two VOP2 instructions cannot be encoded as VOP3.
Fix #54691.
Commit: 43414e736cd122032c07d60ca990655733e52a89
https://github.com/llvm/llvm-project/commit/43414e736cd122032c07d60ca990655733e52a89
Author: XChy <xxs_chy at outlook.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/test/Transforms/DFAJumpThreading/dfa-jump-threading-transform.ll
Log Message:
-----------
[DFAJumpThreading][NFC] Reduce tests
Commit: f6ff7574a6fc979583b8105f0d3f2fac165b6d61
https://github.com/llvm/llvm-project/commit/f6ff7574a6fc979583b8105f0d3f2fac165b6d61
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/include/mlir/IR/Attributes.h
M mlir/lib/IR/AsmPrinter.cpp
M mlir/unittests/IR/AttributeTest.cpp
Log Message:
-----------
[mlir] Attribute add printStripped (#78008)
Enable printing without dialect wrapping.
This closely matches `AsmPrinter::printStrippedAttrOrType`
implementation wise except templating component.
Commit: b984045d4fbd061c6ddb25beeff9797f78b26e27
https://github.com/llvm/llvm-project/commit/b984045d4fbd061c6ddb25beeff9797f78b26e27
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/lib/Conversion/VectorToGPU/VectorToGPU.cpp
Log Message:
-----------
Apply clang-tidy fixes for readability-simplify-boolean-expr in VectorToGPU.cpp (NFC)
Commit: 39c0ebd5584f0649d36eb2d3f0bc0363c9e40a86
https://github.com/llvm/llvm-project/commit/39c0ebd5584f0649d36eb2d3f0bc0363c9e40a86
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/lib/Debug/CLOptionsSetup.cpp
Log Message:
-----------
Apply clang-tidy fixes for readability-identifier-naming in CLOptionsSetup.cpp (NFC)
Commit: e5e08955af215ac9c918212de2b24036b4d7208c
https://github.com/llvm/llvm-project/commit/e5e08955af215ac9c918212de2b24036b4d7208c
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Arith/Transforms/IntRangeOptimizations.cpp
Log Message:
-----------
Apply clang-tidy fixes for performance-move-const-arg in IntRangeOptimizations.cpp (NFC)
Commit: 75e185d50c3f83c82c02e9df587139a41bf96412
https://github.com/llvm/llvm-project/commit/75e185d50c3f83c82c02e9df587139a41bf96412
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
Log Message:
-----------
Apply clang-tidy fixes for readability-simplify-boolean-expr in LegalizeForLLVMExport.cpp (NFC)
Commit: d8ed736c0e7da7752a3e6f4781d9741aae294f81
https://github.com/llvm/llvm-project/commit/d8ed736c0e7da7752a3e6f4781d9741aae294f81
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
Log Message:
-----------
Apply clang-tidy fixes for bugprone-macro-parentheses in Utils.cpp (NFC)
Commit: 199117ae09ed6bab54277e8007f98404834e277e
https://github.com/llvm/llvm-project/commit/199117ae09ed6bab54277e8007f98404834e277e
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrInfo.cpp
Log Message:
-----------
[X86] Fix error: unused variable 'isMemOp' after #78019, NFCI
BTW, I adjust the code by LLVM coding standards.
Commit: ed7f4edc19ada006789318a0929b57d1b5a761bd
https://github.com/llvm/llvm-project/commit/ed7f4edc19ada006789318a0929b57d1b5a761bd
Author: Jinyang He <hejinyang at loongson.cn>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
A llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll
A llvm/test/DebugInfo/LoongArch/lit.local.cfg
Log Message:
-----------
[LoongArch] Add relaxDwarfLineAddr and relaxDwarfCFA to handle the mutable label diff in dwarfinfo (#77728)
When linker-relaxation is enabled, part of the label diff in dwarfinfo
cannot be computed before static link. Refer to RISCV, we add the
relaxDwarfLineAddr and relaxDwarfCFA to add relocations for these label
diffs. Calculate whether the label diff is mutable. For immutable label
diff, return false and do the other works by its parent function.
Commit: d34ac450a74657f03e15dd6776b406d1f31e054a
https://github.com/llvm/llvm-project/commit/d34ac450a74657f03e15dd6776b406d1f31e054a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Warnings.cpp
Log Message:
-----------
[Basic] Use StringRef::consume_front (NFC)
Commit: d041af3019984f505530bac3acb94ca2f13f33cd
https://github.com/llvm/llvm-project/commit/d041af3019984f505530bac3acb94ca2f13f33cd
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
Log Message:
-----------
[Transforms] Use a range-based for loop (NFC)
Commit: 481fd41aaa343e2ee2c86c2444fbc2e5ad1f3831
https://github.com/llvm/llvm-project/commit/481fd41aaa343e2ee2c86c2444fbc2e5ad1f3831
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M clang-tools-extra/modularize/ModularizeUtilities.cpp
Log Message:
-----------
[modularize] Use SmallString::operator std::string (NFC)
Commit: 6da4a7a8e2f13bcb8889898323e72270829ce63a
https://github.com/llvm/llvm-project/commit/6da4a7a8e2f13bcb8889898323e72270829ce63a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M bolt/tools/bat-dump/bat-dump.cpp
M bolt/tools/driver/llvm-bolt.cpp
M bolt/tools/heatmap/heatmap.cpp
Log Message:
-----------
[BOLT] Use SmallString::operator std::string (NFC)
Commit: 001fb1fa1ca31110693065297e4f02ba15b8298f
https://github.com/llvm/llvm-project/commit/001fb1fa1ca31110693065297e4f02ba15b8298f
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[TableGen] Use llvm::drop_begin (NFC)
Commit: 44aa4d7d826f83777b99c07576cfb88e54266928
https://github.com/llvm/llvm-project/commit/44aa4d7d826f83777b99c07576cfb88e54266928
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-15 (Mon, 15 Jan 2024)
Changed paths:
M llvm/tools/dsymutil/SymbolMap.cpp
Log Message:
-----------
[dsymutil] Use StringRef::consume_front (NFC)
Commit: 286a366d057112a112507b9e34c68d35b3b820f7
https://github.com/llvm/llvm-project/commit/286a366d057112a112507b9e34c68d35b3b820f7
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/extractelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-bitcast.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-explodevector.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-vslide1up.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-strided-load-store-asm.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-unaligned.ll
M llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/insertelt-int-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vfmv.s.f.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.s.x-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv32.ll
M llvm/test/CodeGen/RISCV/rvv/vmv.x.s-rv64.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
M llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir
M llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir
M llvm/test/CodeGen/RISCV/sextw-removal.ll
M llvm/test/CodeGen/RISCV/srem-seteq-illegal-types.ll
Log Message:
-----------
[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)
vmv.s.x and vmv.x.s ignore LMUL, so we can replace the PseudoVMV_S_X_MX
and
PseudoVMV_X_S_MX with just one pseudo each. These pseudos use the VR
register
class (just like the actual instruction), so we now only have TableGen
patterns for vectors of LMUL <= 1.
We now rely on the existing combines that shrink LMUL down to 1 for
vmv_s_x_vl (and vfmv_s_f_vl). We could look into removing these combines
later and just inserting the nodes with the correct type in a later
patch.
The test diff is due to the fact that a PseudoVMV_S_X/PsuedoVMV_X_S no
longer
carries any information about LMUL, so if it's the only vector pseudo
instruction in a block then it now defaults to LMUL=1.
Commit: 5f24e779426594448d803906d44481f5137ed052
https://github.com/llvm/llvm-project/commit/5f24e779426594448d803906d44481f5137ed052
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel] Fix build after 9fa9d9a7e1cd0a7fd8c35bdfc642793447bf70aa
Commit: 57d517c2571d16837a018740c068cca89435ea65
https://github.com/llvm/llvm-project/commit/57d517c2571d16837a018740c068cca89435ea65
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Log Message:
-----------
[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg (#77610)
This helper function handles common cases where we can determine a
constant value is being defined in a register. Although it looks like
codegen changes are possible due to this being called in
PeepholeOptimizer, my main motivation is to use this in
describeLoadedValue.
Commit: 84f7fb6217fd417f3b5cb65fe7636e0aab84f6c7
https://github.com/llvm/llvm-project/commit/84f7fb6217fd417f3b5cb65fe7636e0aab84f6c7
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/misched-load-clustering.ll
Log Message:
-----------
[MachineScheduler] Add option to control reordering for store/load clustering (#75338)
Reordering based on the sort order of the MemOpInfo array was disabled
in <https://reviews.llvm.org/D72706>. However, it's not clear this is
desirable for al targets. It also makes it more difficult to compare the
incremental benefit of enabling load clustering in the selectiondag
scheduler as well was the machinescheduler, as the sdag scheduler does
seem to allow this reordering.
This patch adds a parameter that can control the behaviour on a
per-target basis.
Split out from #73789.
Commit: 2c2b27c0eae900977e4d6e0dfc58832270c73682
https://github.com/llvm/llvm-project/commit/2c2b27c0eae900977e4d6e0dfc58832270c73682
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Fix build after 9fa9d9a7e1cd0a7fd8c35bdfc642793447bf70aa
Commit: af9f2dc7fd45fd07559bd1084b1e6ce170082b70
https://github.com/llvm/llvm-project/commit/af9f2dc7fd45fd07559bd1084b1e6ce170082b70
Author: Christian Sigg <chsigg at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/clang/BUILD.bazel
Log Message:
-----------
[bazel] Fix build after 9fa9d9a7e1cd0a7fd8c35bdfc642793447bf70aa
Commit: af1463d403182720ae0e3fab07634817dd0f41be
https://github.com/llvm/llvm-project/commit/af1463d403182720ae0e3fab07634817dd0f41be
Author: martinboehme <mboehme at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/Formula.h
M clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp
M clang/unittests/Analysis/FlowSensitive/DataflowAnalysisContextTest.cpp
Log Message:
-----------
[clang][dataflow] Add an early-out to `flowConditionImplies()` / `flowConditionAllows()`. (#78172)
This saves having to assemble the set of constraints and run the SAT
solver in
the trivial case of `flowConditionImplies(true)` or
`flowConditionAllows(false)`.
This is an update / reland of my previous reverted
[#77453](https://github.com/llvm/llvm-project/pull/77453). That PR
contained a
logic bug -- the early-out for `flowConditionAllows()` was wrong because
my
intuition about the logic was wrong. (In particular, note that
`flowConditionImplies(F)` does not imply `flowConditionAllows(F)`, even
though
this may run counter to intuition.)
I've now done what I should have done on the first iteration and added
more
tests. These pass both with and without my early-outs.
This patch is a performance win on the benchmarks for the Crubit
nullability
checker, except for one slight regression on a relatively short
benchmark:
```
name old cpu/op new cpu/op delta
BM_PointerAnalysisCopyPointer 68.5µs ± 7% 67.6µs ± 4% ~ (p=0.159 n=18+19)
BM_PointerAnalysisIntLoop 173µs ± 3% 162µs ± 4% -6.40% (p=0.000 n=19+20)
BM_PointerAnalysisPointerLoop 307µs ± 2% 312µs ± 4% +1.56% (p=0.013 n=18+20)
BM_PointerAnalysisBranch 199µs ± 4% 181µs ± 4% -8.81% (p=0.000 n=20+20)
BM_PointerAnalysisLoopAndBranch 503µs ± 3% 508µs ± 2% ~ (p=0.081 n=18+19)
BM_PointerAnalysisTwoLoops 304µs ± 4% 286µs ± 2% -6.04% (p=0.000 n=19+20)
BM_PointerAnalysisJoinFilePath 4.78ms ± 3% 4.54ms ± 4% -4.97% (p=0.000 n=20+20)
BM_PointerAnalysisCallInLoop 3.05ms ± 3% 2.90ms ± 4% -5.05% (p=0.000 n=19+20)
```
When running clang-tidy on real-world code, the results are less clear.
In
three runs, averaged, on an arbitrarily chosen input file, I get 11.60 s
of user
time without this patch and 11.40 s with it, though with considerable
measurement noise (I'm seeing up to 0.2 s of variation between runs).
Still, this is a very simple change, and it is a clear win in
benchmarks, so I
think it is worth making.
Commit: a02a0e806fab01f4cf4307443cdaed76a2488752
https://github.com/llvm/llvm-project/commit/a02a0e806fab01f4cf4307443cdaed76a2488752
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/lib/Transforms/Utils/GreedyPatternRewriteDriver.cpp
Log Message:
-----------
[mlir][Transforms] `GreedyPatternRewriteDriver`: Better expensive checks encapsulation (#78175)
This change moves most IR verification logic (which is part of the
expensive checks) into `DebugFingerPrints` and renames the struct to
`ExpensiveChecks`. This isolates the debugging logic better from the
remaining code.
This commit also removes a redundant check: the IR is no longer verified
after a failed pattern application. We already assert that the IR did
not change. (We know that the IR was valid before the attempted pattern
application.)
Commit: 480cc413b7f7e73f90646e5feeb598e36e4e9565
https://github.com/llvm/llvm-project/commit/480cc413b7f7e73f90646e5feeb598e36e4e9565
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
Log Message:
-----------
AMDGPU/GlobalISel: Handle inreg arguments as SGPRs (#78123)
This is the missing GISel part of
54470176afe20b16e6b026ab989591d1d19ad2b7
Commit: c0a354dfabfd1534bc6f992b242e5d0ea043120d
https://github.com/llvm/llvm-project/commit/c0a354dfabfd1534bc6f992b242e5d0ea043120d
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/LowerVectorContract.cpp
M mlir/test/Dialect/Vector/vector-contract-to-outerproduct-matvec-transforms.mlir
R mlir/test/Dialect/Vector/vector-contract-to-outerproduct-transforms-unsupported.mlir
Log Message:
-----------
[mlir][vector] Fix invalid IR in `ContractionOpLowering` (#78130)
If a rewrite pattern returns "failure", it must not have modified the
IR. This commit fixes
`Dialect/Vector/vector-contract-to-outerproduct-transforms-unsupported.mlir`
when running with `MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS`.
```
* Pattern (anonymous namespace)::ContractionOpToOuterProductOpLowering : 'vector.contract -> ()' {
Trying to match "(anonymous namespace)::ContractionOpToOuterProductOpLowering"
** Insert : 'vector.transpose'(0x5625b3a8cb30)
** Insert : 'vector.transpose'(0x5625b3a8cbc0)
"(anonymous namespace)::ContractionOpToOuterProductOpLowering" result 0
} -> failure : pattern failed to match
} -> failure : pattern failed to match
LLVM ERROR: pattern returned failure but IR did change
```
Note: `vector-contract-to-outerproduct-transforms-unsupported.mlir` is
merged into `vector-contract-to-outerproduct-matvec-transforms.mlir`.
The `greedy pattern application failed` error is not longer produced.
This error indicates that the greedy pattern rewrite did not
convergence; it does not mean that a pattern could not be applied.
Commit: 510626fa65841c5a7d0d909cd343e64c3a9246be
https://github.com/llvm/llvm-project/commit/510626fa65841c5a7d0d909cd343e64c3a9246be
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/lib/Dialect/Vector/Transforms/VectorEmulateNarrowType.cpp
Log Message:
-----------
[mlir][vector] Fix invalid IR in `RewriteBitCastOfTruncI` (#78146)
This commit fixes `Dialect/Vector/vector-rewrite-narrow-types.mlir` when
running with `MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS`.
```
within split at llvm-project/mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir:1 offset :118:8: error: 'arith.trunci' op operand type 'vector<3xi16>' and result type 'vector<3xi16>' are cast incompatible
%1 = vector.bitcast %0 : vector<16xi3> to vector<3xi16>
^
within split at llvm-project/mlir/test/Dialect/Vector/vector-rewrite-narrow-types.mlir:1 offset :118:8: note: see current operation: %48 = "arith.trunci"(%47) : (vector<3xi16>) -> vector<3xi16>
LLVM ERROR: IR failed to verify after pattern application
```
Commit: cd263a7ee00cf508fef54aa9e42789e6a2e60137
https://github.com/llvm/llvm-project/commit/cd263a7ee00cf508fef54aa9e42789e6a2e60137
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/Transforms/Utils/NameAnonGlobals.h
Log Message:
-----------
[NameAnonGlobals] Mark the pass as required (#78161)
NameAnonGlobals is required when emitting ThinLTO bitcode, otherwise the
bitcode writer will crash.
Commit: f725bb960d45ada3cc4667dd7aa22792d389c7e7
https://github.com/llvm/llvm-project/commit/f725bb960d45ada3cc4667dd7aa22792d389c7e7
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaCXX/cxx1z-class-template-argument-deduction.cpp
Log Message:
-----------
[clang] Fix CTAD not work for function-type and array-type arguments. (#78159)
Fixes https://github.com/llvm/llvm-project/issues/51710.
When transforming a constructor into a corresponding deduction guide,
the decayed types (function/array type) were not handled properly which
made clang fail to compile valid code. The patch teaches clang handle
these decayed type in the transformation.
Commit: 27d963a7089b050d402dbc1ae210d505f7affff6
https://github.com/llvm/llvm-project/commit/27d963a7089b050d402dbc1ae210d505f7affff6
Author: Ben Shi <2283975856 at qq.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/test/Analysis/std-c-library-functions-POSIX.c
M clang/test/Analysis/stream-errno.c
Log Message:
-----------
[clang][analyzer] Improve modeling of 'fseeko' and 'ftello' in StdLibraryFunctionsChecker (#77902)
Commit: 8fd32b96caf37113dd425cd9d0ff8c839c6a048a
https://github.com/llvm/llvm-project/commit/8fd32b96caf37113dd425cd9d0ff8c839c6a048a
Author: Clement Courbet <courbet at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang-tools-extra/clang-tidy/performance/ForRangeCopyCheck.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/performance/for-range-copy.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/unittests/Analysis/ExprMutationAnalyzerTest.cpp
Log Message:
-----------
[clang-tidy] Handle C++ structured bindings in `performance-for-range-copy` (#77105)
Right now we are not triggering on:
```
for (auto [x, y] : container) {
// const-only access
}
```
Commit: 4b0a76a3d7d590ca1ec60e8a703969be6550ba17
https://github.com/llvm/llvm-project/commit/4b0a76a3d7d590ca1ec60e8a703969be6550ba17
Author: Pierre van Houtryve <pierre.vanhoutryve at amd.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
A llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
Log Message:
-----------
[GlobalISel] Fix buildCopyFromRegs for split vectors (#77448)
Fixes #77055
Commit: 8f2d83da260fc7e1334ee975d9b00344aab51410
https://github.com/llvm/llvm-project/commit/8f2d83da260fc7e1334ee975d9b00344aab51410
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.h
M mlir/include/mlir/Dialect/Bufferization/IR/BufferizableOpInterface.td
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/Transforms/Bufferize.cpp
M mlir/lib/Dialect/Bufferization/Transforms/FuncBufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp
M mlir/lib/Dialect/Bufferization/Transforms/OneShotModuleBufferize.cpp
Log Message:
-----------
[mlir][bufferization] Add `BufferizableOpInterface::hasTensorSemantics` (#75273)
Add a new interface method to `BufferizableOpInterface`:
`hasTensorSemantics`. This method returns "true" if the op has tensor
semantics and should be bufferized.
Until now, we assumed that an op has tensor semantics if it has tensor
operands and/or tensor op results. However, there are ops like
`ml_program.global` that do not have any results/operands but must still
be bufferized (#75103). The new interface method can return "true" for
such ops.
This change also decouples `bufferization::bufferizeOp` a bit from the
func dialect.
Commit: 01f4d40aad58c5c34a8ae30edbf4e0ebbf235838
https://github.com/llvm/llvm-project/commit/01f4d40aad58c5c34a8ae30edbf4e0ebbf235838
Author: elhewaty <mohamedatef1698 at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/test/Transforms/InstCombine/icmp.ll
Log Message:
-----------
Simplify `(a % b) lt/ge (b-1)` into `(a % b) eq/ne (b-1)` (#72504)
Alive2: https://alive2.llvm.org/ce/z/i7zYtE
Fixes: https://github.com/llvm/llvm-project/issues/71280
Commit: d69efa4015ca41746b1aa517976cc376bce48860
https://github.com/llvm/llvm-project/commit/d69efa4015ca41746b1aa517976cc376bce48860
Author: David Green <david.green at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/gep-alias.ll
Log Message:
-----------
[BasicAA] Handle disjoint or as add in DecomposeGEP. (#78209)
This removes the MaskedValueIsZero check in decomposing geps in BasicAA, using
the isDisjoint flags instead. This relies on the disjoint flags being present
when AA is ran. The alternative would be to keep the old MaskedValueIsZero check
too if this causes issues.
Commit: e366e04d5a3ae8d469ce8e3c88360a9b5ea51054
https://github.com/llvm/llvm-project/commit/e366e04d5a3ae8d469ce8e3c88360a9b5ea51054
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
M llvm/tools/llvm-exegesis/lib/PerfHelper.cpp
M llvm/tools/llvm-exegesis/lib/PerfHelper.h
M llvm/tools/llvm-exegesis/lib/Target.cpp
M llvm/tools/llvm-exegesis/lib/Target.h
M llvm/tools/llvm-exegesis/lib/X86/Target.cpp
M llvm/tools/llvm-exegesis/lib/X86/X86Counter.cpp
M llvm/tools/llvm-exegesis/lib/X86/X86Counter.h
Log Message:
-----------
[llvm-exegesis] Refactor Counter to CounterGroup (#77887)
This refactoring gets things ready for validation counters where the
plan is to reuse the existing Counter infrastructure to contain event
groups that consist of a single event that is being measured along with
validation counters.
Commit: 2b08de43506350ec4bd083e320a1913efe76684a
https://github.com/llvm/llvm-project/commit/2b08de43506350ec4bd083e320a1913efe76684a
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/lib/IR/DebugProgramInstruction.cpp
Log Message:
-----------
[RemoveDIs][DebugInfo][NFC] Add Instruction and convenience functions to DPValue (#77896)
This patch adds a set of functions to the DPValue class that
conveniently perform some common operations, and some that replicate
existing functions on `DbgVariableIntrinsic` and its subclasses.
Commit: a690e8675395563aa74d026dc5c0ecc71009f824
https://github.com/llvm/llvm-project/commit/a690e8675395563aa74d026dc5c0ecc71009f824
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/TargetParser/Host.cpp
M llvm/unittests/TargetParser/Host.cpp
Log Message:
-----------
[AArch64] Add native CPU detection for Microsoft Azure Cobalt 100. (#77793)
This patch extends the -mcpu/mtune=native support to handle the
Microsoft Azure Cobalt 100 CPU as a Neoverse N2. We expect users to use
-mcpu=neoverse-n2 when targeting this CPU and all the architecture and
codegen decisions to be identical.
The only difference is that the Microsoft Azure Cobalt 100 has a
different Implementer ID in the /proc/cpuinfo entry that needs to be
detected in getHostCPUNameForARM appropriately.
Commit: dca6f60bcdd4a8e6c5defad454d9c470a27701fe
https://github.com/llvm/llvm-project/commit/dca6f60bcdd4a8e6c5defad454d9c470a27701fe
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h
Log Message:
-----------
[NFC][clang-tidy]improve performance for misc-unused-using-decls check (#78231)
`UnusedUsingDeclsCheck::removeFromFoundDecls` will be called with high
frequency. At current time it will check every `Context`.
This patch adds a cache to reduce algorithm complexity.
Commit: 2c4a53ad519c64e66257e712d0371f1ab01116d9
https://github.com/llvm/llvm-project/commit/2c4a53ad519c64e66257e712d0371f1ab01116d9
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/lib/Target/X86/X86InstrUtils.td
Log Message:
-----------
[X86][NFC] Simplify the definitions of double precision shift instructions
Commit: fd0e06d1118f14e5a90d5f30b1c9d4b69b0a72eb
https://github.com/llvm/llvm-project/commit/fd0e06d1118f14e5a90d5f30b1c9d4b69b0a72eb
Author: Piotr Zegar <me at piotrzegar.pl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/utils/FixItHintUtils.cpp
M clang-tools-extra/clang-tidy/utils/FixItHintUtils.h
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-allow-in-conditions.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-cxx98.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.cpp
Log Message:
-----------
[clang-tidy] Fix missing parentheses in readability-implicit-bool-conversion fixes (#74891)
Check now more properly add missing parentheses to code like this: 'bool
bar = true ? 1 : 0 != 0;'.
Closes #71867
Commit: a974303e0c9f0654a76f82e0a3221b6d866a5037
https://github.com/llvm/llvm-project/commit/a974303e0c9f0654a76f82e0a3221b6d866a5037
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/tools/llvm-exegesis/lib/PerfHelper.cpp
M llvm/tools/llvm-exegesis/lib/PerfHelper.h
M llvm/tools/llvm-exegesis/lib/X86/X86Counter.cpp
Log Message:
-----------
[llvm-exegesis] Refactor individual counter data to ConfiguredEvent (#77900)
This further sets things up for validation events. Having a separate
abstraction for a configured event that is setup as a counter allows for
much easier creation of more events in the future within a single
counter group (like validation counters) without duplicating any code.
Commit: 8e514c572e44eda237417236b4c92176dfce9cd9
https://github.com/llvm/llvm-project/commit/8e514c572e44eda237417236b4c92176dfce9cd9
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/unittests/Analysis/CMakeLists.txt
A llvm/unittests/Analysis/ReplaceWithVecLibTest.cpp
Log Message:
-----------
Reapply [TLI] Fix replace-with-veclib crash with invalid arguments (#77945)
Fix a crash of `replace-with-veclib` pass, when the arguments of the TLI
mapping do not match the original call.
Now, it simply ignores such cases.
Test require assertions as it accesses programmatically the debug log.
Reapplies reverted PR #77112
Commit: c4c53aee584d51b984d3ee4e4cc11c1bfaf9d3f3
https://github.com/llvm/llvm-project/commit/c4c53aee584d51b984d3ee4e4cc11c1bfaf9d3f3
Author: Momchil Velikov <momchil.velikov at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
Log Message:
-----------
[AArch64] Fix a typo in predicate expression (NFC) (#78162)
This would cause compiler errors if ISel tried to match affected
instructions.
Commit: 8e9e4f8809f6ce93ddc0feb35aee3cc121a2753a
https://github.com/llvm/llvm-project/commit/8e9e4f8809f6ce93ddc0feb35aee3cc121a2753a
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
Log Message:
-----------
[AMDGPU] Remove VT helpers isFloatType, isPackedType, simplify isIntType (#77987)
Commit: 1074b94f5df6e164997cdb494f47657fd49d7cb5
https://github.com/llvm/llvm-project/commit/1074b94f5df6e164997cdb494f47657fd49d7cb5
Author: David Green <david.green at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
M llvm/test/CodeGen/Thumb2/mve-gather-optimisation-deep.ll
Log Message:
-----------
[ARM] Fix phi operand order issue in MVEGatherScatterLowering (#78208)
With commuted operands on the phi node, the two old incoming values
could be removed in the wrong order, removing newly added operand
instead of the old one.
Commit: 60c775769b0ee8f57a41c0667664afb12958eeac
https://github.com/llvm/llvm-project/commit/60c775769b0ee8f57a41c0667664afb12958eeac
Author: Alfie Richards <156316945+AlfieRichardsArm at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
A llvm/test/CodeGen/ARM/sqrshr-uqrshl-unpredictable.ll
A llvm/test/MC/ARM/mve-sqrshr-uqrshl-earlyclobber.s
Log Message:
-----------
[ARM] Add missing earlyclobber to sqrshr and uqrshl instructions. (#77782)
This avoids possible undefined behavior using the same register for Rm
and Rda.
Additionally adds a check in MC to produce an error upon parsing this
case.
Commit: 289999bad76e34441a3a43f4bf32e028b43fad93
https://github.com/llvm/llvm-project/commit/289999bad76e34441a3a43f4bf32e028b43fad93
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_dot.c
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-dots.ll
Log Message:
-----------
[Clang] Make sdot builtins available to SME (#77792)
See the specification for more details:
*
https://github.com/ARM-software/acle/blob/main/main/acle.md#udot-sdot-fdot-vectors
*
https://github.com/ARM-software/acle/blob/main/main/acle.md#udot-sdot-fdot-indexed
Commit: de8f782355842a5d3ad44ad8861c53e3ef6fa73a
https://github.com/llvm/llvm-project/commit/de8f782355842a5d3ad44ad8861c53e3ef6fa73a
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/test/Transforms/InstCombine/icmp.ll
Log Message:
-----------
Revert "Simplify `(a % b) lt/ge (b-1)` into `(a % b) eq/ne (b-1)` (#72504)"
This reverts commit 01f4d40aad58c5c34a8ae30edbf4e0ebbf235838.
Causes test failures.
Commit: 26d3cd1d07ae3fc8312feb2ab3a3a86414f28c70
https://github.com/llvm/llvm-project/commit/26d3cd1d07ae3fc8312feb2ab3a3a86414f28c70
Author: XChy <xxs_chy at outlook.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Utils/MoveAutoInit.cpp
A llvm/test/Transforms/MoveAutoInit/catchswitch.ll
M llvm/test/Transforms/MoveAutoInit/loop.ll
Log Message:
-----------
[MoveAutoInit] Ignore unreachable basicblocks and handle catchswitch (#78232)
Fixes #78049
This patch has done:
- Ignore unreachable predecessors when looking for nearest common
dominator.
- Check catchswitch with `getFirstNonPHI`, instead of
`getFirstInsertionPt`. The latter skips EHPad.
Commit: 17058940c0187f5c4e2118ab0fed22ebe4bf6f26
https://github.com/llvm/llvm-project/commit/17058940c0187f5c4e2118ab0fed22ebe4bf6f26
Author: Hristo Hristov <hristo.goshev.hristov at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/include/__utility/cmp.h
Log Message:
-----------
[libc++][utility][NFC] Refactored safe integer `cmp_xxxx` functions to use the `__libcpp_is_integer` concept (#78115)
Replaced a functionally identical internal concept helper.
References:
- https://eel.is/c++draft/utility.intcmp
- https://eel.is/c++draft/basic.fundamental
Co-authored-by: Zingam <zingam at outlook.com>
Commit: 076eb4c79ec7e489a041379b82279bf1740f2bb3
https://github.com/llvm/llvm-project/commit/076eb4c79ec7e489a041379b82279bf1740f2bb3
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
Log Message:
-----------
[bazel] Add dependencies for 8e514c572e44eda237417236b4c92176dfce9cd9
Commit: 032c832719b5b2c44b78359ed54b91964ef15b79
https://github.com/llvm/llvm-project/commit/032c832719b5b2c44b78359ed54b91964ef15b79
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/utils/TableGen/SveEmitter.cpp
Log Message:
-----------
[Clang][AArch64] Remove unnecessary and incorrect attributes from arm_sme.h.
These attributes were using the GNU attribute syntax, rather than the new
keyword attribute syntax, and they are no longer required as we have code
in SemaChecking to verify whether a builtin is compatible with its caller.
Commit: c19cacfa34f52b65addeb7239d564b20e3cf2c61
https://github.com/llvm/llvm-project/commit/c19cacfa34f52b65addeb7239d564b20e3cf2c61
Author: martinboehme <mboehme at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h
M clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h
M clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp
M clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
Log Message:
-----------
[clang][dataflow] Tighten checking for existence of a function body. (#78163)
In various places, we would previously call `FunctionDecl::hasBody()`
(which
checks whether any redeclaration of the function has a body, not
necessarily the
one on which `hasBody()` is being called).
This is bug-prone, as a recent bug in Crubit's nullability checker has
shown
([fix](https://github.com/google/crubit/commit/4b01ed0f14d953cda20f92d62256e7365d206b2e),
[fix for the
fix](https://github.com/google/crubit/commit/e0c5d8ddd7d647da483c2ae198ff91d131c12055)).
Instead, we now use `FunctionDecl::doesThisDeclarationHaveABody()`
which, as the
name implies, checks whether the specific redeclaration it is being
called on
has a body.
Alternatively, I considered being more lenient and "canonicalizing" to
the
`FunctionDecl` that has the body if the `FunctionDecl` being passed is a
different redeclaration. However, this also risks hiding bugs: A caller
might
inadverently perform the analysis for all redeclarations of a function
and end
up duplicating work without realizing it. By accepting only the
redeclaration
that contains the body, we prevent this.
I've checked, and all clients that I'm aware of do currently pass in the
redeclaration that contains the function body. Typically this is because
they
use the `ast_matchers::hasBody()` matcher which, unlike
`FunctionDecl::hasBody()`, only matches for the redeclaration containing
the
body.
Commit: 86bc18ade8f335f03f607142311957129e156efc
https://github.com/llvm/llvm-project/commit/86bc18ade8f335f03f607142311957129e156efc
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrShiftRotate.td
Log Message:
-----------
[X86][NFC] Simplify the definitions of BMI shift/rotate instructions
Commit: b1eaffd389045827a649b95726824bfc5d0de0fd
https://github.com/llvm/llvm-project/commit/b1eaffd389045827a649b95726824bfc5d0de0fd
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
A llvm/test/CodeGen/X86/apx/and.ll
Log Message:
-----------
[X86][test] Add test for lowering NDD AND
We supported encoding/decoding for APX AND in #76319
This test should be added in #77564 but was missing.
Commit: e2bb47caa69f393b011c2d8e3295587ae35699b5
https://github.com/llvm/llvm-project/commit/e2bb47caa69f393b011c2d8e3295587ae35699b5
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/lib/Dialect/ArmSME/Transforms/TileAllocation.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeVectorStorage.cpp
Log Message:
-----------
[mlir][Arm] Fix invalid rewrite pattern API violations (#78246)
This commit fixes rewrite pattern API violations:
* Rewrite pattern must return "failure" if the IR was not modified.
* In-place op modifications must be communicated to the rewriter
(`updateRootInPlace`).
This commit fixes `test/Dialect/ArmSVE/legalize-vector-storage.mlir`,
`test/Dialect/ArmSME/vector-ops-to-llvm.mlir`,
`test/Dialect/ArmSME/tile-allocation-invalid.mlir`,
`test/Conversion/ArmSMEToLLVM/arm-sme-to-llvm.mlir`,
`test/Conversion/ArmSMEToLLVM/tile-spills-and-fills.mlir`,
`test/Conversion/ArmSMEToLLVM/unsupported.mlir` when running with
`MLIR_ENABLE_EXPENSIVE_PATTERN_API_CHECKS`.
---------
Co-authored-by: Benjamin Maxwell <macdue at dueutil.tech>
Commit: 3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a
https://github.com/llvm/llvm-project/commit/3ac9fe69f70a2b3541266daedbaaa7dc9c007a2a
Author: Wang Pengcheng <wangpengcheng.pp at bytedance.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv32-abi.c
A clang/test/CodeGen/RISCV/riscv32-ilp32e-error.c
M clang/test/CodeGen/RISCV/riscv32-vararg.c
M clang/test/CodeGen/RISCV/riscv64-abi.c
M clang/test/CodeGen/RISCV/riscv64-vararg.c
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
M llvm/include/llvm/Support/RISCVAttributes.h
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
M llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
M llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
A llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
A llvm/test/CodeGen/RISCV/calling-conv-lp64e.ll
A llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32e.ll
M llvm/test/CodeGen/RISCV/interrupt-attr.ll
A llvm/test/CodeGen/RISCV/rv32e.ll
A llvm/test/CodeGen/RISCV/rv64e.ll
R llvm/test/CodeGen/RISCV/rve.ll
M llvm/test/CodeGen/RISCV/stack-realignment-with-variable-sized-objects.ll
M llvm/test/CodeGen/RISCV/stack-realignment.ll
M llvm/test/CodeGen/RISCV/target-abi-valid.ll
A llvm/test/CodeGen/RISCV/vararg-ilp32e.ll
M llvm/test/CodeGen/RISCV/vararg.ll
M llvm/test/MC/RISCV/option-invalid.s
M llvm/test/MC/RISCV/target-abi-invalid.s
Log Message:
-----------
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
This commit includes the necessary changes to clang and LLVM to support
codegen of `RVE` and the `ilp32e`/`lp64e` ABIs.
The differences between `RVE` and `RVI` are:
* `RVE` reduces the integer register count to 16(x0-x16).
* The ABI should be `ilp32e` for 32 bits and `lp64e` for 64 bits.
`RVE` can be combined with all current standard extensions.
The central changes in ilp32e/lp64e ABI, compared to ilp32/lp64 are:
* Only 6 integer argument registers (rather than 8).
* Only 2 callee-saved registers (rather than 12).
* A Stack Alignment of 32bits (rather than 128bits).
* ilp32e isn't compatible with D ISA extension.
If `ilp32e` or `lp64` is used with an ISA that has any of the registers
x16-x31 and f0-f31, then these registers are considered temporaries.
To be compatible with the implementation of ilp32e in GCC, we don't use
aligned registers to pass variadic arguments and set stack alignment\
to 4-bytes for types with length of 2*XLEN.
FastCC is also supported on RVE, while GHC isn't since there is only one
avaiable register.
Differential Revision: https://reviews.llvm.org/D70401
Commit: 12c7d4c4b4ddbb9ee407bcfbfb79e47ae1de832a
https://github.com/llvm/llvm-project/commit/12c7d4c4b4ddbb9ee407bcfbfb79e47ae1de832a
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M flang/lib/Lower/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP] Remove space before :: in member function definition,… (#78205)
… NFC
The names were
```
bool DataSharingProcessor ::needBarrier()
void DataSharingProcessor ::insertBarrier()
```
It seems like clang-format treats those as references to the global
namespace instead of separators in a qualified name.
Commit: da6806dcb45d311efceaba0d770d9027d68a0de9
https://github.com/llvm/llvm-project/commit/da6806dcb45d311efceaba0d770d9027d68a0de9
Author: Ben Shi <2283975856 at qq.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
Log Message:
-----------
Improve modeling of two functions in StdLibraryFunctionsChecker (#78079)
Improve 'errno' modeling of 'opendir' and 'fdopendir'.
Commit: c20811b659766469e80317702ee204ef6c4375b4
https://github.com/llvm/llvm-project/commit/c20811b659766469e80317702ee204ef6c4375b4
Author: Petr Hosek <phosek at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libc/CMakeLists.txt
M libc/utils/HdrGen/CMakeLists.txt
M llvm/cmake/modules/CrossCompile.cmake
M llvm/runtimes/CMakeLists.txt
Log Message:
-----------
[libc] Fix libc-hdrgen crosscompiling (#78227)
The support introduced in 675702f356b0c3a540fa2e8af4192f7d658b2988 is
not working correctly in all scenarios. Instead of setup_host_tool
function, we can use the existing targets introduced by add_tablegen
macro.
Commit: d499df02a2508641d67918d7dc41b2e01a4a4114
https://github.com/llvm/llvm-project/commit/d499df02a2508641d67918d7dc41b2e01a4a4114
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Metadata.cpp
Log Message:
-----------
[RemoveDIs][DebugInfo] Add DPVAssign variant of DPValue (#77912)
This implements the DbgAssignIntrinsic class as a variant of DPValues -
unfortunately this involves increasing the size of the `DebugValueUser`
storage by 3x, but this is necessary to enable assigns to be
represented, and can be offset in a future patch by splitting DPValue
into subclasses such that each variant can store only the fields it
needs. This patch does not actually create DPVAssigns in any case;
future patches will handle this variant in all cases where generic
DPValue handling does not. This patch also does not implement tracking
support for DIAssignIDs, which is necessary to find DPVAssigns that
reference a given DIAssignID; that is added in a subsequent patch.
Commit: 4967d98eda48bed4a6f382d240f5a33177bc654c
https://github.com/llvm/llvm-project/commit/4967d98eda48bed4a6f382d240f5a33177bc654c
Author: Heejin Ahn <aheejin at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libunwind/src/libunwind.cpp
Log Message:
-----------
[libunwind][WebAssembly] Fix libunwind.cpp guard (#78230)
This should have been `&&`, meaning neither SjLj nor Wasm uses this
file.
Commit: a9bfad2b9b04772836827c351a9365a7cbddcba0
https://github.com/llvm/llvm-project/commit/a9bfad2b9b04772836827c351a9365a7cbddcba0
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel][llvm] Sort load statements
Commit: 93d39657f5e60db99b004d898406d1304705a87f
https://github.com/llvm/llvm-project/commit/93d39657f5e60db99b004d898406d1304705a87f
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll
Log Message:
-----------
[RISCV] Remove -riscv-v-vector-bits-min flag that was left behind. NFC
This should have been removed in 74f985b793bf4005e49736f8c2cef8b5cbf7c1ab
Commit: 9e068cd78491d371f30fa2c5eeed98585adbef80
https://github.com/llvm/llvm-project/commit/9e068cd78491d371f30fa2c5eeed98585adbef80
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-cache-construct.c
Log Message:
-----------
[OpenACC} Improve diagnostics for 'tag's on clauses/directives (#77957)
The 'cache' directive and various clauses have a 'tag' name that is
optional. This patch cleans up the use of the 'cache' version so that we
get a nicer diagnostic, and enables us to do the same with clauses in
the same situation.
Commit: da7607307a5eed532d1ad9d2cd020e67b299b129
https://github.com/llvm/llvm-project/commit/da7607307a5eed532d1ad9d2cd020e67b299b129
Author: Stephen Tozer <Stephen.Tozer at Sony.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/IR/Metadata.cpp
Log Message:
-----------
[RemoveDIs][DebugInfo] Explicitly convert iterator to pointer for std::distance
This is a small patch attempting to fix an error with a prior patch which
caused buildbot failures on certain targets; for example:
https://lab.llvm.org/buildbot/#/builders/127/builds/60931
The compile error comes from std::distance not having an overload for a
std::array iterator and a raw pointer; this patch converts the iterator
to a pointer to resolve this.
Fixes d499df02
Commit: 6011d6b2cceaed14b03c6a9759b4af3b56bdc262
https://github.com/llvm/llvm-project/commit/6011d6b2cceaed14b03c6a9759b4af3b56bdc262
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
Log Message:
-----------
[VPlan] Use start value of reduction phi to determine type (NFCI).
Instead of accessing the underlying original IR value, check the type of
the start value from the recipe directly.
Commit: fdbf255c96cb18bc1fb08fa7264446bcbbd5fbd0
https://github.com/llvm/llvm-project/commit/fdbf255c96cb18bc1fb08fa7264446bcbbd5fbd0
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
R libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/utils/FPUtil/x86_long_double_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
Log Message:
-----------
[libc][NFC] Refactor FPBits and remove LongDoubleBits specialization (#78192)
This patch removes the `FPBits` specialization for x86 Extended Precision by moving it up to `FPRep`.
It also introduces enums (`Exponent`, `BiasedExponent` and `Significand`) to represent the exponent and significant parts of the floating point numbers. These enums are used to construct and observe floating point representations.
Additionally, we remove `LongDoubleBits.h` that is now unnecessary.
Commit: 19cab7ef2e14d6e6b174019b6fd1549b476e1907
https://github.com/llvm/llvm-project/commit/19cab7ef2e14d6e6b174019b6fd1549b476e1907
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/pseudo/lib/grammar/BUILD.gn
M llvm/utils/gn/secondary/clang/include/clang/Basic/BUILD.gn
M llvm/utils/gn/secondary/clang/lib/Basic/BUILD.gn
Log Message:
-----------
[gn] port 8e7f073eb42c (-gen-clang-regular-keyword-attr-info)
Commit: 23bfc271a316345459809427d98e942455d0e2b6
https://github.com/llvm/llvm-project/commit/23bfc271a316345459809427d98e942455d0e2b6
Author: martinboehme <mboehme at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/unittests/Analysis/FlowSensitive/DataflowEnvironmentTest.cpp
Log Message:
-----------
[clang][dataflow] Use `ignoreCFGOmittedNodes()` in `setValue()`. (#78245)
This is to be consistent with `getValue()`, which also uses
`ignoreCFGOmittedNodes()`.
Before this fix, it was not possible to retrieve a `Value` from a "CFG
omitted"
node that had previously been set using `setValue()`; see the
accompanying test,
which fails without the fix.
I discovered this issue while running internal integration tests on
https://github.com/llvm/llvm-project/pull/78127.
Commit: 279dfe77da718734ccc6ebd8ae6c40357c9d6721
https://github.com/llvm/llvm-project/commit/279dfe77da718734ccc6ebd8ae6c40357c9d6721
Author: Maciej Gabka <maciej.gabka at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/test/Transforms/LoopVectorize/AArch64/veclib-function-calls.ll
Log Message:
-----------
[TLI][AArch64] Add extra SLEEF mappings and tests (#78140)
This patch is adding more scalar to vector mappings to the TLI
for the SLEEF vector library.
The added mappings are for the following functions:
acosh, asinh, cbrt, copysign, cospi
erf, erfc, expm1, fdim, fma, fmax, fmin
hypot, ilogb, ldexp, log1p, nextafter, sinpi.
It also brings back accidentally removed tests for sincospi.
Commit: d79fdb2749b26d1d6801a85090fa36a66a56036f
https://github.com/llvm/llvm-project/commit/d79fdb2749b26d1d6801a85090fa36a66a56036f
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/replaced-external-in-reduction.ll
Log Message:
-----------
[SLP]Fix PR78236: correctly track external values, replaced several
times during reduction vectorization.
If the external value was replaced in the vectorizer several times during reduction vectorization, need to find the original value to correctly handle external uses and emit extractelement instructions properly.
Commit: dfaf09b5d1a0da1a700808d35a12a2a15f38f4ab
https://github.com/llvm/llvm-project/commit/dfaf09b5d1a0da1a700808d35a12a2a15f38f4ab
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrShiftRotate.td
Log Message:
-----------
[X86][NFC] Simplify the patterns of BMI shift/rotate instructions in X86InstrShiftRotate.td
This patch is to extract NFC in #77433 into a separate commit.
Commit: a63d7872f059784c9bfd24adb37e868247f3cfc9
https://github.com/llvm/llvm-project/commit/a63d7872f059784c9bfd24adb37e868247f3cfc9
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
Revert "[bazel][llvm] Sort load statements"
This reverts commit a9bfad2b9b04772836827c351a9365a7cbddcba0.
Commit: d835d6f4fface8ac093b7583e07f4ce5b1802042
https://github.com/llvm/llvm-project/commit/d835d6f4fface8ac093b7583e07f4ce5b1802042
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Parse/ParseOpenACC.cpp
Log Message:
-----------
[OpenACC} Improve diagnostics for 'tag's on clauses/directives
The 'cache' directive and various clauses have a 'tag' name that is
optional. This patch cleans up the use of the 'cache' version so that
we get a nicer diagnostic, and enables us to do the same with clauses in
the same situation.
Commit: d5000e9cd95b720fc9082da6cdcdb2c865303dcf
https://github.com/llvm/llvm-project/commit/d5000e9cd95b720fc9082da6cdcdb2c865303dcf
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Parse/ParseOpenACC.cpp
Log Message:
-----------
rename to 'try' isntead of 'Try'x
Commit: eca25bbdbb4f4681cd82de80e92b5f1315f0996a
https://github.com/llvm/llvm-project/commit/eca25bbdbb4f4681cd82de80e92b5f1315f0996a
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
Log Message:
-----------
[OpenACC] Implement 'copyout' clause parsing.
This is a fairly simple clause that just requires parsing a potential
'zero:' in front of a Clause var-list. This patch implements/tests
that.
Commit: aa440aae36474525211d02bbc0d120cc90c91cbf
https://github.com/llvm/llvm-project/commit/aa440aae36474525211d02bbc0d120cc90c91cbf
Author: Tarun Prabhu <tarun at lanl.gov>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M flang/test/Driver/driver-help-hidden.f90
M flang/test/Driver/driver-help.f90
A flang/test/Driver/pthread.f90
Log Message:
-----------
[flang][Driver] Support -pthread in the frontend (#77360)
The -pthread option seems to be extensively tested for various platforms by
clang. Since flang uses those parts of the clang driver, the only test added
is to ensure that the option is recognized by the frontend.
Commit: e7671bc9d6da20ed7ed5877bb3c43c373019886f
https://github.com/llvm/llvm-project/commit/e7671bc9d6da20ed7ed5877bb3c43c373019886f
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
Log Message:
-----------
[LV] Fix indent for loop in adjustRecipesForReductions (NFC).
Commit: c1a442462d9d47f86392da7e7019ab218d7a3088
https://github.com/llvm/llvm-project/commit/c1a442462d9d47f86392da7e7019ab218d7a3088
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libunwind/src/UnwindCursor.hpp
Log Message:
-----------
[libunwind] Move errno.h and signal.h includes under the block where they're needed (#78054)
Commit fc1c478709e3 added includes of <signal.h> and <errno.h> to
UnwindCursor.hpp. The library previously built on platforms where these
headers are not provided. These headers should be included only in the
case where they are actually needed, i.e. on Linux.
Commit: bd26ce47c820858856bd33f20b0c606973155f51
https://github.com/llvm/llvm-project/commit/bd26ce47c820858856bd33f20b0c606973155f51
Author: Tobias Gysi <tobias.gysi at nextsilicon.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMAttrDefs.td
M mlir/lib/Target/LLVMIR/LoopAnnotationImporter.cpp
M mlir/test/Dialect/LLVMIR/loop-metadata.mlir
Log Message:
-----------
[mlir][llvm] Fix loop annotation parser (#78266)
This revision moves the ArrayRef field of the LoopAnnotation attribute
to the end of the struct to enable printing and parsing of the
attribute. Previously, the parsing could fail in the presence of a start
or end loc.
Commit: 118d4234ac6d0893974d324cdb738a1e0255c08d
https://github.com/llvm/llvm-project/commit/118d4234ac6d0893974d324cdb738a1e0255c08d
Author: Koakuma <koachan at protonmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
A llvm/test/CodeGen/SPARC/getpcx-call.ll
A llvm/test/CodeGen/SPARC/getpcx-rdpc.ll
Log Message:
-----------
[SPARC] Prefer RDPC over CALL to implement GETPCX for 64-bit target
On 64-bit target, prefer using RDPC over CALL to get the value of %pc.
This is faster on modern processors (Niagara T1 and newer) and avoids
polluting the processor's predictor state.
The old behavior of using a fake CALL is still done when tuning for
classic UltraSPARC processors, since RDPC is much slower there.
A quick pgbench test on a SPARC T4 shows about 2% speedup on SELECT
loads, and about 7% speedup on INSERT/UPDATE loads.
Reviewed By: @s-barannikov
Github PR: https://github.com/llvm/llvm-project/pull/78280
Commit: 7b8f7f75a0be5571f3b01a9cebbfce929bbc76b3
https://github.com/llvm/llvm-project/commit/7b8f7f75a0be5571f3b01a9cebbfce929bbc76b3
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
Log Message:
-----------
[OpenACC] Implement copyin/create clause parsing.
Implement two more clauses, copyin and create. These are both pretty
simple in that they are just a tag followed by a var-list.
Commit: 9a402d6fbbeff21d72fc49befef7571ddaf39227
https://github.com/llvm/llvm-project/commit/9a402d6fbbeff21d72fc49befef7571ddaf39227
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
Log Message:
-----------
[LV] Make DL optional argument for VPBuilder member functions (NFCI).
Commit: 1617c8d3b8c5fc5d1ec54e4e1b2c43679e573065
https://github.com/llvm/llvm-project/commit/1617c8d3b8c5fc5d1ec54e4e1b2c43679e573065
Author: Zequan Wu <zequanwu at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Host/Config.h.cmake
M lldb/tools/driver/Driver.cpp
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/tools/lldb-server/lldb-server.cpp
M llvm/CMakeLists.txt
M llvm/utils/gn/secondary/lldb/include/lldb/Host/BUILD.gn
Log Message:
-----------
[lldb] Add LLDB_BUG_REPORT_URL macro to allow a different URL for lldb bug reporting. (#78210)
This allows release teams to customize the bug report url for lldb. It
also removes unnecessary constructions of
`llvm::PrettyStackTraceProgram` as it's already constructed inside
`llvm::InitLLVM`.
Commit: 77610dd10454e87bb387040d2b51100a17ac5755
https://github.com/llvm/llvm-project/commit/77610dd10454e87bb387040d2b51100a17ac5755
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxxabi/CMakeLists.txt
Log Message:
-----------
[libc++abi] Fix typo in CMake error message
Commit: f1ef910b97d6acb80480b79a4144541311369cc9
https://github.com/llvm/llvm-project/commit/f1ef910b97d6acb80480b79a4144541311369cc9
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Core/DebuggerEvents.h
M lldb/include/lldb/Core/Progress.h
M lldb/source/Core/Progress.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolLocator/Default/SymbolLocatorDefault.cpp
M lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py
Log Message:
-----------
[lldb][Progress] Separate title and details (#77547)
Per this RFC:
https://discourse.llvm.org/t/rfc-improve-lldb-progress-reporting/75717
on improving progress reports, this commit separates the title field and
details field so that the title specifies the category that the progress
report falls under. The details field is added as a part of the
constructor for progress reports and by default is an empty string. In addition, changes the total amount of progress completed into a std::optional. Also
updates the test to check for details being correctly reported from the
event structured data dictionary.
Commit: 6c1b5ec213ee7376bed9357211e5582931318974
https://github.com/llvm/llvm-project/commit/6c1b5ec213ee7376bed9357211e5582931318974
Author: Shengchen Kan <shengchen.kan at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
Log Message:
-----------
[X86][NFC] Simplify the patterns of BMI shift/rotate instructions in X86InstrCompiler.td
This patch is to extract NFC in #77433 into a separate commit.
Commit: 154cea4d4ab762174bc44676452fb94879a5659e
https://github.com/llvm/llvm-project/commit/154cea4d4ab762174bc44676452fb94879a5659e
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/readability/BUILD.gn
Log Message:
-----------
[gn build] Port 8e21557d0401
Commit: a7d01da7d7d2b1936755b85c2553abaed19fdb16
https://github.com/llvm/llvm-project/commit/a7d01da7d7d2b1936755b85c2553abaed19fdb16
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
Log Message:
-----------
[gn build] Port 8e514c572e44
Commit: 27acfdd2ded8c3b246dc2580ba43c285741b1dfd
https://github.com/llvm/llvm-project/commit/27acfdd2ded8c3b246dc2580ba43c285741b1dfd
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/clang/tools/clang-linker-wrapper/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/Frontend/Offloading/BUILD.gn
Log Message:
-----------
[gn build] Port 9fa9d9a7e1cd
Commit: cbaadb1f0ff9966a65c926b3d8c32f2f47281b73
https://github.com/llvm/llvm-project/commit/cbaadb1f0ff9966a65c926b3d8c32f2f47281b73
Author: Julian Schmidt <44101708+5chmidti at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/LibASTMatchersReference.html
M clang/docs/ReleaseNotes.rst
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/unittests/AST/ASTImporterTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNarrowingTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersNodeTest.cpp
M clang/unittests/ASTMatchers/ASTMatchersTraversalTest.cpp
Log Message:
-----------
[clang][ASTMatcher] Add matchers for CXXFoldExpr (#71245)
Adds support for the following matchers related to `CXXFoldExpr`:
`cxxFoldExpr`, `callee`,
`hasInit`, `hasPattern`, `isRightFold`, `isLeftFold`,
`isUnaryFold`, `isBinaryFold`, `hasOperator`, `hasLHS`, `hasRHS`.
Commit: f1f1875c18b8ba794a073e924b5c61f0ff7ae60b
https://github.com/llvm/llvm-project/commit/f1f1875c18b8ba794a073e924b5c61f0ff7ae60b
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libc/CMakeLists.txt
Log Message:
-----------
[libc][cmake] reset COMPILE_DEFINITIONS (#77810)
While trying to enable -Werror (#74506), the 32b ARM build bot reported
an
error stemming from -Wshorten-64-to-32 related to usages of `off_t`.
I failed to fix these properly in #77350 (the 32b ARM build is not a
fullbuild)
and #77396.
It turns out, the preprocessor defines `-D_LARGEFILE_SOURCE` and
`-D_FILE_OFFSET_BITS=64` were being set for llvmlibc when using the
cmake build
system. In particular, these preprocessor defines are feature test
macros used
by glibc, and which have effects no the corresponding ABI for types like
`off_t` (for instance, should `off_t` be 32b or 64b on 32b targets).
But who was setting these? Turns out that the use of
add_compile_definitions
in llvm/cmake/modules/HandleLLVMOptions.cmake was setting these (and
more),
which is then inherited by every subdirectory. While some of these
defines
maybe make sense for host builds, they do not make sense for libraries
for the
target. The full list of defines being set prior to this commit:
- `-D_GNU_SOURCE`
- `-D_FILE_OFFSET_BITS=64`
- `-D_DEBUG`
- `-D_GLIBCXX_ASSERTIONS`
- `-D_LARGEFILE_SOURCE`
- `-D_FILE_OFFSET_BITS=64`
- `-D__STDC_CONSTANT_MACROS`
- `-D__STDC_FORMAT_MACROS`
- `-D__STDC_LIMIT_MACROS`
If we desire any of the above, we should manually reset them.
Fix this by resetting COMPILE_DEFINITIONS for the libc/ subdirectory.
Side note: to debug 'directory properties' in cmake, you first need to
use
`get_directory_property` to fetch the corresponding value into a
variable
first, then that variable can be printed via `message`.
Link:
https://www.gnu.org/software/libc/manual/html_node/Feature-Test-Macros.html#index-_005fFILE_005fOFFSET_005fBITS
Link:
https://www.gnu.org/software/libc/manual/html_node/Feature-Test-Macros.html#index-_005fFILE_005fOFFSET_005fBITS
Fixes: #77395
Commit: a4ec04ea77afa8fb6c08fe8f77c664c95a5eb62e
https://github.com/llvm/llvm-project/commit/a4ec04ea77afa8fb6c08fe8f77c664c95a5eb62e
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
M llvm/test/Verifier/sme-attributes.ll
M llvm/unittests/Target/AArch64/SMEAttributesTest.cpp
Log Message:
-----------
[AArch64][SME2] Add ZT0 attributes to SMEAttrs (#77607)
This patch extends SMEAttrs to interpret the following new attributes,
which are mutually exclusive and apply to SME2 only:
- aarch64_sme_zt0_in (ZT0_In)
- aarch64_sme_zt0_out (ZT0_Out)
- aarch64_sme_zt0_inout (ZT0_InOut)
- aarch64_sme_zt0_new (ZT0_New)
- aarch64_sme_zt0_preserved (ZT0_Preserved)
ZT0_In, ZT0_Out, ZT0_InOut & ZT0_Preserved are all considered to share
ZT0. These attributes will be required by later patches to determine
if ZT0 should be preserved around function calls, or cleared on entry
to the function.
Commit: 127fc7930a7571694888f057ca6f17314b23d355
https://github.com/llvm/llvm-project/commit/127fc7930a7571694888f057ca6f17314b23d355
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
R libcxx/docs/ReleaseNotes/17.rst
M libcxx/docs/index.rst
Log Message:
-----------
[libc++][doc] Removes LLVM-17 release notes. (#78062)
The old notes are kept to make it easier to backport changes to the
release branch. There are no LLVM-17 releases expected and this
documentation should not be available in the LLVM-18 release.
Note after branching LLVM-18 both LLVM-18 and LLVM-19 release notes
should be available.
Commit: a8b3deb2c8be419c06c258751d4d5ba03699afac
https://github.com/llvm/llvm-project/commit/a8b3deb2c8be419c06c258751d4d5ba03699afac
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/include/ostream
M libcxx/include/print
Log Message:
-----------
[libc++][print] Renames __use_unicode. (#76290)
This is addresses a review comment in #73262.
Commit: 82d21814e6556480a71c83a2f8da350d0c8cadf6
https://github.com/llvm/llvm-project/commit/82d21814e6556480a71c83a2f8da350d0c8cadf6
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/include/ostream
M libcxx/include/print
A libcxx/test/libcxx/input.output/iostream.format/output.streams/ostream.syn/includes.compile.pass.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
A libcxx/test/std/input.output/iostream.format/print.fun/includes.compile.pass.cpp
Log Message:
-----------
[libc++][print] Includes <format>. (#76333)
The overloads of `println` are specified in terms of `format`. The
function `format` is specified to work with ranges.
The implementations for `println` do not include `<format>`, but
libc++'s granularized header. This means the following example does not
work
#include <vector>
#include <print>
int main() {
std::vector<int> v{1, 2, 3};
std::println("{}", v);
}
(The other print functions also require this to work, they are specified
in terms of other format functions.)
Fixes: https://github.com/llvm/llvm-project/issues/71925
Commit: 662d1cb86bc156f4c8b5d991b3262e3649479540
https://github.com/llvm/llvm-project/commit/662d1cb86bc156f4c8b5d991b3262e3649479540
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
A llvm/test/CodeGen/X86/pr78109.ll
Log Message:
-----------
[X86] Add test case for Issue #78109
Commit: be690ea3dbd3b92265ecf620b158f4715c97d040
https://github.com/llvm/llvm-project/commit/be690ea3dbd3b92265ecf620b158f4715c97d040
Author: yonillasky <yonillasky at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Coroutines/CoroEarly.cpp
M mlir/lib/Dialect/Async/Transforms/AsyncToAsyncRuntime.cpp
Log Message:
-----------
[Coroutines] Fix incorrect attribute name coroutine.presplit (NFC) (#78296)
Those are probably leftovers from an old name of the same attribute.
Fixed for the sake of consistency.
Co-authored-by: Yoni Lavi <yoni.lavi at nextsilicon.com>
Commit: 7fe5269b544b33c9e32de50b76fe0b67022de6d3
https://github.com/llvm/llvm-project/commit/7fe5269b544b33c9e32de50b76fe0b67022de6d3
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/test/Preprocessor/riscv-target-features.c
M llvm/docs/RISCVUsage.rst
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/test/CodeGen/RISCV/attributes.ll
M llvm/test/MC/RISCV/attribute-arch.s
M llvm/unittests/Support/RISCVISAInfoTest.cpp
Log Message:
-----------
[RISCV] Bump Zfbfmin, Zvfbfmin, and Zvfbfwma to 1.0. (#78021)
Commit: 847c78726920e4a29d71bdc3a46c92a0bc26bfc4
https://github.com/llvm/llvm-project/commit/847c78726920e4a29d71bdc3a46c92a0bc26bfc4
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVProcessors.td
A llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
Log Message:
-----------
[RISCV] Add scheduler model for sifive-p450. (#77989)
This is a slightly cleaned up version of what we've been using in our
downstream toolchain.
Commit: 03f260fd831fb0e5cd77599afb0437a36bc1cd0c
https://github.com/llvm/llvm-project/commit/03f260fd831fb0e5cd77599afb0437a36bc1cd0c
Author: Tom Eccles <tom.eccles at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M flang/CMakeLists.txt
Log Message:
-----------
[flang] Add install target to install flang headers (#78151)
This makes it more convenient to install flang without using the general
`ninja install` to install everything.
To install flang-new and associated things one needs `ninja
install-flang-new install-flang-libraries install-flang-headers`.
Commit: d88c1f94894ff568d1f5fa2dfc9219a9361d9932
https://github.com/llvm/llvm-project/commit/d88c1f94894ff568d1f5fa2dfc9219a9361d9932
Author: Alina Sbirlea <asbirlea at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/test/MC/ARM/pcrel-ldrd-same-section.s
Log Message:
-----------
[MC][ARM] Fix test.
Commit: 371fdbaa57c3eaeea0f99591ae9675ecaa0cd1ad
https://github.com/llvm/llvm-project/commit/371fdbaa57c3eaeea0f99591ae9675ecaa0cd1ad
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
Log Message:
-----------
[AMDGPU] Sign extend simm16 in setreg intrinsic (#77997)
We currently force users to use a negative contant in the intrinsic
call. Changing it zext would break existing programs, so just sign
extend an argument.
Commit: 093206bb7eddf53cf6e1ffe4c0ffc09d37785e27
https://github.com/llvm/llvm-project/commit/093206bb7eddf53cf6e1ffe4c0ffc09d37785e27
Author: Alexey Bataev <a.bataev at outlook.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
A llvm/test/Transforms/SLPVectorizer/X86/gep-nonconst-idx-transformed-to-const.ll
Log Message:
-----------
[SLP]Fix PR78298: Assertion `GEP->getNumIndices() == 1 &&
!isa<Constant>(GEPIdx)' failed.
The non-constant index might be folded to constant during earlier stages
of vectorization. Need to consider this option and filter out out GEP
with the constant indices from the candidates list.
Commit: 7850c94b86ac4889f4c792a487f4c0b0c5759a98
https://github.com/llvm/llvm-project/commit/7850c94b86ac4889f4c792a487f4c0b0c5759a98
Author: David Green <david.green at arm.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/MC/MCSymbol.h
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
M llvm/lib/CodeGen/SlotIndexes.cpp
M llvm/lib/ExecutionEngine/ExecutionEngine.cpp
M llvm/lib/MC/MCFragment.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
Log Message:
-----------
[NFC] sentinal -> sentinel
Commit: d6ee91b1100a3356506643da37cbd6891a663db9
https://github.com/llvm/llvm-project/commit/d6ee91b1100a3356506643da37cbd6891a663db9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
Log Message:
-----------
[X86] Add test case for Issue #77805
Commit: 9c4e7a159b1f2228ddf146c58c2478418cd63e86
https://github.com/llvm/llvm-project/commit/9c4e7a159b1f2228ddf146c58c2478418cd63e86
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
Log Message:
-----------
[OpenACC] Implement 'self' clause parsing on 'update'.
The update directive has its own version of 'self' that has a 'var-list'
instead of a 'condition' (like the serial/parallel/kernel/combined
constructs). This patch special cases it on 'update' to make sure we
parse this correctly.
Commit: fc64a7342c6cec1a3a1a62348990b912ac7dfaf0
https://github.com/llvm/llvm-project/commit/fc64a7342c6cec1a3a1a62348990b912ac7dfaf0
Author: Aart Bik <39774503+aartbik at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M .github/CODEOWNERS
Log Message:
-----------
[mlir][sparse][codeowners] add MLIR sparsifier team to codeowners (#78319)
Commit: 65ecbdf61f5a3fb53f05abc610b90a8671f93730
https://github.com/llvm/llvm-project/commit/65ecbdf61f5a3fb53f05abc610b90a8671f93730
Author: Yitzhak Mandelbaum <ymand at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/Value.cpp
M clang/unittests/Analysis/FlowSensitive/ValueTest.cpp
Log Message:
-----------
[clang][dataflow] Fix bug in `Value` comparison. (#76746)
Makes value equivalence require that the values have no properties,
except in
the case of equivalence by pointer equality (if the pointers are equal,
nothing
else is checked).
Fixes issue #76459.
Commit: e0443624b9b418cd2a1b26cac662885aedfb4977
https://github.com/llvm/llvm-project/commit/e0443624b9b418cd2a1b26cac662885aedfb4977
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/docs/ReleaseNotes/18.rst
M libcxx/docs/UsingLibcxx.rst
M libcxx/include/__config
M libcxx/test/libcxx/depr/enable_removed_cpp17_features.compile.pass.cpp
A libcxx/test/libcxx/depr/enable_removed_cpp17_features.deprecated.verify.cpp
A libcxx/test/libcxx/depr/enable_removed_cpp20_features.deprecated.verify.cpp
Log Message:
-----------
[libc++] Deprecate removed features macros. (#77879)
We discussed the removal of these enable-all macros in the libc++
monthly meeting and we agreed that we should deprecate these macros in
LLVM 18, and then remove them in LLVM 19 since they can silently enable
deprecated features that are implemented after the first release of the
macro.
This patch does the first part of this -- it deprecates the macro.
Note that the file
test/libcxx/depr/enable_removed_cpp20_features.compile.pass.cpp
does not exist so this file is not adapted. Since the feature is
deprecated and slated for removal soon the missing test is not
implemented.
Partly addresses: https://github.com/llvm/llvm-project/issues/75976
---------
Co-authored-by: Louis Dionne <ldionne.2 at gmail.com>
Commit: 34933d1872b5eefb94dbd30dce3c342db008ad1c
https://github.com/llvm/llvm-project/commit/34933d1872b5eefb94dbd30dce3c342db008ad1c
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/include/barrier
M libcxx/include/future
M libcxx/include/latch
M libcxx/include/semaphore
M libcxx/include/shared_mutex
M libcxx/include/stop_token
M libcxx/include/thread
Log Message:
-----------
[libc++] Improves _LIBCPP_HAS_NO_THREADS guards. (#76624)
Previously the header included several headers, possibly granularized
threading headers. This could lead to build errors when these headers
were incompatible with threading disabled.
Now test the guard before inclusion. This matches the pattern used for
no localization and no wide characters.
Fixes: https://github.com/llvm/llvm-project/issues/76620
Commit: 4a87db6b10a075849673247ded426504561a8a25
https://github.com/llvm/llvm-project/commit/4a87db6b10a075849673247ded426504561a8a25
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/include/__availability
M libcxx/include/ostream
M libcxx/src/ostream.cpp
M libcxx/test/libcxx/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_unicode.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/print.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/println.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_nonunicode.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_unicode.pass.cpp
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++][print] Enables it on Apple backdeployment. (#76293)
As suggested in #73262 this enable the stream printing on Apple
backdeployment targets. This omits the check whether the file is a
terminal. This is not entirely conforming, but the differences should be
minor and are typically not observable.
Fixes https://github.com/llvm/llvm-project/issues/75225
Commit: 8803112beedde4d7b7d396bea457085a754914f3
https://github.com/llvm/llvm-project/commit/8803112beedde4d7b7d396bea457085a754914f3
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/docs/UsingLibcxx.rst
Log Message:
-----------
[libc++][NFC] Add deprecated mention for _LIBCPP_ENABLE_CXX20_REMOVED_ALLOCATOR_MEMBERS in the docs
This was missed in the patch where I marked the macro as deprecated.
Commit: 127c390fc413f8f267b085b153e6d21f84c7886e
https://github.com/llvm/llvm-project/commit/127c390fc413f8f267b085b153e6d21f84c7886e
Author: Louis Dionne <ldionne.2 at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/include/libcxx.imp
M libcxx/utils/generate_iwyu_mapping.py
M libcxx/utils/libcxx/header_information.py
Log Message:
-----------
[libc++] Rewrite the IWYU generation (#78295)
This simplifies the IWYU generation script by treating everything as a
file, instead of dealing with directories and files separately.
This has the downside that the `libcxx.imp` file is a lot larger than it
used to be, however we now have the flexibility of mapping files under
detail directories to different public headers. For example, this allows
us to map <__fwd/subrange.h> to <ranges> but <__fwd/pair.h> to
<utility>.
This patch also adds basic validation to ensure that we never map a
header to a public header that doesn't exist. We may still be missing
some mappings or we may be mapping to incorrect headers, but we won't be
mapping to headers that downright don't exist.
Fixes #63346
Commit: 8d7bba0d5a8f024f44995adb9f3286c00b316689
https://github.com/llvm/llvm-project/commit/8d7bba0d5a8f024f44995adb9f3286c00b316689
Author: Petr Hosek <phosek at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
Log Message:
-----------
[CMake] Include riscv32-unknown-elf runtimes in Fuchsia toolchain (#78323)
This contains compiler-rt builtins and llvm-libc for baremetal use.
Differential Revision: https://reviews.llvm.org/D155337
Commit: 7e909d58d1862686375a0a71fd907151b109c2db
https://github.com/llvm/llvm-project/commit/7e909d58d1862686375a0a71fd907151b109c2db
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M .github/workflows/docs.yml
Log Message:
-----------
[libc++][CI] Fixes documentation builder. (#78327)
The documentation CI no longer builds. This is likely introduced by
8f90e6937a1fac80873bb2dab5f382c82ba1ba4e. This fixes the issue.
Commit: aa23e493f2b363982a472fe38caffc69d907402c
https://github.com/llvm/llvm-project/commit/aa23e493f2b363982a472fe38caffc69d907402c
Author: mmoadeli <mmoadeli at hotmail.co.uk>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
A llvm/test/CodeGen/NVPTX/shuffle-vec-undef-init.ll
Log Message:
-----------
[NVPTX] Fix generating permute bytes from register pair when the initial values are undefined (#74437)
When generating the permute bytes for the prmt instruction, the
existence of an undefined initial value initialises the int32 that holds
the mask with all 1's (0xFFFFFFFF). That initialization subsequently
leads to complications during the subsequent OR operation, leading to
inaccuracies in populating mask values for the following bytes.
Consequently, the final value persists as a constant -1, irrespective of
the actual mask values that succeed the initial set value.
Commit: ab398416a7932d9b85e216353b7c847189c1a597
https://github.com/llvm/llvm-project/commit/ab398416a7932d9b85e216353b7c847189c1a597
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libcxx/modules/std/memory.inc
Log Message:
-----------
[libc++][modules] Fixes RTTI build.
This was reviewed in https://github.com/llvm/llvm-project/pull/76246
Commit: 070738ba8894ed2c4ef02b07cfb7ce27d3d024ec
https://github.com/llvm/llvm-project/commit/070738ba8894ed2c4ef02b07cfb7ce27d3d024ec
Author: Teresa Johnson <tejohnson at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
Log Message:
-----------
[MemProf][NFC] Explicitly specify llvm version of function_ref (#77783)
As suggested in https://github.com/llvm/llvm-project/pull/75823, to
avoid confusion with std::function_ref, qualify all uses with llvm::
(we were already using the llvm version, but this avoids ambiguity).
Commit: 32dd5b20973bde1ef77fa3b84b9f85788a1a303a
https://github.com/llvm/llvm-project/commit/32dd5b20973bde1ef77fa3b84b9f85788a1a303a
Author: jimingham <jingham at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
Log Message:
-----------
Work around a bug in the interaction between newer dyld's and older simulator dyld's (#78004)
There's a bad interaction between the macOS 14 dyld and the "dyld_sim"
shim that comes from older (iOS 15) simulator downloads that results in
dyld reporting some modules twice in the return from the dyld callback
to list modules. The records were identical, but lldb wasn't happy with
seeing the duplicates...
Since it's not possible to load two different modules at the same
address, this change just picks the first instance of any entries that
have the same load address.
There really isn't a good way to test this patch.
Commit: 3973955282121cf97fb3b77c4bac0a89dcf82591
https://github.com/llvm/llvm-project/commit/3973955282121cf97fb3b77c4bac0a89dcf82591
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
Log Message:
-----------
[OpenACC] Implement 'reduction' clause parsing.
The 'reduction' clause takes a mandatory operator followed by a colon,
followed by a 'var-list'. This patch implements the parsing for the
'reduction' clause.
Commit: 16b238798250cb16ac78c710958b353cb45b11a0
https://github.com/llvm/llvm-project/commit/16b238798250cb16ac78c710958b353cb45b11a0
Author: Aiden Grossman <agrossman154 at yahoo.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp
Log Message:
-----------
[llvm-exegesis] Fix snippet value scaling (#77226)
Currently, BenchmarkRunner scales the per snippet counters by
multiplying the raw counter values by the number of instructions (casted
to a double) divided by the minimum number of instructions. This is
incorrect for the loop repetition mode for snippets that don't fit a
whole number of times into the minimum instruction count. For example,
with 3 instructions in the snippet and the minimum number of
instructions set to 4, the loop repetitor will execute a total of six
instructions, but BenchmarkRunner will scale the raw count by 3/4
instead of 3/6=1/2. This will also be incorrect for the duplicate
snippet repetitor after #77224.
This patch fixes this behavior by dividing the raw count by the ceiling
of the number of repetitions divided by the instruction count.
Commit: bbb3f9b1321176a012dac7d50da54b869a85e9bc
https://github.com/llvm/llvm-project/commit/bbb3f9b1321176a012dac7d50da54b869a85e9bc
Author: Pranav Kant <prka at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/test/MC/ARM/pcrel-vldr-same-section.s
Log Message:
-----------
[MC][ARM] Fix test
Similar to d88c1f94894ff568d1f5fa2dfc9219a9361d9932
Commit: 184784690dabba638730c2d365a5e9f4062317d3
https://github.com/llvm/llvm-project/commit/184784690dabba638730c2d365a5e9f4062317d3
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/MIR/BUILD.gn
Log Message:
-----------
[gn build] Manually port 8566cd61
Commit: 337b7715929909fd2bb55069ecb939cf23dbfe52
https://github.com/llvm/llvm-project/commit/337b7715929909fd2bb55069ecb939cf23dbfe52
Author: Nick Desaulniers <nickdesaulniers at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
A libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/utils/FPUtil/x86_long_double_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
R utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
Log Message:
-----------
Revert "[libc][NFC] Refactor FPBits and remove LongDoubleBits specialization (#78192)" (#78329)
This reverts commit fdbf255c96cb18bc1fb08fa7264446bcbbd5fbd0.
Causes build breakage on 32b arm (see reports:
https://github.com/llvm/llvm-project/pull/78192).
These are reproducible for the 32b arm baremetal target on x86 hosts as
well.
Commit: 4737959d91fab7673b1bb642f88658bb2a24d723
https://github.com/llvm/llvm-project/commit/4737959d91fab7673b1bb642f88658bb2a24d723
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/include/clang/AST/APNumericStorage.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/Expr.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
Log Message:
-----------
[AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (#78311)
EnumConstantDecl is allocated by the ASTContext allocator so the
destructor is never called.
This patch takes a similar approach to IntegerLiteral by using
APIntStorage to allocate large APSInts using the ASTContext allocator as
well.
The downside is that an additional heap allocation and copy of the data
needs to be made when calling getInitValue if the APSInt is large.
Fixes #78160.
Commit: 59a265311a072437232767c228263bea0c0074b5
https://github.com/llvm/llvm-project/commit/59a265311a072437232767c228263bea0c0074b5
Author: serbanu <serban.ungureanu1 at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/unittests/Format/ConfigParseTest.cpp
Log Message:
-----------
[clang-format] Add parse tests for SeparateDefinitionBlocks option (#78256)
Add config parse tests for SeparateDefinitionBlocks option.
Commit: f3d534c4251bb08ee210a49fcf721cefff7ded11
https://github.com/llvm/llvm-project/commit/f3d534c4251bb08ee210a49fcf721cefff7ded11
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
R clang/include/clang/AST/APNumericStorage.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/Expr.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
Log Message:
-----------
Revert "[AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (#78311)"
This reverts commit 4737959d91fab7673b1bb642f88658bb2a24d723.
Missed an lldb update.
Commit: 41b09bbe98fc8d5952beeeb34fcb07caeecfbdcb
https://github.com/llvm/llvm-project/commit/41b09bbe98fc8d5952beeeb34fcb07caeecfbdcb
Author: Charlie Barto <chbarto at microsoft.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M compiler-rt/lib/asan/asan_win.cpp
M compiler-rt/lib/interception/interception_win.cpp
Log Message:
-----------
[ASAN][sanitizers][win] Allow windows-asan to be built with /MDd and intercept functions from the debug runtimes. (#77840)
It turns out this works _mostly_ fine, even when mixing debug versions
of asan with programs built with the release runtime. Using /MT (or
/MTd) with a dynamically linked asan has never really worked that well,
and I am planning on opening a PR that will completely remove the
static-asan configuration for windows and make programs linked with the
static CRT/runtime work with the DLL version of asan. This is better
than the current situation because the static linked version of asan
doesn't work well on windows if there are multiple DLLs in the process
using it.
The check for building asan with only /MD or /MT has been removed. It
was in AsanDoesNotSupportStaticLinkage, but was checking for debug CRTs,
not static linkage. The kind of static linkage this function is supposed
to check for (on linux for example) doesn't really exist on windows.
Note: There is one outstanding issue with this approach, if you mix a
/MDd DLLs and /MD dlls in the same process then the "real" function
called by asan interceptors will be the same for calls from both
contexts, potentially screwing up things like errno. This only happens
if you mix /MD and /MDd in the same process, because otherwise asan
won't find functions from both runtimes to intercept. We are working on
a fix for this, and it mainly hits with the CRT functions exported from
both ucrtbase and ntdll.
This change is being upstreamed from Microsoft's fork.
Commit: 03abf7fe09bb13d387660bcd5abaf8257de2c152
https://github.com/llvm/llvm-project/commit/03abf7fe09bb13d387660bcd5abaf8257de2c152
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
Log Message:
-----------
[AMDGPU] Fix predicates for V_DOT instructions. (#78198)
Resolves AsmParser ambiguities, e.g., between V_DOT4C_I32_I8_dpp_vi and
V_DOT4C_I32_I8_dpp_gfx10. The latter is predicated with isGFX10Only
while the first has no subtarget generation predicates.
Part of <https://github.com/llvm/llvm-project/issues/69256>.
Commit: dda2ce82c2ec8a3b988636c6cebb76eb32b4de05
https://github.com/llvm/llvm-project/commit/dda2ce82c2ec8a3b988636c6cebb76eb32b4de05
Author: Yeoul Na <yeoul_na at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
A clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyImplPlans.rst
M clang/docs/index.rst
Log Message:
-----------
[BoundsSafety] Initial documentation for -fbounds-safety (#70749)
The document is mostly the exact copy of RFC: Enforcing Bounds Safety in
C, except some clarifications made over the PR review:
https://discourse.llvm.org/t/rfc-enforcing-bounds-safety-in-c-fbounds-safety/70854
Further changes and clarifications for the programming model will be
done as separate patches to make it easier to track history of changes.
Commit: 142f270c279f2576e4618fc0d1121181c7531fdf
https://github.com/llvm/llvm-project/commit/142f270c279f2576e4618fc0d1121181c7531fdf
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
A clang/include/clang/AST/APNumericStorage.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/Expr.h
M clang/lib/AST/Decl.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
Log Message:
-----------
Recommit "[AST] Use APIntStorage to fix memory leak in EnumConstantDecl. (#78311)"
With lldb build fix.
Original message:
EnumConstantDecl is allocated by the ASTContext allocator so the
destructor is never called.
This patch takes a similar approach to IntegerLiteral by using
APIntStorage to allocate large APSInts using the ASTContext allocator as
well.
The downside is that an additional heap allocation and copy of the data
needs to be made when calling getInitValue if the APSInt is large.
Fixes #78160.
Commit: ad50676055cf03fd4fecdda5736c7ac1a940231f
https://github.com/llvm/llvm-project/commit/ad50676055cf03fd4fecdda5736c7ac1a940231f
Author: Victor Mustya <victor.mustya at intel.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/IR/Instructions.cpp
M llvm/test/Transforms/InstCombine/fptrunc.ll
Log Message:
-----------
[InstCombine] Only fold bitcast(fptrunc) if destination type matches fptrunc result type. (#77046)
It's not enough to just make sure destination type is floating point,
because the following chain may be incorrectly optimized:
```LLVM
%trunc = fptrunc float %src to bfloat
%cast = bitcast bfloat %trunc to half
```
Before the fix, the instruction sequence mentioned above used to be
translated into single fptrunc instruction as follows:
```LLVM
%trunc = fptrunc float %src to half
```
Such transformation was semantically incorrect.
Commit: e1616ef9d742ebcc226451c4ca5ec2204c460840
https://github.com/llvm/llvm-project/commit/e1616ef9d742ebcc226451c4ca5ec2204c460840
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
M llvm/test/CodeGen/X86/basic-block-sections-clusters-error.ll
A llvm/test/CodeGen/X86/basic-block-sections-entryblock.ll
Log Message:
-----------
[BasicBlockSections] Always keep the entry block in the beginning of the function. (#74696)
BasicBlockSections must enforce placing the entry block at the beginning
of the function regardless of the basic block sections profile.
Commit: 6ba2c2bb804532e97180d548957bb231d994c8ff
https://github.com/llvm/llvm-project/commit/6ba2c2bb804532e97180d548957bb231d994c8ff
Author: Rahman Lavaee <rahmanl at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/unittests/Object/ELFObjectFileTest.cpp
Log Message:
-----------
[SHT_LLVM_BB_ADDR_MAP,NFC] Add SCOPED_TRACE for convenient mapping of failures to test cases. (#78335)
Although parameterized gtests are preferred for this, our tests are not
very straightforward. So I decided to add SCOPED_TRACE for different
test cases and the lambda checks as well.
Typical test failure message now looks like:
```
...llvm-project/llvm/unittests/Object/ELFObjectFileTest.cpp:737
Expected equality of these values:
*BBAddrMaps
Which is: { 32-byte object <11-11 01-00 00-00 00-00 C0-A9 FB-3E E4-55 00-00 D0-A9 FB-3E E4-55 00-00 D0-A9 FB-3E E4-55 00-00>, 32-byte object <22-22 02-00 00-00 00-00 F0-8E FB-3E E4-55 00-00 00-8F FB-3E E4-55 00-00 00-8F FB-3E E4-55 00-00> }
ExpectedResult
Which is: { 32-byte object <33-33 03-00 00-00 00-00 50-A7 FB-3E E4-55 00-00 60-A7 FB-3E E4-55 00-00 60-A7 FB-3E E4-55 00-00> }
Google Test trace:
...llvm-project/llvm/unittests/Object/ELFObjectFileTest.cpp:726: for TextSectionIndex: 1 and object yaml:
--- !ELF
FileHeader:
Class: ELFCLASS64
Data: ELFDATA2LSB
Type: ET_EXEC
Sections:
- Name: .llvm_bb_addr_map_1
Type: SHT_LLVM_BB_ADDR_MAP
Link: 1
Entries:
- Version: 2
Address: 0x11111
BBEntries:
- ID: 1
AddressOffset: 0x0
Size: 0x1
Metadata: 0x2
- Name: .llvm_bb_addr_map_2
Type: SHT_LLVM_BB_ADDR_MAP
Link: 1
Entries:
- Version: 2
Address: 0x22222
BBEntries:
- ID: 2
AddressOffset: 0x0
Size: 0x2
Metadata: 0x4
- Name: .llvm_bb_addr_map_3
Type: SHT_LLVM_BB_ADDR_MAP
Link: 2
Entries:
- Version: 1
Address: 0x33333
BBEntries:
- ID: 0
AddressOffset: 0x0
Size: 0x3
Metadata: 0x6
- Name: .llvm_bb_addr_map_4
Type: SHT_LLVM_BB_ADDR_MAP_V0
# Link: 0 (by default, can be overriden)
Entries:
- Version: 0
Address: 0x44444
BBEntries:
- ID: 0
AddressOffset: 0x0
Size: 0x4
Metadata: 0x18
...llvm-project/llvm/unittests/Object/ELFObjectFileTest.cpp:757: normal sections
```
Commit: 1b5f72c5ece4442ca29ced45f8bcb25ed0d57790
https://github.com/llvm/llvm-project/commit/1b5f72c5ece4442ca29ced45f8bcb25ed0d57790
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Utility/FileSpecList.h
A lldb/include/lldb/Utility/SupportFile.h
Log Message:
-----------
[lldb] Hoist SupportFile out of FileSpecList (NFC)
This hoists SupportFile out of FileSpecList. SupportFileList is still
implemented there as it's very similar to FileSpecList.
Commit: 00b6d032a22196bc14e4e30e413c040eb1b65da4
https://github.com/llvm/llvm-project/commit/00b6d032a22196bc14e4e30e413c040eb1b65da4
Author: Bill Wendling <5993918+bwendling at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/AttrDocs.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Sema/Sema.h
M clang/include/clang/Sema/TypoCorrection.h
M clang/lib/AST/ASTImporter.cpp
M clang/lib/AST/DeclBase.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGExpr.cpp
M clang/lib/CodeGen/CodeGenFunction.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaExpr.cpp
A clang/test/CodeGen/attr-counted-by.c
M clang/test/CodeGen/bounds-checking.c
M clang/test/Misc/pragma-attribute-supported-attributes-list.test
A clang/test/Sema/attr-counted-by.c
Log Message:
-----------
[Clang] Implement the 'counted_by' attribute (#76348)
The 'counted_by' attribute is used on flexible array members. The
argument for the attribute is the name of the field member holding the
count of elements in the flexible array. This information is used to
improve the results of the array bound sanitizer and the
'__builtin_dynamic_object_size' builtin. The 'count' field member must
be within the same non-anonymous, enclosing struct as the flexible array
member. For example:
```
struct bar;
struct foo {
int count;
struct inner {
struct {
int count; /* The 'count' referenced by 'counted_by' */
};
struct {
/* ... */
struct bar *array[] __attribute__((counted_by(count)));
};
} baz;
};
```
This example specifies that the flexible array member 'array' has the
number of elements allocated for it in 'count':
```
struct bar;
struct foo {
size_t count;
/* ... */
struct bar *array[] __attribute__((counted_by(count)));
};
```
This establishes a relationship between 'array' and 'count';
specifically that 'p->array' must have *at least* 'p->count' number of
elements available. It's the user's responsibility to ensure that this
relationship is maintained throughout changes to the structure.
In the following, the allocated array erroneously has fewer elements
than what's specified by 'p->count'. This would result in an
out-of-bounds access not not being detected:
```
struct foo *p;
void foo_alloc(size_t count) {
p = malloc(MAX(sizeof(struct foo),
offsetof(struct foo, array[0]) + count *
sizeof(struct bar *)));
p->count = count + 42;
}
```
The next example updates 'p->count', breaking the relationship
requirement that 'p->array' must have at least 'p->count' number of
elements available:
```
void use_foo(int index, int val) {
p->count += 42;
p->array[index] = val; /* The sanitizer can't properly check this access */
}
```
In this example, an update to 'p->count' maintains the relationship
requirement:
```
void use_foo(int index, int val) {
if (p->count == 0)
return;
--p->count;
p->array[index] = val;
}
```
Commit: 8947469ec1ad6d35b2feec0acc43d0d191514f0b
https://github.com/llvm/llvm-project/commit/8947469ec1ad6d35b2feec0acc43d0d191514f0b
Author: Chelsea Cassanova <chelsea_cassanova at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/test/API/functionalities/progress_reporting/TestTrimmedProgressReporting.py
Log Message:
-----------
[lldb][Progress] Fix test for trimmed progress reports (#78357)
The test TestTrimmedProgressReporting tests that progress reports are
being sent by listening for events with the titles of specific progress
reports. Commit f1ef910b removed the report for Apple DWARF indices
which was one of the reports being listened for in this test, so that
report is removed here as well.
That commit also now creates all progress reports with details so
reports string are prepended with the details count. This changes the
length of the trimmed progress report title string that's checked for
here so this commit changes the string to match as well.
This test was skipped on non-Apple platforms, but since the progress
report for Apple DWARF indices has been removed this commit removes that
decorator.
Commit: e9e3e9d23dd4e06ed5d9adb156ced4ab3a1f34bc
https://github.com/llvm/llvm-project/commit/e9e3e9d23dd4e06ed5d9adb156ced4ab3a1f34bc
Author: PiJoules <6019989+PiJoules at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
M llvm/lib/Target/RISCV/RISCVTargetObjectFile.h
M llvm/test/MC/ELF/rtti-proxy-gotpcrel.ll
Log Message:
-----------
[llvm] Indirect symbol replacement with GOTPCREL for aarch64 and risc… (#78003)
…v64 ELF
This is similar to https://github.com/llvm/llvm-project/pull/67754 but
adds support for ELF aarch64 and riscv64 now that GOTPCREL-equivalent
relocations have been added for those archs.
Commit: 894c22406f68af6574a62a40ec49e058344c324b
https://github.com/llvm/llvm-project/commit/894c22406f68af6574a62a40ec49e058344c324b
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/test/PCH/gch-probe.c
M llvm/include/llvm/BinaryFormat/Magic.h
M llvm/lib/BinaryFormat/Magic.cpp
M llvm/lib/Object/Binary.cpp
M llvm/lib/Object/ObjectFile.cpp
Log Message:
-----------
[clang][Driver] Don't ignore -gmodules .gch files (#77711)
A previous commit (82f75ed) made clang ignore .gch files that were not
Clang AST files. This broke `-gmodules`, which embeds the Clang AST into
an object file containing debug info.
This changes the probing to detect any file format recognized by
`llvm::identify_magic()` as potentially containing a Clang AST.
Previous PR: https://github.com/llvm/llvm-project/pull/69204
Commit: 06328d55c39b73fae3611bb076ee8d4a75f3c989
https://github.com/llvm/llvm-project/commit/06328d55c39b73fae3611bb076ee8d4a75f3c989
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
Log Message:
-----------
[JITLink][AArch32] In warning output add decimal value for CPUArch and missing newline
Commit: 539c557a7fe050b19ba08dc1bf7f65cb2a56337f
https://github.com/llvm/llvm-project/commit/539c557a7fe050b19ba08dc1bf7f65cb2a56337f
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
A llvm/test/ExecutionEngine/JITLink/AArch32/ELF_relocations_arm.s
A llvm/test/ExecutionEngine/JITLink/AArch32/ELF_relocations_data.s
A llvm/test/ExecutionEngine/JITLink/AArch32/ELF_relocations_thumb.s
R llvm/test/ExecutionEngine/JITLink/AArch32/ELF_static_arm_reloc.s
R llvm/test/ExecutionEngine/JITLink/AArch32/ELF_static_data_reloc.s
R llvm/test/ExecutionEngine/JITLink/AArch32/ELF_static_thumb_reloc.s
A llvm/test/ExecutionEngine/JITLink/AArch32/ELF_stubs_thumb.s
R llvm/test/ExecutionEngine/JITLink/AArch32/ELF_thumb_stubs.s
Log Message:
-----------
[JITLink][AArch32] Streamline file-names of tests (NFC)
All other backends use the full term "relocations". Also, sorting by type (relocations/stubs/etc.) before CPU states (arm/thumb/other) makes it easier to filter in LIT.
Commit: 079706df0225902054cf7b7a0388a60db59ac426
https://github.com/llvm/llvm-project/commit/079706df0225902054cf7b7a0388a60db59ac426
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/test/ExecutionEngine/JITLink/AArch32/ELF_stubs_thumb.s
Log Message:
-----------
[JITLink][AArch32] Fix typos in Thumb stubs test (NFC)
Commit: a979797dc2f460003e2b923b4ee6bbd977253d98
https://github.com/llvm/llvm-project/commit/a979797dc2f460003e2b923b4ee6bbd977253d98
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
M llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
Log Message:
-----------
[JITLink][AArch32] Rename stubs flavor Thumbv7 to v7 (NFC)
Commit: 9c607e77eae75f0f9152eb3e6ba2a69616aba4fa
https://github.com/llvm/llvm-project/commit/9c607e77eae75f0f9152eb3e6ba2a69616aba4fa
Author: Stefan Gränitz <stefan.graenitz at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
M llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
Log Message:
-----------
[JITLink][AArch32] Refactor StubsManager (NFC)
Commit: 854aa9112df253bcad4db6f21ea9b2fbca4ed83e
https://github.com/llvm/llvm-project/commit/854aa9112df253bcad4db6f21ea9b2fbca4ed83e
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Utility/FileSpecList.h
M lldb/source/Utility/FileSpecList.cpp
Log Message:
-----------
[lldb] Store SupportFile as shared_ptr (NFC)
Commit: a43a4a5329fbb4c5bedddb9cbbe89d3659422be3
https://github.com/llvm/llvm-project/commit/a43a4a5329fbb4c5bedddb9cbbe89d3659422be3
Author: Alex Langford <alangford at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/test/API/macosx/rosetta/Makefile
Log Message:
-----------
[lldb] Build the TestRosetta.py executable with system stdlib (#78370)
This is a speculative fix for TestRosetta.py which is currently failing
on Green Dragon.
TestRosetta just makes sure we can debug an x86_64 process on Apple
Silicon. However, we're failing to build the x86_64 test binary. The
linker is failing with some warnings about libc++ and libunwind being
build for arm64 while the target binary is x86_64. I'm going to try
building with the system standard libraries instead of the just-built
ones to workaround it.
Commit: 7d3466b5c30878c5e014949ebf1dc44bb2160995
https://github.com/llvm/llvm-project/commit/7d3466b5c30878c5e014949ebf1dc44bb2160995
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/MachO.def
M llvm/include/llvm/TargetParser/Triple.h
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TextAPI/Platform.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
[llvm] Introduce XROS platform (#77707)
Accepts but otherwise ignores visionOS/XROS target triples as Darwin
based platform.
https://developer.apple.com/documentation/visionos
Commit: 25c7c231149813692db1dbfc348d2df87ecc5307
https://github.com/llvm/llvm-project/commit/25c7c231149813692db1dbfc348d2df87ecc5307
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
Log Message:
-----------
[llvm][MC] silence xros platform warnings, NFC
Commit: 32382bb8329a0931456ab0c60e351cf3a18ab6f3
https://github.com/llvm/llvm-project/commit/32382bb8329a0931456ab0c60e351cf3a18ab6f3
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Symbol/LineEntry.h
M lldb/source/Symbol/LineEntry.cpp
Log Message:
-----------
[lldb] Remove unused LineEntry ctor (NFC)
Commit: f3190c78ec6f3db77defd28d1b25aba0ef4834f6
https://github.com/llvm/llvm-project/commit/f3190c78ec6f3db77defd28d1b25aba0ef4834f6
Author: Florian Mayer <fmayer at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
Log Message:
-----------
Revert "[AMDGPU] Sign extend simm16 in setreg intrinsic" (#78372)
Reverts llvm/llvm-project#77997
Broke UBSan bots.
Commit: c3f96acb41ef20a1f84715b1b6fb39e916f9aac8
https://github.com/llvm/llvm-project/commit/c3f96acb41ef20a1f84715b1b6fb39e916f9aac8
Author: Zixu Wang <9819235+zixu-w at users.noreply.github.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/test/Driver/fdefine-target-os-macros.c
Log Message:
-----------
Revert "[Fix] Disable fdefine-target-os-macros for now" (#78353)
https://github.com/llvm/llvm-test-suite/pull/65 fixed the
llvm-test-suite errors. Reapply the change to enable
`fdefine-target-os-macros` by default for Darwin targets.
This reverts commit 63be986f612c175559efffed9daebcb944fa5cea.
Commit: b6f922fbf5e983122271aa12acb33f6172046d4d
https://github.com/llvm/llvm-project/commit/b6f922fbf5e983122271aa12acb33f6172046d4d
Author: Davide Italiano <davidino at fb.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/test/CodeGen/debug-info-codeview-unnamed.c
M clang/test/CodeGen/debug-info-unused-types.c
M clang/test/CodeGen/debug-info-unused-types.cpp
M clang/test/CodeGenCXX/debug-info-access.cpp
M clang/test/CodeGenCXX/debug-info-anon-union-vars.cpp
M clang/test/CodeGenCXX/debug-info-codeview-unnamed.cpp
M clang/test/CodeGenCXX/debug-info-gline-tables-only-codeview.cpp
M clang/test/CodeGenCXX/debug-lambda-this.cpp
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
R llvm/test/Bitcode/clone-local-types.ll
M llvm/test/Bitcode/upgrade-cu-locals.ll
M llvm/test/Bitcode/upgrade-cu-locals.ll.bc
R llvm/test/DebugInfo/Generic/inlined-local-type.ll
R llvm/test/DebugInfo/Generic/lexical-block-retained-types.ll
R llvm/test/DebugInfo/Generic/lexical-block-types.ll
A llvm/test/DebugInfo/Generic/split-dwarf-local-import.ll
A llvm/test/DebugInfo/Generic/split-dwarf-local-import2.ll
A llvm/test/DebugInfo/Generic/split-dwarf-local-import3.ll
M llvm/test/DebugInfo/Generic/verifier-invalid-disubprogram.ll
R llvm/test/DebugInfo/X86/local-type-as-template-parameter.ll
M llvm/test/DebugInfo/X86/set.ll
R llvm/test/DebugInfo/X86/split-dwarf-local-import.ll
R llvm/test/DebugInfo/X86/split-dwarf-local-import2.ll
R llvm/test/DebugInfo/X86/split-dwarf-local-import3.ll
M llvm/unittests/Transforms/Utils/CloningTest.cpp
Log Message:
-----------
Revert "[CloneFunction][DebugInfo] Avoid cloning DILocalVariables of inlined functions (#75385)"
This reverts commit fc6faa1113e9069f41b5500db051210af0eea843.
Commit: 0266f414f624ebd74f8607ebd3ac94bbb93b0ebb
https://github.com/llvm/llvm-project/commit/0266f414f624ebd74f8607ebd3ac94bbb93b0ebb
Author: Alexander Richardson <alexrichardson at google.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M compiler-rt/lib/builtins/CMakeLists.txt
Log Message:
-----------
[compiler-rt] Drop COMPILER_RT_BUILD_CRT workaround (#78331)
This variable was explicitly removed from the cache to ease transition
from existing build directories but that breaks passing
COMPILER_RT_BUILD_CRT=OFF on the command line. I was surprised to see
the CRT builds being run for my builtins-only build config (I noticed
because one of the tests was failing despite having `REQUIRES: crt`).
If I pass `-DCOMPILER_RT_BUILD_CRT=OFF` to cmake and add some prints
around the `unset` statement it shows the following:
```
-- before unset(): COMPILER_RT_BUILD_CRT=OFF
-- after unset: COMPILER_RT_BUILD_CRT=
-- after cmake_dependent_option COMPILER_RT_BUILD_CRT=ON
```
Drop this temporary workaround now that over 6 months have passed.
Commit: a4cd99ea8736eda2b8b4de34453f55008bcf9c30
https://github.com/llvm/llvm-project/commit/a4cd99ea8736eda2b8b4de34453f55008bcf9c30
Author: jimingham <jingham at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/source/Core/ModuleList.cpp
A lldb/test/API/functionalities/executable_first/Makefile
A lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
A lldb/test/API/functionalities/executable_first/b.cpp
A lldb/test/API/functionalities/executable_first/main.cpp
Log Message:
-----------
Ensure that the executable module is ModuleList[0] (#78360)
We claim in a couple places that the zeroth element of the module list
for a target is the main executable, but we don't actually enforce that
in the ModuleList class. As we saw, for instance, in
32dd5b20973bde1ef77fa3b84b9f85788a1a303a
it's not all that hard to get this to be off. This patch ensures that
the first object file of type Executable added to it is moved to the
front of the ModuleList. I also added a test for this.
In the normal course of operation, where the executable is added first,
this only adds a check for whether the first element in the module list
is an executable. If that's true, we just append as normal.
Note, the code in Target::GetExecutableModule doesn't actually agree
that the zeroth element must be the executable, it instead returns the
first Module of type Executable. But I can't tell whether that was a
change in intention or just working around the bug that we don't always
maintain this ordering. But given we've said this in scripting as well
as internally, I think we shouldn't change our minds about this.
Commit: 29b5f8f977af9b09aa8f56152baca04cf8750981
https://github.com/llvm/llvm-project/commit/29b5f8f977af9b09aa8f56152baca04cf8750981
Author: Younan Zhang <zyn7109 at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/test/SemaTemplate/concepts.cpp
Log Message:
-----------
[Clang][Sema] Extract ellipsis location from CXXFoldExpr for reattaching constraints on NTTPs (#78080)
We build up a `CXXFoldExpr` for immediately declared constraints as per
C++20 [temp.param]/4. This is done by
`formImmediatelyDeclaredConstraint` where an `EllipsisLoc` is essential
to determine whether this is a pack.
On the other hand, when attempting to instantiate a class template,
member templates might not be instantiated immediately, so we leave them
intact. For function templates with NTTPs, we reattach constraints if
possible so that they can be evaluated later. To properly form that, we
attempted to extract an ellipsis location if the param per se was a
parameter pack. Unfortunately, for the following NTTP case, we seemingly
failed to handle:
```cpp
template <Constraint auto... Pack>
void member();
```
The NTTPD Pack is neither an `ExpandedParameterPack` nor a
`PackExpansion` (its type does not expand anything). As a result, we end
up losing track of the constraints on packs, although we have them
inside the associated `CXXFoldExpr`.
This patch fixes that by extracting the ellipsis location out of the
previous constraint expression. Closes
https://github.com/llvm/llvm-project/issues/63837.
Commit: 705c5b80ace9d6fb1b9d1129ca1529d6645f1f24
https://github.com/llvm/llvm-project/commit/705c5b80ace9d6fb1b9d1129ca1529d6645f1f24
Author: jimingham <jingham at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
Log Message:
-----------
Add the Linux "you can use this binary" bits to run_to_source_breakpoint (#78377)
Follow-on to a4cd99ea8736eda2b8b4de34453f55008bcf9c30 - I forgot you
have to add ANY shared library you want to use to extra_images...
Commit: 46a395d8c41f6009a7fbae51f408c3c6ea2399d3
https://github.com/llvm/llvm-project/commit/46a395d8c41f6009a7fbae51f408c3c6ea2399d3
Author: antangelo <contact at antangelo.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CXX/dcl.decl/dcl.decl.general/p4-20.cpp
M clang/test/SemaTemplate/GH71595.cpp
M clang/test/SemaTemplate/concepts-friends.cpp
Log Message:
-----------
[clang] Emit error for invalid friend functions under [temp.friend]p9 (#78083)
Emits an error for friend FunctionDecls that either:
* are not templates and have a requires clause
* are templates, and have a constrained parameter that depends on a
template parameter from an enclosing template
and are not a definition.
For a non-template friend function with a requires clause, if the
function is not templated then the original error message indicating
that such a function is disallowed is shown instead, as the function
will still be rejected if a definition is added.
Commit: 9745c13ca82538d30a04db7da40d3c4cd9f7f13c
https://github.com/llvm/llvm-project/commit/9745c13ca82538d30a04db7da40d3c4cd9f7f13c
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/test/CodeGen/X86/bfloat.ll
Log Message:
-----------
[X86][BF16] Improve float -> bfloat lowering under AVX512BF16 and AVXNECONVERT (#78042)
Commit: 8934b10642664c0824f45f115b2a0afcb56a5e5f
https://github.com/llvm/llvm-project/commit/8934b10642664c0824f45f115b2a0afcb56a5e5f
Author: Jacques Pienaar <jpienaar at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/include/mlir/Conversion/ArithCommon/AttrToLLVMConverter.h
M mlir/include/mlir/Dialect/Arith/IR/ArithBase.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOps.td
M mlir/include/mlir/Dialect/Arith/IR/ArithOpsInterfaces.td
M mlir/include/mlir/Dialect/LLVMIR/LLVMInterfaces.td
M mlir/lib/Conversion/ArithCommon/AttrToLLVMConverter.cpp
M mlir/lib/Conversion/ArithToLLVM/ArithToLLVM.cpp
M mlir/lib/Conversion/ArithToSPIRV/ArithToSPIRV.cpp
M mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td
M mlir/lib/Dialect/Arith/IR/ArithOps.cpp
M mlir/test/Conversion/ArithToLLVM/arith-to-llvm.mlir
M mlir/test/Conversion/ArithToSPIRV/arith-to-spirv.mlir
M mlir/test/Dialect/Arith/ops.mlir
A mlir/test/python/dialects/arith_llvm.py
M mlir/test/python/ir/diagnostic_handler.py
Log Message:
-----------
[mlir][arith] Add overflow flags support to arith ops (#78376)
Add overflow flags support to the following ops:
* `arith.addi`
* `arith.subi`
* `arith.muli`
Example of new syntax:
```
%res = arith.addi %arg1, %arg2 overflow<nsw> : i64
```
Similar to existing LLVM dialect syntax
```
%res = llvm.add %arg1, %arg2 overflow<nsw> : i64
```
Tablegen canonicalization patterns updated to always drop flags, proper
support with tests will be added later.
Updated LLVMIR translation as part of this commit as it currenly written
in a way that it will crash when new attributes added to arith ops
otherwise.
Also lower `arith` overflow flags to corresponding SPIR-V op decorations
Discussion
https://discourse.llvm.org/t/rfc-integer-overflow-flags-support-in-arith-dialect/76025
This effectively rolls forward #77211, #77700 and #77714 while adding a
test to ensure the Python usage is not broken. More follow up needed but
unrelated to the core change here. The changes here are minimal and just
correspond to "textual namespacing" ODS side, no C++ or Python changes
were needed.
---------
---------
Co-authored-by: Ivan Butygin <ivan.butygin at gmail.com>, Yi Wu <yi.wu2 at arm.com>
Commit: 84bdee2875da364be7eb2144b1ae530f6a05f0e2
https://github.com/llvm/llvm-project/commit/84bdee2875da364be7eb2144b1ae530f6a05f0e2
Author: Ami-zhang <zhanglimin at loongson.cn>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/test/MC/LoongArch/Basic/Float/d-arith.s
M llvm/test/MC/LoongArch/Basic/Float/f-arith.s
M llvm/test/MC/LoongArch/Basic/Integer/atomic.s
M llvm/test/MC/LoongArch/lasx/frecip.s
M llvm/test/MC/LoongArch/lasx/frsqrt.s
M llvm/test/MC/LoongArch/lsx/frecip.s
M llvm/test/MC/LoongArch/lsx/frsqrt.s
Log Message:
-----------
[LoongArch] Add LoongArch V1.1 instructions definitions and MC tests (#78238)
LoongArch V1.1 instrucions include floating-point approximate reciprocal
instructions and atomic instrucions. And add testcases for these
instrucions meanwhile.
Commit: 8d6e82d501cda1946c7d99658241033d78676e95
https://github.com/llvm/llvm-project/commit/8d6e82d501cda1946c7d99658241033d78676e95
Author: Phoebe Wang <phoebe.wang at intel.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/test/CodeGen/X86/avx512-kconstraints-att_inline_asm.c
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/test/CodeGen/X86/pr41678.ll
Log Message:
-----------
[X86] Use vXi1 for `k` constraint in inline asm (#77733)
Fixes #77172
Commit: 8371cdca12b1510d9ac6a1d13d573ced6c05402f
https://github.com/llvm/llvm-project/commit/8371cdca12b1510d9ac6a1d13d573ced6c05402f
Author: Pranav Kant <prka at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel
Log Message:
-----------
Disable ConstraintSystemTest for now
as it started failing after https://github.com/llvm/llvm-project/commit/8e514c572e44eda237417236b4c92176dfce9cd9
Above commit enables llvm::DebugFlag which is a global variable.
Commit: 0a64367a72f1634321f5051221f05f2f364bd882
https://github.com/llvm/llvm-project/commit/0a64367a72f1634321f5051221f05f2f364bd882
Author: YunQiang Su <wzssyqa at gmail.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M compiler-rt/lib/interception/interception.h
M compiler-rt/lib/sanitizer_common/sanitizer_asm.h
Log Message:
-----------
Sanitizer/MIPS: Use $t9 for preemptible function call (#76894)
Currently, almost all of the shared libraries of MIPS, rely on $t9
to get the address of current function, instead of PCREL instructions,
even on MIPSr6. So we have to set $t9 properly.
To get the address of preemptible function, we need the help of GOT.
MIPS/O32 has .cpload, which can help to generate 3 instructions to get GOT.
For __mips64, we can get GOT by:
lui $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)))))
daddu $t8, $t8, $t9
daddiu $t8, $t8, %hi(%neg(%gp_rel(SANITIZER_STRINGIFY(TRAMPOLINE(func)))))
And then get the address of __interceptor_func, and jump to it
ld $t9, %got_disp(_interceptor" SANITIZER_STRINGIFY(func) ")($t8)
jr $t9
Fixes #74047
Co-authored-by: YunQiang Su <yunqiang.su at cipunited.com>
Commit: 3e0d71cdf4a406c6a1de825cf69d889d97ede46b
https://github.com/llvm/llvm-project/commit/3e0d71cdf4a406c6a1de825cf69d889d97ede46b
Author: h-vetinari <h.vetinari at gmx.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/docs/CommandGuide/clang.rst
M clang/docs/UsersManual.rst
Log Message:
-----------
[clang-cl] document correct defaults for `-fms-compatibility-version` / `-fmsc-version` (#76418)
The UserManual states wrongly (AFAICT) that these default are not being
defined for clang-cl, whereas further up the opposite is stated:
https://github.com/llvm/llvm-project/blob/c86fe3ee0b92934f5d18394d9a0cdc1d3f0eef64/clang/docs/UsersManual.rst#L3375-L3382
I've chosen to follow that wording, as it's the latest related update.
CC @RIscRIpt who recently touched this in
b3e6ff331925dde24a4707452d657da0fdf7f588
CC @AaronBallman who cared about this, c.f.
8fc0dcf036bf199b2af2e10a4f81215dbd706daf
Commit: 933c25e558e6d0d8766d024a329d003a8d4c1162
https://github.com/llvm/llvm-project/commit/933c25e558e6d0d8766d024a329d003a8d4c1162
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Symbol/LineEntry.h
M lldb/include/lldb/Utility/FileSpecList.h
M lldb/include/lldb/Utility/SupportFile.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/Breakpoint/BreakpointResolver.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Symbol/LineEntry.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Target/ThreadPlanStepOverRange.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
Log Message:
-----------
[lldb] Store SupportFile in LineEntry (NFC) (#77999)
Store a SupportFile, rather than a FileSpec, in LineEntry. This commit
works towards having the SourceManageroperate on SupportFiles so that it
can (1) validate the Checksum and (2) materialize the content of inline
source information.
Commit: 4e64159c866446ed7f5783649f8f5699f84bb1a6
https://github.com/llvm/llvm-project/commit/4e64159c866446ed7f5783649f8f5699f84bb1a6
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/DeclCXX.h
M clang/lib/AST/DeclCXX.cpp
M clang/test/CXX/drs/dr20xx.cpp
M clang/test/CXX/drs/dr25xx.cpp
M clang/test/SemaCXX/literal-type.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[Clang] Implement CWG2598: Union of non-literal types (#78195)
A union is considered a literal type unless it has no non-literal
member.
This resolves CWG2096 (which makes unions with literal members literal)
and CWG2598 (empty unions are literal types).
Fixes #77924
Commit: ff9fcc74a356b8542e5ac782426c9d4c817143f3
https://github.com/llvm/llvm-project/commit/ff9fcc74a356b8542e5ac782426c9d4c817143f3
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/include/lldb/Symbol/CompileUnit.h
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Symbol/CompileUnit.cpp
Log Message:
-----------
[lldb] Store SupportFile in CompileUnit (NFC)
Store a SupportFile, rather than a FileSpec, in CompileUnit. This commit
works towards having the SourceManager operate on SupportFiles so that
it can (1) validate the Checksum and (2) materialize the content of
inline source information.
Commit: 5aea6ba8f5f06e06887fe5c5c8740895907f6540
https://github.com/llvm/llvm-project/commit/5aea6ba8f5f06e06887fe5c5c8740895907f6540
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/source/Core/Module.cpp
Log Message:
-----------
[lldb] Fix trailing whitespace & formatting in Core/Module.cpp (NFC)
I have my editor configured to remove trailing whitespace and every time
I touch this file I end up with a bunch of clang-format changes to lines
that were modified because of it. Nobody likes trailing whitespace so
this cleans up the file.
Commit: 9e9907f1cfa424366fba58d9520f9305b537cec9
https://github.com/llvm/llvm-project/commit/9e9907f1cfa424366fba58d9520f9305b537cec9
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-br.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fadd.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fconstant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fma.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmad.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmaxnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum-ieee.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fminnum.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fract.f64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-i1-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-icmp.s64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-intrinsic-trunc.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-load-flat.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
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M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
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M llvm/test/CodeGen/AMDGPU/fold-operands-remove-m0-redef.mir
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M llvm/test/CodeGen/AMDGPU/fold-readlane.mir
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M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
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M llvm/test/CodeGen/AMDGPU/merge-image-sample-gfx12.mir
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M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
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M llvm/test/CodeGen/AMDGPU/mfma-bf16-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
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M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx940.ll
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M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
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M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
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M llvm/test/CodeGen/AMDGPU/mul.i16.ll
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M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
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M llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm-gfx90a.mir
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M llvm/test/CodeGen/AMDGPU/rv7x0_count3.ll
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M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
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M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
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M llvm/test/CodeGen/AMDGPU/select64.ll
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M llvm/test/CodeGen/AMDGPU/setcc64.ll
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M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/sminmax.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill192.mir
M llvm/test/CodeGen/AMDGPU/spill224.mir
M llvm/test/CodeGen/AMDGPU/spill288.mir
M llvm/test/CodeGen/AMDGPU/spill320.mir
M llvm/test/CodeGen/AMDGPU/spill352.mir
M llvm/test/CodeGen/AMDGPU/spill384.mir
M llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/split-smrd.ll
M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-global.ll
M llvm/test/CodeGen/AMDGPU/store-hi16.ll
M llvm/test/CodeGen/AMDGPU/store-local.ll
M llvm/test/CodeGen/AMDGPU/store-private.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/store_typed.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
M llvm/test/CodeGen/AMDGPU/structurize.ll
M llvm/test/CodeGen/AMDGPU/structurize1.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
M llvm/test/CodeGen/AMDGPU/subvector-test.mir
M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
M llvm/test/CodeGen/AMDGPU/swizzle-export.ll
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/target-cpu.ll
M llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
M llvm/test/CodeGen/AMDGPU/texture-input-merge.ll
M llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/undef-build-vector.ll
M llvm/test/CodeGen/AMDGPU/undef-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
M llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
M llvm/test/CodeGen/AMDGPU/unpack-half.ll
M llvm/test/CodeGen/AMDGPU/unsupported-atomics.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cc.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/urem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v1024.ll
M llvm/test/CodeGen/AMDGPU/v1i64-kernel-arg.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane16var-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll
M llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
M llvm/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
M llvm/test/CodeGen/AMDGPU/vmem-vcc-hazard.mir
M llvm/test/CodeGen/AMDGPU/vni8-across-blocks.ll
M llvm/test/CodeGen/AMDGPU/vop-shrink-frame-index.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink-non-ssa.mir
M llvm/test/CodeGen/AMDGPU/vop-shrink.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.ll
M llvm/test/CodeGen/AMDGPU/vopc_dpp.mir
M llvm/test/CodeGen/AMDGPU/vopd-combine.mir
M llvm/test/CodeGen/AMDGPU/vopd-src2acc-delay.mir
M llvm/test/CodeGen/AMDGPU/vselect.ll
M llvm/test/CodeGen/AMDGPU/vselect64.ll
M llvm/test/CodeGen/AMDGPU/vtx-fetch-branch.ll
M llvm/test/CodeGen/AMDGPU/vtx-schedule.ll
M llvm/test/CodeGen/AMDGPU/wait.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-agpr.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-back-edge-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-bvh.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-irreducible.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-loop-single-basic-block.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-meta-instructions.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-overflow.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-preexisting.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-skip-meta.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vinterp.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmcnt-loop.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vmem-waw.mir
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.mir
M llvm/test/CodeGen/AMDGPU/waitcnt.mir
M llvm/test/CodeGen/AMDGPU/waterfall_kills_scc.ll
M llvm/test/CodeGen/AMDGPU/wave32.ll
M llvm/test/CodeGen/AMDGPU/while-break.ll
M llvm/test/CodeGen/AMDGPU/widen-vselect-and-mask.ll
M llvm/test/CodeGen/AMDGPU/wmma-hazards.mir
M llvm/test/CodeGen/AMDGPU/wmma_modifiers.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_32.ll
M llvm/test/CodeGen/AMDGPU/wmma_multiple_64.ll
M llvm/test/CodeGen/AMDGPU/wqm-gfx11.ll
M llvm/test/CodeGen/AMDGPU/wqm-terminators.mir
M llvm/test/CodeGen/AMDGPU/wqm.ll
M llvm/test/CodeGen/AMDGPU/wqm.mir
M llvm/test/CodeGen/AMDGPU/write-register-vgpr-into-sgpr.ll
M llvm/test/CodeGen/AMDGPU/write_register.ll
M llvm/test/CodeGen/AMDGPU/wrong-transalu-pos-fix.ll
M llvm/test/CodeGen/AMDGPU/xfail.r600.bitcast.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/xnack-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/xnor.ll
M llvm/test/CodeGen/AMDGPU/xor.ll
M llvm/test/CodeGen/AMDGPU/xor3-i1-const.ll
M llvm/test/CodeGen/AMDGPU/zero_extend.ll
M llvm/test/CodeGen/AMDGPU/zext-divergence-driven-isel.ll
M llvm/test/CodeGen/AMDGPU/zext-i64-bit-operand.ll
M llvm/test/CodeGen/AMDGPU/zext-lid.ll
M llvm/test/CodeGen/MIR/AMDGPU/empty-custom-regmask.mir
M llvm/test/CodeGen/MIR/AMDGPU/expected-target-index-name.mir
M llvm/test/CodeGen/MIR/AMDGPU/invalid-target-index-operand.mir
M llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline-ir.mir
M llvm/test/CodeGen/MIR/AMDGPU/llc-target-cpu-attr-from-cmdline.mir
M llvm/test/CodeGen/MIR/AMDGPU/long-branch-reg-all-sgpr-used.ll
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error1.mir
M llvm/test/CodeGen/MIR/AMDGPU/machine-function-info-register-parse-error2.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-frame-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-frame-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-scratch-rsrc-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-parse-error-stack-ptr-offset-reg.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-scratch-rsrc-reg-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mfi-stack-ptr-offset-reg-class.mir
M llvm/test/CodeGen/MIR/AMDGPU/mir-canon-multi.mir
M llvm/test/CodeGen/MIR/AMDGPU/mircanon-memoperands.mir
M llvm/test/CodeGen/MIR/AMDGPU/parse-order-reserved-regs.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id-assert.mir
M llvm/test/CodeGen/MIR/AMDGPU/stack-id.mir
M llvm/test/CodeGen/MIR/AMDGPU/subreg-def-is-not-ssa.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-flags.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-index-operands.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
M llvm/test/MachineVerifier/test_g_intrinsic.mir
M llvm/test/MachineVerifier/test_g_intrinsic_w_side_effects.mir
M llvm/test/MachineVerifier/verifier-pseudo-terminators.mir
M llvm/test/Transforms/InferAddressSpaces/AMDGPU/flat_atomic.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-invalid-ptr-extend.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-postinc-pos-addrspace.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void-inseltpoison.ll
M llvm/test/Transforms/LoopStrengthReduce/AMDGPU/lsr-void.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-address-space.ll
M llvm/test/Transforms/LoopVectorize/runtime-check-readonly-address-space.ll
M llvm/test/tools/llvm-objdump/AMDGPU/elf-disassemble-symbolize-operands.yaml
Log Message:
-----------
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
Similar to 806761a7629df268c8aed49657aeccffa6bca449.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
Commit: 46a929f0a077186034d5692b013730578a2a2d36
https://github.com/llvm/llvm-project/commit/46a929f0a077186034d5692b013730578a2a2d36
Author: Danila Malyutin <danilaml at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/X86/fminimum-fmaximum.ll
Log Message:
-----------
[SelectionDAG] Fix isKnownNeverZeroFloat for vectors (#78308)
Return true iff all of vector elements are constant AND not zero
Fixes #77805
Previously, it'd return `true` (as in - the value is known to be never
zero) for any build_vector/splat_vector with non-constant elements.
Commit: 00d6232d6b331f7d82823c508684be81239a2897
https://github.com/llvm/llvm-project/commit/00d6232d6b331f7d82823c508684be81239a2897
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
Log Message:
-----------
[RISCV][GISel] Don't create generic virtual registers in selectSHXADDOp/selectSHXADD_UWOp. (#78396)
Since we're creating target specific instructions, I think we should be
creating registers with the GPR register class.
Commit: 069e9b44954cad452eb6be4d1e3b924e7dda8de0
https://github.com/llvm/llvm-project/commit/069e9b44954cad452eb6be4d1e3b924e7dda8de0
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/RISCV.cpp
M clang/test/CodeGen/RISCV/riscv-func-attr-target.c
Log Message:
-----------
[RISCV] Overwrite cpu target features for full arch string in target attribute (#77426)
This patch reworks RISCVTargetInfo::initFeatureMap to fix the issue
described
in
https://github.com/llvm/llvm-project/pull/74889#pullrequestreview-1773445559
(and is an alternative to #75804)
When a full arch string is specified, a "full" list of extensions is now
passed
after the __RISCV_TargetAttrNeedOverride marker feature, which includes
any
negative features that disable ISA extensions.
In initFeatureMap, there are now two code paths:
1. If the arch string was overriden, use the "full" list of override
features,
only adding back any non-isa features that were specified.
Using the full list of positive and negative features will mean that the
target-cpu will have no effect on the final arch, e.g.
__attribute__((target("arch=rv64i"))) with -mcpu=sifive-x280 will have
the
features for rv64i, not a mix of both.
2. Otherwise, parse and *append* the list of implied features. By
appending, we
turn back on any features that might have been disabled by a negative
extension, i.e. this handles the case fixed in #74889.
Commit: e8af89ef3de45b3058041388267d728c4ade16e8
https://github.com/llvm/llvm-project/commit/e8af89ef3de45b3058041388267d728c4ade16e8
Author: Robin Caloudis <53619127+robincaloudis at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/LibASTMatchersTutorial.rst
Log Message:
-----------
[clang][docs] Improve "Obtaining Clang" section (#71313)
## Why
The documentation is written relatively to `clang-llvm`, not the root
repository directory. However, some steps in the documentation are
relative to the repository root, which is not correct.
## What
Documentation steps have been modified to make them correct and outdated
ones were updated. Some details:
* Correct paths in documentation
* Change `bootstrap.py` -> `configure.py` since bootstraping Ninja has
[slightly
changed](https://github.com/ninja-build/ninja/tree/master?tab=readme-ov-file#python)
Commit: d89a0a65947eb0c7bce733ee76991f900209d139
https://github.com/llvm/llvm-project/commit/d89a0a65947eb0c7bce733ee76991f900209d139
Author: Aviad Cohen <aviadcohen7 at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Tosa/IR/TosaOps.cpp
M mlir/lib/Dialect/Tosa/Transforms/TosaFolders.cpp
M mlir/test/Dialect/Tosa/canonicalize.mlir
Log Message:
-----------
[mlir][Tosa]: Add folder to ReciprocalOp of splat constant inputs (#78137)
Commit: d06ae33ec32122bb526fb35025c1f0cf979f1090
https://github.com/llvm/llvm-project/commit/d06ae33ec32122bb526fb35025c1f0cf979f1090
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M .github/workflows/libcxx-build-and-test.yaml
M libcxx/CMakeLists.txt
M libcxx/cmake/caches/Generic-cxx26.cmake
M libcxx/cmake/caches/Generic-hardening-mode-extensive.cmake
M libcxx/cmake/caches/Generic-no-exceptions.cmake
M libcxx/cmake/caches/Generic-no-experimental.cmake
M libcxx/cmake/caches/Generic-no-filesystem.cmake
M libcxx/cmake/caches/Generic-no-localization.cmake
M libcxx/cmake/caches/Generic-no-random_device.cmake
M libcxx/cmake/caches/Generic-no-threads.cmake
M libcxx/cmake/caches/Generic-no-tzdb.cmake
M libcxx/cmake/caches/Generic-no-unicode.cmake
M libcxx/cmake/caches/Generic-no-wide-characters.cmake
M libcxx/docs/Modules.rst
M libcxx/docs/ReleaseNotes/18.rst
M libcxx/modules/CMakeLists.txt
R libcxx/modules/CMakeLists.txt.in
M libcxx/test/CMakeLists.txt
M libcxx/test/configs/cmake-bridge.cfg.in
R libcxx/test/lit.local.cfg
M libcxx/test/std/modules/std.compat.pass.cpp
M libcxx/test/std/modules/std.pass.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/buildkite-pipeline.yml
M libcxx/utils/ci/run-buildbot
M libcxx/utils/libcxx/test/features.py
M libcxx/utils/libcxx/test/modules.py
Log Message:
-----------
[libc++][modules] Removes module testing. (#76083)
This removes the entire modules testing infrastructure.
The current infrastructure uses CMake to generate the std and std.compat
module. This requires quite a bit of plumbing and uses CMake. Since
CMake introduced module support in CMake 3.26, modules have a higher
CMake requirement than the rest of the LLVM project. (The LLVM project
requires 3.20.) The main motivation for this approach was how libc++
generated its modules. Every header had its own module partition. This
was changed to improve performance and now only two modules remain. The
code to build these can be manually crafted.
A followup patch will reenable testing modules, using a different
approach.
Commit: 57ca74843586c9a93c425036c5538aae0a2cfa60
https://github.com/llvm/llvm-project/commit/57ca74843586c9a93c425036c5538aae0a2cfa60
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/docs/TestingLibcxx.rst
M libcxx/test/libcxx/module_std.gen.py
M libcxx/test/libcxx/module_std_compat.gen.py
A libcxx/test/libcxx/selftest/modules/no-modules.sh.cpp
A libcxx/test/libcxx/selftest/modules/std-and-std.compat-module.sh.cpp
A libcxx/test/libcxx/selftest/modules/std-module.sh.cpp
A libcxx/test/libcxx/selftest/modules/std.compat-module.sh.cpp
M libcxx/test/std/modules/std.compat.pass.cpp
M libcxx/test/std/modules/std.pass.cpp
M libcxx/utils/libcxx/test/config.py
M libcxx/utils/libcxx/test/features.py
M libcxx/utils/libcxx/test/format.py
M libcxx/utils/libcxx/test/modules.py
Log Message:
-----------
[libc++][modules] Adds module testing. (#76246)
This adds a new module test infrastructure. This requires tagging tests
using modules. The test runner uses this information to determine the
compiler flags needed to build and use the module.
Currently modules are build per test, which allows testing them for
tests with ADDITIONAL_COMPILE_FLAGS. At the moment only 4 tests use
modules. Therefore the performance penalty is not measurable. If in the
future more tests use modules it would be good to measure the overhead
and determine whether it's acceptable.
Commit: e6ac33b9369252b616625195bffc9ed6eb92cb52
https://github.com/llvm/llvm-project/commit/e6ac33b9369252b616625195bffc9ed6eb92cb52
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/test/tools/clang_tidy_checks/CMakeLists.txt
M libcxx/utils/libcxx/test/features.py
Log Message:
-----------
[libc++][modules] Increase clang-tidy version used. (#76268)
As suggested in #71438 we should use
export import std;
in the std.compat module.
Testing this locally failed when building with the clang-tidy-17 plugin.
The std module was considered corrupt in the test
libcxx/test/libcxx/module_std_compat.gen.py
however the test
libcxx/test/libcxx/module_std.gen.py
passed. Both test generated identical std.pcm files. Using the
clang-tidy-18 plugin solves the issue.
Commit: 020ea3e8d1075ab4a388ecd0d6e7a9d4cd415392
https://github.com/llvm/llvm-project/commit/020ea3e8d1075ab4a388ecd0d6e7a9d4cd415392
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/.clang-tidy
M libcxx/include/__atomic/is_always_lock_free.h
M libcxx/include/locale
Log Message:
-----------
[libc++] Clang-tidy enable modernize-use-nullptr. (#76659)
Clang-tidy 18 no longer has false positives with the spaceship operator.
Note that I'm quite sure there are more occurrences in our headers that
are not caught.
Commit: fb79f80bf6bb7d70d0446894d8c531d584012adf
https://github.com/llvm/llvm-project/commit/fb79f80bf6bb7d70d0446894d8c531d584012adf
Author: Mark de Wever <koraq at xs4all.nl>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
Log Message:
-----------
[libc++][modules] Fixes clang-tidy exports. (#76288)
As suggested in #71438 we should use
export import std;
in the std.compat module.
Using this exports some named declarations from functions and records,
adding them to the global namespace. Clang correctly does not export
these and it's an issue in the declaration filtering. Declarations in
function or record context are not considered a global named
declaration.
Commit: 2b3cdd69f7fa8f84513390fff06d0a9c28126717
https://github.com/llvm/llvm-project/commit/2b3cdd69f7fa8f84513390fff06d0a9c28126717
Author: Tacet <advenam.tacet at trailofbits.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/include/vector
Log Message:
-----------
[ASan][libc++][NFC] refactor vector annotations arguments (#78322)
This commit simplifies ASan helper functions in `std::vector` by
removing arguments which can be calculated later.
Short term it improves readability of helper functions in `std::vector`.
Long term it aims to help with a bigger refactor of container
annotations.
Commit: d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7
https://github.com/llvm/llvm-project/commit/d4cb5d9f2ba636b0049fc5791d378e224e3a3ae7
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/X86.cpp
M clang/test/CodeGen/X86/inline-asm-constraints.c
M clang/test/Sema/inline-asm-validate-x86.c
M llvm/docs/LangRef.rst
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
A llvm/test/CodeGen/X86/inline-asm-Ws-constraint-error.ll
A llvm/test/CodeGen/X86/inline-asm-Ws-constraint.ll
Log Message:
-----------
[X86] Add "Ws" constraint and "p" modifier for symbolic address/label reference (#77886)
Printing the raw symbol is useful in inline asm (e.g. getting the C++
mangled name, referencing a symbol in a custom way while ensuring it is
not optimized out even if internal). Similar constraints are available
in other targets (e.g. "S" for aarch64/riscv, "Cs" for m68k).
```
namespace ns { extern int var, a[4]; }
void foo() {
asm(".pushsection .xxx,\"aw\"; .dc.a %p0; .popsection" :: "Ws"(&ns::var));
asm(".reloc ., BFD_RELOC_NONE, %p0" :: "Ws"(&ns::a[3]));
}
```
Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105576
Commit: cbb46d94e771b1961faf03371de4a893e044979a
https://github.com/llvm/llvm-project/commit/cbb46d94e771b1961faf03371de4a893e044979a
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
Log Message:
-----------
[RISCV] Add run line for code size in rvv load/store cost model test. NFC
This illustrates #78352. There are other tests for gathers/scatters and masked
load/stores which likely have the same issue, but I've left them out for now
since they don't seem to be affected by fixing RISCVTTIImpl::getMemoryOpCost.
Commit: 54d81936393758fff8982aa4f4f997f4d9062828
https://github.com/llvm/llvm-project/commit/54d81936393758fff8982aa4f4f997f4d9062828
Author: Jason Molenda <jmolenda at apple.com>
Date: 2024-01-16 (Tue, 16 Jan 2024)
Changed paths:
M lldb/source/Target/Process.cpp
Log Message:
-----------
Return high address masks correctly in Process (#78379)
In https://reviews.llvm.org/D151292 I added the ability to track address
masks separately for high and low memory addresses, a capability of
AArch64. I did my testing with manual address mask settings (via
target.process.highmem-virtual-addressable-bits) but didn't have a real
corefile that included this metadata and required it.
My intention is that when the high address mask isn't specified, by the
user (via the setting) or the Process plugin, we fall back to using the
low address mask. The low and high address mask is the same for almost
all environments.
But the patch I wrote never uses the Process plugin high address mask if
it was set, e.g. from corefile metadata. This patch corrects that.
I also have an old patch in Phabractor that was approved to add
FixAddress methods to SBProcess; I need to pick that patch up and finish
it (I wanted to add an enum to specify which mask is being requested
iirc), so I can do address masks tests in API tests.
rdar://120926000
Commit: da0755f7b7ccb08c8819125bc7b75e0129e4be42
https://github.com/llvm/llvm-project/commit/da0755f7b7ccb08c8819125bc7b75e0129e4be42
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
A llvm/test/CodeGen/RISCV/spill-fill-fold.ll
Log Message:
-----------
[RISCV][test] Test showing missed optimisation for spills/fills of GPR<->FPR moves
The fmv can be removed through appropriate logic in
RISCVInstrInfo::foldMemoryOperandImpl.
Commit: 55172b7005a6f972272f6d79f2b0d15063bc1b1c
https://github.com/llvm/llvm-project/commit/55172b7005a6f972272f6d79f2b0d15063bc1b1c
Author: Dávid Ferenc Szabó <30732159+dfszabo at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
Log Message:
-----------
[GlobalISel] Improve combines for extend operation by taking hint ins… (#74125)
…tructions into account
Hint instructions like G_ASSERT_ZEXT cann be viewed as a copy. Including
this fact into the combiner allows the match more patterns involving
such instructions.
Commit: 5f57ad85a1a7c46eb43eee3c7d93b11d8fd7fcfa
https://github.com/llvm/llvm-project/commit/5f57ad85a1a7c46eb43eee3c7d93b11d8fd7fcfa
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/test/Analysis/BasicAA/inttoptr_constexpr.ll
Log Message:
-----------
[BasicAA] Remove incorrect rule about constant pointers (#76815)
BasicAA currently says that any Constant cannot alias an identified
local object. This is not correct if the local object escaped, as it's
possible to create a pointer to the escaped object using an inttoptr
constant expression base.
To compensate for this, make sure that inttoptr constant expressions are
treated as escape sources, just like inttoptr instructions. This ensures
that the optimization can still be applied if the local object is
non-escaping. This is sufficient to still optimize the original
motivating case from c53e2ecf0296a55d3c33c19fb70a3aa7f81f2732.
Fixes https://github.com/llvm/llvm-project/issues/76789.
Commit: cde780c18f8cde22ffd377bf6bcc098c52640f00
https://github.com/llvm/llvm-project/commit/cde780c18f8cde22ffd377bf6bcc098c52640f00
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
A llvm/test/CodeGen/X86/dag-combine-counter.ll
Log Message:
-----------
[DAGCombine] Add debug counter (#78259)
Add a debug counter for DAGCombine. This can help with bisecting which
DAG combine introduced a miscompile.
Commit: 435bcea83bd5fc3e4195fc811d89b2de0163d8e5
https://github.com/llvm/llvm-project/commit/435bcea83bd5fc3e4195fc811d89b2de0163d8e5
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
A llvm/test/CodeGen/AArch64/GlobalISel/counter-fallback.ll
Log Message:
-----------
[GISel] Add debug counter to force sdag fallback (#78257)
Add a debug counter that allows forcing an sdag fallback after a certain
number of functions.
The intended use-case is to bisect which function gets miscompiled by
global isel using `-debug-counter=globalisel-count=N` (in cases where
sdag doesn't also miscompile it, of course).
The "falling back" debug line is printed unconditionally, because using
`-debug-only` is usually too spammy for the intended purpose.
Commit: 34b106789ac2b3a0b8728e003dc63224a1d008fb
https://github.com/llvm/llvm-project/commit/34b106789ac2b3a0b8728e003dc63224a1d008fb
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/AsmParser/LLParser.cpp
A llvm/test/Assembler/implicit-intrinsic-declaration-invalid.ll
A llvm/test/Assembler/implicit-intrinsic-declaration.ll
Log Message:
-----------
[AsmParser] Implicitly declare intrinsics (#78251)
We currently require that all referenced globals have an explicit
declaration or definition in the IR. For intrinsics, this requirement is
redundant, because they cannot be called indirectly (including "direct"
calls with mismatched function type). The function type used in the call
directly determines the function type of the intrinsic declaration.
Relax this requirement, and implicitly declare any intrinsics that do
not have an explicit declaration. This will remove a common annoyance
when writing tests and alive2 proofs.
(I also plan to introduce a mode where declarations for all missing
symbols will be automatically added, to make working with incomplete IR
easier -- but that will be behind a default-disabled flag.)
Commit: 75f232181a2b9c9bd85823f88b2d63559c592556
https://github.com/llvm/llvm-project/commit/75f232181a2b9c9bd85823f88b2d63559c592556
Author: Craig Hesling <craig at hesling.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/bindings/python/README.txt
M clang/bindings/python/clang/cindex.py
Log Message:
-----------
[libclang/python] Bump minimum compatibility to Python 3.6 (#77228)
Remove Python 2 support and clean up code that conditions based on
version.
Issue #76664.
Commit: 588802a6708d8d3116331d975eb80eba7cfdae24
https://github.com/llvm/llvm-project/commit/588802a6708d8d3116331d975eb80eba7cfdae24
Author: Craig Hesling <craig at hesling.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M .github/workflows/libclang-python-tests.yml
M .github/workflows/llvm-project-tests.yml
Log Message:
-----------
[GitHub] Add python 3.7 to libclang python test (#77219)
This enables the libclang python binding test to check
the oldest version of Python supported in addition
to the normal python version.
It is important to check this for issue #76664, since
many new mainstream python type annotation features
and best practices are not compatible with older
versions of python.
Additionally, frustration around ever increasing
platform dependencies and versions has been raised.
This will help ensure that python maintains reasonable
backwards compatibility.
Adding this additional build step will increase the
run time, but this should always be minimal, since
the additional libclang compilation should see 100%
cache hit rate.
Issue #76664.
Fixes #76601.
Commit: baa39b789bbcf3c597945e6794a02c8e32ccbbd5
https://github.com/llvm/llvm-project/commit/baa39b789bbcf3c597945e6794a02c8e32ccbbd5
Author: Alex Zinenko <zinenko at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/Linalg/TransformOps/LinalgTransformOps.td
M mlir/include/mlir/Dialect/SCF/TransformOps/SCFTransformOps.td
M mlir/include/mlir/Dialect/Transform/IR/TransformOps.td
Log Message:
-----------
[mlir] fix wording in transform dialect docs
The wording "fails silently" has been sometimes used to indicate that a
silenceable failure was emitted by the operation. The meaning is exactly
the opposite: silenceable failure is _not_ silent unless silenced.
Commit: 94da2b21ee3f2baed729333ec8bbf96f92c1fa84
https://github.com/llvm/llvm-project/commit/94da2b21ee3f2baed729333ec8bbf96f92c1fa84
Author: Konstantin Varlamov <varconsteq at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/.clang-tidy
M libcxx/include/__atomic/is_always_lock_free.h
M libcxx/include/locale
Log Message:
-----------
Revert "[libc++] Clang-tidy enable modernize-use-nullptr. (#76659)" (#78409)
This reverts commit 020ea3e8d1075ab4a388ecd0d6e7a9d4cd415392.
This seems to break `test/libcxx/clang_tidy.gen.py/regex.sh.cpp` (in
C++03 mode for some reason):
```
2024-01-17T07:32:22.1759374Z # RUN: at line 12
2024-01-17T07:32:22.1773919Z clang-tidy-18 /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/test/libcxx/clang_tidy.gen.py/regex.sh.cpp --warnings-as-errors=* -header-filter=.* --config-file=/home/runner/_work/llvm-project/llvm-project/libcxx/.clang-tidy -- -Wweak-vtables -nostdinc++ -I /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1 -I /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1 -I /home/runner/_work/llvm-project/llvm-project/libcxx/test/support -std=c++03 -Werror -Wall -Wctad-maybe-unsupported -Wextra -Wshadow -Wundef -Wunused-template -Wno-unused-command-line-argument -Wno-attributes -Wno-pessimizing-move -Wno-noexcept-type -Wno-atomic-alignment -Wno-reserved-module-identifier -Wdeprecated-copy -Wdeprecated-copy-dtor -Wno-user-defined-literals -Wno-tautological-compare -Wsign-compare -Wunused-variable -Wunused-parameter -Wunreachable-code -Wno-unused-local-typedef -Wno-local-type-template-args -Wno-c++11-extensions -Wno-unknown-pragmas -Wno-pass-failed -Wno-mismatched-new-delete -Wno-redundant-move -Wno-self-move -D_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER -D_LIBCPP_ENABLE_EXPERIMENTAL -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_NONE -Werror=thread-safety -Wuser-defined-warnings -fno-modules
2024-01-17T07:32:22.1803227Z # executed command: clang-tidy-18 /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/test/libcxx/clang_tidy.gen.py/regex.sh.cpp '--warnings-as-errors=*' '-header-filter=.*' --config-file=/home/runner/_work/llvm-project/llvm-project/libcxx/.clang-tidy -- -Wweak-vtables -nostdinc++ -I /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1 -I /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1 -I /home/runner/_work/llvm-project/llvm-project/libcxx/test/support -std=c++03 -Werror -Wall -Wctad-maybe-unsupported -Wextra -Wshadow -Wundef -Wunused-template -Wno-unused-command-line-argument -Wno-attributes -Wno-pessimizing-move -Wno-noexcept-type -Wno-atomic-alignment -Wno-reserved-module-identifier -Wdeprecated-copy -Wdeprecated-copy-dtor -Wno-user-defined-literals -Wno-tautological-compare -Wsign-compare -Wunused-variable -Wunused-parameter -Wunreachable-code -Wno-unused-local-typedef -Wno-local-type-template-args -Wno-c++11-extensions -Wno-unknown-pragmas -Wno-pass-failed -Wno-mismatched-new-delete -Wno-redundant-move -Wno-self-move -D_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER -D_LIBCPP_ENABLE_EXPERIMENTAL -D_LIBCPP_HARDENING_MODE=_LIBCPP_HARDENING_MODE_NONE -Werror=thread-safety -Wuser-defined-warnings -fno-modules
2024-01-17T07:32:22.1817757Z # .---command stdout------------
2024-01-17T07:32:22.1820160Z # | /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1/__iterator/iterator_traits.h:124:50: error: use nullptr [modernize-use-nullptr,-warnings-as-errors]
2024-01-17T07:32:22.1822498Z # | 124 | static const bool value = decltype(__test<_Tp>(0, 0, 0, 0, 0))::value;
2024-01-17T07:32:22.1823337Z # | | ^
2024-01-17T07:32:22.1824052Z # | | nullptr
2024-01-17T07:32:22.1826651Z # | /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1/__iterator/iterator_traits.h:124:53: error: use nullptr [modernize-use-nullptr,-warnings-as-errors]
2024-01-17T07:32:22.1829325Z # | 124 | static const bool value = decltype(__test<_Tp>(0, 0, 0, 0, 0))::value;
2024-01-17T07:32:22.1831137Z # | | ^
2024-01-17T07:32:22.1831963Z # | | nullptr
2024-01-17T07:32:22.1834149Z # | /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1/__iterator/iterator_traits.h:124:56: error: use nullptr [modernize-use-nullptr,-warnings-as-errors]
2024-01-17T07:32:22.1848711Z # | 124 | static const bool value = decltype(__test<_Tp>(0, 0, 0, 0, 0))::value;
2024-01-17T07:32:22.1849506Z # | | ^
2024-01-17T07:32:22.1849997Z # | | nullptr
2024-01-17T07:32:22.1851528Z # | /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1/__iterator/iterator_traits.h:124:59: error: use nullptr [modernize-use-nullptr,-warnings-as-errors]
2024-01-17T07:32:22.1853391Z # | 124 | static const bool value = decltype(__test<_Tp>(0, 0, 0, 0, 0))::value;
2024-01-17T07:32:22.1854277Z # | | ^
2024-01-17T07:32:22.1854841Z # | | nullptr
2024-01-17T07:32:22.1856314Z # | /home/runner/_work/llvm-project/llvm-project/build/generic-cxx03/include/c++/v1/__iterator/iterator_traits.h:124:62: error: use nullptr [modernize-use-nullptr,-warnings-as-errors]
2024-01-17T07:32:22.1857768Z # | 124 | static const bool value = decltype(__test<_Tp>(0, 0, 0, 0, 0))::value;
2024-01-17T07:32:22.1858493Z # | | ^
2024-01-17T07:32:22.1858998Z # | | nullptr
2024-01-17T07:32:22.1859503Z # `-----------------------------
2024-01-17T07:32:22.1859900Z # .---command stderr------------
2024-01-17T07:32:22.1860259Z # | 43 warnings generated.
2024-01-17T07:32:22.1860710Z # | Suppressed 33 warnings (33 in non-user code).
2024-01-17T07:32:22.1861809Z # | Use -header-filter=.* to display errors from all non-system headers. Use -system-headers to display errors from system headers as well.
2024-01-17T07:32:22.1862750Z # | 5 warnings treated as errors
2024-01-17T07:32:22.1863229Z # `-----------------------------
2024-01-17T07:32:22.1863622Z # error: command failed with exit status: 1
```
(see
https://github.com/llvm/llvm-project/actions/runs/7552394884/job/20561192096)
Commit: 4426a1b7593a6e15caa09006d2446c95c19b5193
https://github.com/llvm/llvm-project/commit/4426a1b7593a6e15caa09006d2446c95c19b5193
Author: Tanmay <tnmysachan at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/test/Transforms/InstCombine/log-pow.ll
Log Message:
-----------
[InstCombine] Add log-pow simplification for FP exponent edge case. (#76641)
Fixes https://github.com/llvm/llvm-project/issues/76549
The cause of the optimization miss was -
1. `optimizePow` converting almost integer FP exponents to integer, and
turning `pow` to `powi`.
2. `optimizeLog` not accepting `Intrinsic::powi` as a target.
This patch converts constantInt back to constantFP where applicable and
adds a test.
Commit: 53a3c738a95ec654b0b2196cdbd454a8d6d1be0e
https://github.com/llvm/llvm-project/commit/53a3c738a95ec654b0b2196cdbd454a8d6d1be0e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
Log Message:
-----------
AMDGPU: Remove fixed fixme from a test
Commit: 92289db82fb2334593e21995bb140b4bc95926e3
https://github.com/llvm/llvm-project/commit/92289db82fb2334593e21995bb140b4bc95926e3
Author: Alexandros Lamprineas <alexandros.lamprineas at arm.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/VectorUtils.h
A llvm/include/llvm/IR/VFABIDemangler.h
M llvm/include/llvm/Transforms/Utils/ModuleUtils.h
M llvm/lib/Analysis/CMakeLists.txt
R llvm/lib/Analysis/VFABIDemangling.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/IR/CMakeLists.txt
A llvm/lib/IR/VFABIDemangler.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/Transforms/Utils/InjectTLIMappings.cpp
M llvm/lib/Transforms/Utils/ModuleUtils.cpp
M llvm/test/Transforms/LoopVectorize/AArch64/scalable-call.ll
A llvm/test/Verifier/vector-function-abi-variant.ll
M llvm/tools/vfabi-demangle-fuzzer/vfabi-demangler-fuzzer.cpp
M llvm/unittests/Analysis/CMakeLists.txt
R llvm/unittests/Analysis/VectorFunctionABITest.cpp
M llvm/unittests/IR/CMakeLists.txt
A llvm/unittests/IR/VFABIDemanglerTest.cpp
M llvm/unittests/Transforms/Utils/CMakeLists.txt
R llvm/unittests/Transforms/Utils/VFABIUtils.cpp
M llvm/utils/gn/secondary/llvm/lib/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Analysis/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
M llvm/utils/gn/secondary/llvm/unittests/Transforms/Utils/BUILD.gn
Log Message:
-----------
[VFABI] Move the Vector ABI demangling utility to LLVMCore. (#77513)
This fixes #71892 allowing us to check magled names in the IR verifier.
Commit: 7f7bbb9b441eb4311419be051de4cc8e3cd3ab3c
https://github.com/llvm/llvm-project/commit/7f7bbb9b441eb4311419be051de4cc8e3cd3ab3c
Author: Anatoly Trosinenko <atrosinenko at accesssoftek.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[AArch64] Use parseArchExtension function. NFC (#78158)
Commit: 57b50ef0174b6fdf7b554c4ae2691e2fa4f78f96
https://github.com/llvm/llvm-project/commit/57b50ef0174b6fdf7b554c4ae2691e2fa4f78f96
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
[AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode. (#71556)
Substitute with zero-extended to i64 ballot.i32 intrinsic.
Commit: 5fcf907b34355980f77d7665a175b05fea7a6b7b
https://github.com/llvm/llvm-project/commit/5fcf907b34355980f77d7665a175b05fea7a6b7b
Author: Matthias Springer <me at m-sp.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp
M flang/lib/Optimizer/Transforms/AffineDemotion.cpp
M flang/lib/Optimizer/Transforms/AffinePromotion.cpp
M flang/lib/Optimizer/Transforms/ExternalNameConversion.cpp
M mlir/docs/PatternRewriter.md
M mlir/examples/standalone/lib/Standalone/StandalonePasses.cpp
M mlir/examples/toy/Ch5/mlir/LowerToAffineLoops.cpp
M mlir/examples/toy/Ch6/mlir/LowerToAffineLoops.cpp
M mlir/examples/toy/Ch7/mlir/LowerToAffineLoops.cpp
M mlir/include/mlir/IR/PatternMatch.h
M mlir/include/mlir/Transforms/DialectConversion.h
M mlir/lib/Conversion/ArmSMEToLLVM/ArmSMEToLLVM.cpp
M mlir/lib/Conversion/GPUCommon/GPUToLLVMConversion.cpp
M mlir/lib/Conversion/OpenACCToSCF/OpenACCToSCF.cpp
M mlir/lib/Conversion/VectorToSCF/VectorToSCF.cpp
M mlir/lib/Dialect/Affine/IR/AffineOps.cpp
M mlir/lib/Dialect/Affine/Transforms/DecomposeAffineOps.cpp
M mlir/lib/Dialect/ArmSME/Transforms/TileAllocation.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeForLLVMExport.cpp
M mlir/lib/Dialect/ArmSVE/Transforms/LegalizeVectorStorage.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizableOpInterface.cpp
M mlir/lib/Dialect/Bufferization/IR/BufferizationOps.cpp
M mlir/lib/Dialect/Bufferization/Transforms/BufferDeallocationSimplification.cpp
M mlir/lib/Dialect/ControlFlow/IR/ControlFlowOps.cpp
M mlir/lib/Dialect/Func/Transforms/DecomposeCallGraphTypes.cpp
M mlir/lib/Dialect/Func/Transforms/FuncConversions.cpp
M mlir/lib/Dialect/Func/Transforms/OneToNFuncConversions.cpp
M mlir/lib/Dialect/GPU/IR/GPUDialect.cpp
M mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp
M mlir/lib/Dialect/LLVMIR/Transforms/TypeConsistency.cpp
M mlir/lib/Dialect/Linalg/TransformOps/LinalgTransformOps.cpp
M mlir/lib/Dialect/Linalg/Transforms/ConvertToDestinationStyle.cpp
M mlir/lib/Dialect/Linalg/Transforms/Detensorize.cpp
M mlir/lib/Dialect/Linalg/Transforms/ElementwiseOpFusion.cpp
M mlir/lib/Dialect/Linalg/Transforms/EliminateEmptyTensors.cpp
M mlir/lib/Dialect/Linalg/Transforms/EraseUnusedOperandsAndResults.cpp
M mlir/lib/Dialect/Linalg/Transforms/HoistPadding.cpp
M mlir/lib/Dialect/Linalg/Transforms/Interchange.cpp
M mlir/lib/Dialect/Linalg/Transforms/Split.cpp
M mlir/lib/Dialect/Linalg/Transforms/Tiling.cpp
M mlir/lib/Dialect/Linalg/Transforms/Vectorization.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp
M mlir/lib/Dialect/MemRef/IR/MemRefOps.cpp
M mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp
M mlir/lib/Dialect/MemRef/Transforms/IndependenceTransforms.cpp
M mlir/lib/Dialect/MemRef/Transforms/MultiBuffer.cpp
M mlir/lib/Dialect/NVGPU/Transforms/MmaSyncTF32Transform.cpp
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
M mlir/lib/Dialect/SCF/IR/SCF.cpp
M mlir/lib/Dialect/SCF/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/SCF/Transforms/ForToWhile.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopCanonicalization.cpp
M mlir/lib/Dialect/SCF/Transforms/LoopSpecialization.cpp
M mlir/lib/Dialect/SCF/Transforms/OneToNTypeConversion.cpp
M mlir/lib/Dialect/SCF/Transforms/StructuralTypeConversions.cpp
M mlir/lib/Dialect/SCF/Transforms/TileUsingInterface.cpp
M mlir/lib/Dialect/SPIRV/Transforms/DecorateCompositeTypeLayoutPass.cpp
M mlir/lib/Dialect/SPIRV/Transforms/LowerABIAttributesPass.cpp
M mlir/lib/Dialect/SparseTensor/IR/SparseTensorInterfaces.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseReinterpretMap.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/SparseVectorization.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp
M mlir/lib/Dialect/SparseTensor/Transforms/Utils/LoopEmitter.cpp
M mlir/lib/Dialect/Tensor/IR/TensorOps.cpp
M mlir/lib/Dialect/Tosa/IR/TosaCanonicalizations.cpp
M mlir/lib/Dialect/Vector/IR/VectorOps.cpp
M mlir/lib/Dialect/Vector/Transforms/BufferizableOpInterfaceImpl.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorDistribute.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransferSplitRewritePatterns.cpp
M mlir/lib/Dialect/Vector/Transforms/VectorTransforms.cpp
M mlir/lib/IR/PatternMatch.cpp
M mlir/lib/Transforms/Mem2Reg.cpp
M mlir/lib/Transforms/Utils/CommutativityUtils.cpp
M mlir/lib/Transforms/Utils/DialectConversion.cpp
M mlir/test/lib/Dialect/Test/TestPatterns.cpp
Log Message:
-----------
[mlir][IR] Rename "update root" to "modify op" in rewriter API (#78260)
This commit renames 4 pattern rewriter API functions:
* `updateRootInPlace` -> `modifyOpInPlace`
* `startRootUpdate` -> `startOpModification`
* `finalizeRootUpdate` -> `finalizeOpModification`
* `cancelRootUpdate` -> `cancelOpModification`
The term "root" is a misnomer. The root is the op that a rewrite pattern
matches against
(https://mlir.llvm.org/docs/PatternRewriter/#root-operation-name-optional).
A rewriter must be notified of all in-place op modifications, not just
in-place modifications of the root
(https://mlir.llvm.org/docs/PatternRewriter/#pattern-rewriter). The old
function names were confusing and have contributed to various broken
rewrite patterns.
Note: The new function names use the term "modify" instead of "update"
for consistency with the `RewriterBase::Listener` terminology
(`notifyOperationModified`).
Commit: 36ef291d632e3c0ac109e8e1b19ae09d39ac5496
https://github.com/llvm/llvm-project/commit/36ef291d632e3c0ac109e8e1b19ae09d39ac5496
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
A llvm/test/CodeGen/AMDGPU/insert-waitcnts-hang.mir
Log Message:
-----------
[AMDGPU] Fix hang caused by VS_CNT handling at calls (#78318)
Fix a potential hang introduced by #77439 and #77935. This line:
setScoreUB(VS_CNT, getScoreLB(VS_CNT) + getWaitCountMax(VS_CNT));
could potentialy set UB lower than it was before, which confused
SIInsertWaitcnts's fixed point algorithm.
This was only triggered a STORE instruction with an implicit-def, which
seems odd but apparently happens for some spills.
Commit: 42b9ea841e2d9fe186b8892be713443b5f680565
https://github.com/llvm/llvm-project/commit/42b9ea841e2d9fe186b8892be713443b5f680565
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/test/CodeGen/AMDGPU/huge-private-buffer.ll
Log Message:
-----------
[AMDGPU] Increase max scratch allocation for GFX12 (#77625)
Commit: 4a77414660d9ccd5c39cecfcc2dc1bf7fa6866e5
https://github.com/llvm/llvm-project/commit/4a77414660d9ccd5c39cecfcc2dc1bf7fa6866e5
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
A llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
Log Message:
-----------
[AMDGPU] CodeGen for GFX12 8/16-bit SMEM loads (#77633)
Commit: bbf2304d0a5c61565f82aac1a2e2209ed980be39
https://github.com/llvm/llvm-project/commit/bbf2304d0a5c61565f82aac1a2e2209ed980be39
Author: David Spickett <david.spickett at linaro.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M .github/workflows/issue-subscriber.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-subscriber.yml
Log Message:
-----------
[GitHub][workflows] Replace curl with sparse checkout (#78303)
Commit: 15311d5822f5fcaf53bc7cfc728ad2b477a430e4
https://github.com/llvm/llvm-project/commit/15311d5822f5fcaf53bc7cfc728ad2b477a430e4
Author: Pavel Labath <pavel at labath.sk>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
Log Message:
-----------
[lldb] Skip TestExecutableFirst.test_executable_is_first_before_run on ELF
ELF does not have a hard distinction between shared libraries (and
position-independent) executables. It is possible to create a shared
library that will also be executable.
Commit: a3fc0f9d2b73b2bf6afbf420d204ab30253ebf33
https://github.com/llvm/llvm-project/commit/a3fc0f9d2b73b2bf6afbf420d204ab30253ebf33
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Log Message:
-----------
[AMDGPU] Add comments on SITargetLowering::widenLoad
Commit: 68ae1e49d24ce186331866ddae71063f4b8056e2
https://github.com/llvm/llvm-project/commit/68ae1e49d24ce186331866ddae71063f4b8056e2
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseObjc.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaType.cpp
Log Message:
-----------
[Clang][Sema][NFC] Remove unused Scope* parameter from Sema::GetTypeForDeclarator and Sema::ActOnTypeName (#78325)
Split from #78274
Commit: 1fbf5332863e9f7319ce4a91931b2c4ab089d6bb
https://github.com/llvm/llvm-project/commit/1fbf5332863e9f7319ce4a91931b2c4ab089d6bb
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
Log Message:
-----------
AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#76145)
Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.
TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.
patch 3 from: https://github.com/llvm/llvm-project/pull/73337
Commit: 8f7fdd94ef19af7b4905b316c253a78219a6038f
https://github.com/llvm/llvm-project/commit/8f7fdd94ef19af7b4905b316c253a78219a6038f
Author: Haojian Wu <hokein.wu at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/AST/ast-dump-invalid-initialized.cpp
Log Message:
-----------
[clang][AST] Invalidate DecompositionDecl if it has invalid initializer. (#72428)
Fix #67495, #72198
We build ill-formed AST nodes for invalid structured binding. For case
`int [_, b] = {0, 0};`, the `DecompositionDecl` is valid, and its
children `BindingDecl`s are valid but with a NULL type, this breaks
clang invariants in many places, and using these `BindingDecl`s can lead
to crashes. This patch fixes them by marking the DecompositionDecl and
its children invalid.
Commit: e9e9d1b0b1c617481341957a9bedee89a08c3bfd
https://github.com/llvm/llvm-project/commit/e9e9d1b0b1c617481341957a9bedee89a08c3bfd
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
Log Message:
-----------
[AMDGPU] Disable V_MAD_U64_U32/V_MAD_I64_I32 workaround for GFX12 (#77927)
Commit: f12059eb3fd07d3a0cb0b9e8853e1583681d1a36
https://github.com/llvm/llvm-project/commit/f12059eb3fd07d3a0cb0b9e8853e1583681d1a36
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.wait.event.ll
Log Message:
-----------
[AMDGPU] Fix llvm.amdgcn.s.wait.event.export.ready for GFX12 (#78191)
The meaning of bit 0 of the immediate operand of S_WAIT_EVENT has been
flipped from GFX11.
Commit: 2db9244b6f66a4fd4c937de7b33a5b6dda4a06a8
https://github.com/llvm/llvm-project/commit/2db9244b6f66a4fd4c937de7b33a5b6dda4a06a8
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/Metadata.h
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/Metadata.cpp
M llvm/lib/IR/Verifier.cpp
Log Message:
-----------
[RemoveDIs][DebugInfo] Make DIAssignID always replaceable (#78300)
This patch is a necessary step to allowing the new non-intrinsic debug
info to replace llvm.dbg.assign intrinsics. DIAssignIDs must be able to
look up the debug assigns that refer to them, and this patch makes them
always be considered "replaceable", allowing us to track and replace uses
for non-temporary instances.
Commit: e3702f6225fe4438ccffcac3f612e902c7b3db22
https://github.com/llvm/llvm-project/commit/e3702f6225fe4438ccffcac3f612e902c7b3db22
Author: Hirofumi Nakamura <k.nakamura.hirofumi at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/unittests/Format/TokenAnnotatorTest.cpp
Log Message:
-----------
[clang-format] TableGen multi line string support. (#78032)
Support the handling of TableGen's multiline string (code) literal.
That has the form,
[{ this is the string possibly with multi line... }]
Commit: e6bd9835d90c8c30ceeb05338e80d75cf41a3b84
https://github.com/llvm/llvm-project/commit/e6bd9835d90c8c30ceeb05338e80d75cf41a3b84
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/CodeGen/CGBuiltin.cpp
Log Message:
-----------
[clang][CodeGen] Fix gcc warning about unused variable [NFC]
Without the fix gcc warned with
../../clang/lib/CodeGen/CGBuiltin.cpp:1022:19: warning: unused variable 'DRE' [-Wunused-variable]
1022 | if (const auto *DRE = dyn_cast<DeclRefExpr>(Base)) {
| ^~~
Fix the warning by removing the unused variable and change the "dyn_cast"
to "isa".
Commit: c5bbf40d9836409837696e4d60e94ed2ad3d6a32
https://github.com/llvm/llvm-project/commit/c5bbf40d9836409837696e4d60e94ed2ad3d6a32
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M openmp/libomptarget/src/OpenMP/InteropAPI.cpp
Log Message:
-----------
[openmp] Remove extra ';' outside of function
Fixes:
```
[4038/11058] Building CXX object projects/openmp/libomptarget/src/CMakeFiles/omptarget.dir/OpenMP/InteropAPI.cpp.o
/home/aganea/llvm-project/openmp/libomptarget/src/OpenMP/InteropAPI.cpp:202:2: warning: extra ';' outside of a function is incompatible with C++98 [-Wc++98-compat-extra-semi]
};
^
1 warning generated.
```
Commit: 63a3c4cc85066a5fc44ae7f55d5b42a5708b9724
https://github.com/llvm/llvm-project/commit/63a3c4cc85066a5fc44ae7f55d5b42a5708b9724
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/lib/orc/coff_platform.cpp
Log Message:
-----------
[compiler-rt] Silence warning with MSVC 19.38 (Visual Studio 2022 17.8.3)
This fixes:
```
C:\git\llvm-project\compiler-rt\lib\orc\coff_platform.cpp(512): warning C4189: 'JDState': local variable is initialized but not referenced
```
Commit: 92f91dde6975a09830a3453f94f05452789c952f
https://github.com/llvm/llvm-project/commit/92f91dde6975a09830a3453f94f05452789c952f
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M third-party/benchmark/src/benchmark.cc
Log Message:
-----------
[third-party] Silence warning on benchmark when building with Clang ToT
fixes:
```
[7409/7446] Building CXX object third-party\benchmark\src\CMakeFiles\benchmark.dir\benchmark.cc.obj
C:\git\llvm-project\third-party\benchmark\src\benchmark.cc(172,17): warning: offset of on non-standard-layout type 'State' [-Winvalid-offsetof]
172 | static_assert(offsetof(State, error_occurred_) <=
| ^ ~~~~~~~~~~~~~~~
C:\git\llvm_package_18.0.0\build64_stage0\lib\clang\18\include\__stddef_offsetof.h(11,24): note: expanded from macro 'offsetof'
11 | #define offsetof(t, d) __builtin_offsetof(t, d)
| ^ ~
1 warning generated.
```
Commit: 935c652d07145960124ab1264ed1accc26759401
https://github.com/llvm/llvm-project/commit/935c652d07145960124ab1264ed1accc26759401
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
Log Message:
-----------
[lldb] Silence warning when building with Clang ToT
Fixes:
```
C:\git\llvm-project\lldb\source\Plugins\Process\Windows\Common\x64\RegisterContextWindows_x64.cpp(195,5): warning: missing field 'flags_type' initializer [-Wmissing-field-initializers]
```
Commit: 6f8b633d0b0615c2f46f818b70901d880c205631
https://github.com/llvm/llvm-project/commit/6f8b633d0b0615c2f46f818b70901d880c205631
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/lib/profile/InstrProfilingFile.c
M compiler-rt/lib/profile/InstrProfilingMerge.c
M compiler-rt/lib/profile/InstrProfilingValue.c
Log Message:
-----------
[compiler-rt] Silence warnings when building with Clang ToT
Fixes several warnings such as:
```
C:\git\llvm-project\compiler-rt\lib\profile\InstrProfilingFile.c(760,18): warning: cast from 'const char *' to 'void *' drops const qualifier [-Wcast-qual]
760 | free((void *)lprofCurFilename.FilenamePat);
| ^
3 warnings generated.
```
Commit: 6736cc60ed85e52c26d6643301d45c7d98a85698
https://github.com/llvm/llvm-project/commit/6736cc60ed85e52c26d6643301d45c7d98a85698
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/lib/orc/wrapper_function_utils.h
Log Message:
-----------
[ORC-RT] Silence warning when building with Clang ToT on Windows
This fixes several of these:
```
[3524/7446] Building CXX object projects\compiler-rt\lib\orc\CMakeFiles\RTOrc.x86_64.dir\dlfcn_wrapper.cpp.obj
In file included from C:\git\llvm-project\compiler-rt\lib\orc\dlfcn_wrapper.cpp:15:
C:\git\llvm-project\compiler-rt\lib\orc\wrapper_function_utils.h(299,27): warning: address of '__orc_rt_jit_dispatch_ctx' will always evaluate to 'true' [-Wpointer-bool-conversion]
299 | if (ORC_RT_UNLIKELY(!&__orc_rt_jit_dispatch_ctx))
| ~ ^~~~~~~~~~~~~~~~~~~~~~~~~
C:\git\llvm-project\compiler-rt\lib\orc\compiler.h(60,55): note: expanded from macro 'ORC_RT_UNLIKELY'
60 | #define ORC_RT_UNLIKELY(EXPR) __builtin_expect((bool)(EXPR), false)
| ^~~~
1 warning generated.
```
Commit: 2ce430ab2f2964de2fb278467be7bc39fc296792
https://github.com/llvm/llvm-project/commit/2ce430ab2f2964de2fb278467be7bc39fc296792
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/tools/c-index-test/c-index-test.c
Log Message:
-----------
[clang][tools] Silence const cast warning when building with Clang ToT
This fixes:
```
[4960/7446] Building C object tools\clang\tools\c-index-test\CMakeFiles\c-index-test.dir\c-index-test.c.obj
C:\git\llvm-project\clang\tools\c-index-test\c-index-test.c(49,19): warning: cast from 'const char *' to 'char *' drops const qualifier [-Wcast-qual]
49 | return((char*)path);
| ^
C:\git\llvm-project\clang\tools\c-index-test\c-index-test.c(239,18): warning: cast from 'const char *' to 'char *' drops const qualifier [-Wcast-qual]
239 | free((char *)unsaved_files[i].Filename);
| ^
C:\git\llvm-project\clang\tools\c-index-test\c-index-test.c(240,18): warning: cast from 'const char *' to 'char *' drops const qualifier [-Wcast-qual]
240 | free((char *)unsaved_files[i].Contents);
| ^
```
Commit: 0f62e7ea2c608be525bcf0635d8b58190f93c8c3
https://github.com/llvm/llvm-project/commit/0f62e7ea2c608be525bcf0635d8b58190f93c8c3
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/test/fuzzer/lit.cfg.py
Log Message:
-----------
[compiler-rt] Fix fuzzer tests on Windows
This fixes a link-time mismatch between the clang_rt.fuzzer-x86_64.lib
and the fuzzer tests, which happen to build with -fsanitize=address.
See: https://learn.microsoft.com/en-us/cpp/sanitizers/error-container-overflow?view=msvc-170
Commit: bd9bec8e78a8f1f4229c18713425406007a92b64
https://github.com/llvm/llvm-project/commit/bd9bec8e78a8f1f4229c18713425406007a92b64
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/lib/orc/CMakeLists.txt
Log Message:
-----------
[compiler-rt][ORC] Silence warning when building on MSVC/Windows
This fixes (the ORC lib already builds with exceptions disabled):
```
[5/11] Building CXX object projects\compiler-rt\lib\orc\CMakeFiles\RTOrc.x86_64.dir\dlfcn_wrapper.cpp.obj
C:\Program Files\Microsoft Visual Studio\2022\Community\VC\Tools\MSVC\14.38.33130\include\vector(1619): warning C4530: C++ exception handler used, but unwind semantics are not enabled. Specify /EHsc
```
Commit: 47bd76d80fefdcef13a764dbc4c1f7e8320252dd
https://github.com/llvm/llvm-project/commit/47bd76d80fefdcef13a764dbc4c1f7e8320252dd
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/source/API/SBTypeFilter.cpp
M lldb/source/API/SBTypeFormat.cpp
M lldb/source/API/SBTypeSummary.cpp
M lldb/source/API/SBTypeSynthetic.cpp
M lldb/source/Core/ModuleList.cpp
Log Message:
-----------
[lldb] Replace deprecated `std::unique_ptr::unique()` to silence a warning with MS-STL. NFC.
MS-STL warns about this with `warning STL4016: std::shared_ptr::unique() is deprecated in C++17`.
Commit: 994e478601bad117057d27b9d1c98c97d21cdf99
https://github.com/llvm/llvm-project/commit/994e478601bad117057d27b9d1c98c97d21cdf99
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
Log Message:
-----------
[lldb] Use `LLVM_FALLTHROUGH` to avoid a compiler error when building with MSVC.
Commit: 8ef7aaa637fbf1b0ae1ccfb102c081f58e22444d
https://github.com/llvm/llvm-project/commit/8ef7aaa637fbf1b0ae1ccfb102c081f58e22444d
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp
Log Message:
-----------
[lldb] Silence warning with Clang ToT
This fixes `-Wcovered-switch-default` warnings. This is a reminiscent of an old refactoring, see ce03a862372a6f36d2fcf80dc80052aa155fcae8.
Commit: 64874e5ab5fd102344d43ac9465537a44130bf19
https://github.com/llvm/llvm-project/commit/64874e5ab5fd102344d43ac9465537a44130bf19
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M openmp/runtime/src/kmp.h
M openmp/runtime/src/kmp_affinity.cpp
M openmp/runtime/src/kmp_atomic.h
M openmp/runtime/src/kmp_barrier.cpp
M openmp/runtime/src/kmp_dispatch.h
M openmp/runtime/src/kmp_io.cpp
M openmp/runtime/src/kmp_settings.cpp
M openmp/runtime/src/kmp_wait_release.h
M openmp/runtime/src/z_Windows_NT_util.cpp
Log Message:
-----------
[openmp] Silence warnings when building the LLVM release with MSVC
Commit: 61b5bf85f0908b75f736c77f619480094697c435
https://github.com/llvm/llvm-project/commit/61b5bf85f0908b75f736c77f619480094697c435
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/lib/builtins/fp_extend_impl.inc
Log Message:
-----------
[compiler-rt] On Windows, silence warning when building with latest MSVC
This fixes:
```
[3334/7449] Building C object projects\compiler-rt\lib\builtins\CMakeFiles\clang_rt.builtins-x86_64.dir\extendsfdf2.c.obj
C:\git\llvm-project\compiler-rt\lib\builtins\fp_extend_impl.inc(63): warning C4018: '<': signed/unsigned mismatch
```
Commit: 9110c2b40215e64b8cb95ff83877bd50d4e365d1
https://github.com/llvm/llvm-project/commit/9110c2b40215e64b8cb95ff83877bd50d4e365d1
Author: Alexandre Ganea <alex_toresh at yahoo.fr>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/source/Commands/CommandObjectFrame.cpp
Log Message:
-----------
[lldb] On Windows, silence warning with latest MSVC
This fixes:
```
[6083/7449] Building CXX object tools\lldb\source\Commands\CMakeFiles\lldbCommands.dir\CommandObjectFrame.cpp.obj
C:\git\llvm-project\lldb\source\Commands\CommandObjectFrame.cpp(497) : warning C4715: 'CommandObjectFrameVariable::ScopeRequested': not all control paths return a value
```
Commit: cee60a80101dbc2494865910fc7acef4fcab42bd
https://github.com/llvm/llvm-project/commit/cee60a80101dbc2494865910fc7acef4fcab42bd
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
[RISCV] Remove dead early exit in performCombineVMergeAndVOps. NFC
Because a masked instruction always has a tied dest (because it has a
passthru), the early exit if Merge is an implicit def will have always already
been taken in the branch above that handles HasTiedDest.
Commit: 5e8def2f14151655b0cfdb5d3ad591e3b4771e7d
https://github.com/llvm/llvm-project/commit/5e8def2f14151655b0cfdb5d3ad591e3b4771e7d
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
Log Message:
-----------
Revert "[RISCV] Remove dead early exit in performCombineVMergeAndVOps. NFC"
This reverts commit cee60a80101dbc2494865910fc7acef4fcab42bd.
This change is not NFC because there is also an additional check for
isImplicitDef in the branch above.
Commit: 67f5df78d7d1d925100cc318e629bbde64337015
https://github.com/llvm/llvm-project/commit/67f5df78d7d1d925100cc318e629bbde64337015
Author: Sanjay Marreddi <sanjay.mareddi at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/include/regex
M libcxx/test/std/re/re.const/re.matchflag/match_not_eol.pass.cpp
Log Message:
-----------
Revert "[libc++] Fix `regex_search` to match `$` alone with `match_default` flag" (#78349)
The behavior of `std::regex_search` for patterns anchored both to the
start and to the end of the input went wrong after merging #77256 .
Patterns like `"^b*$"` started matching the strings such as `"a"`, which
is not expected.
Reverts the PR: #77256
Commit: 2fe5b157189906cac86c300f1a4c89614087c0f4
https://github.com/llvm/llvm-project/commit/2fe5b157189906cac86c300f1a4c89614087c0f4
Author: Qizhi Hu <836744285 at qq.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/lib/Sema/SemaStmt.cpp
A clang/test/SemaCXX/PR76631.cpp
Log Message:
-----------
[Clang][Sema] improve sema check of clang::musttail attribute (#77727)
Call function with no-return attribute generates code with unreachable
instruction instead of return and if the call statement has
`clang::musttail` attribute, it would crash in `VerifyPass`. Check this
condition in Sema ahead.
Fix [issue](https://github.com/llvm/llvm-project/issues/76631)
Co-authored-by: huqizhi <836744285 at qq.com>
Commit: 837cde8aa15b0eb17aefc24530e82e25000d9fe0
https://github.com/llvm/llvm-project/commit/837cde8aa15b0eb17aefc24530e82e25000d9fe0
Author: Victor Campos <victor.campos at arm.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Headers/arm_acle.h
Log Message:
-----------
[NFC][Clang][Headers] Update refs to ACLE in comments (#78305)
Co-authored-by: Max Iyengar <Max.Iyengar at arm.com>
Commit: 9791e5414960f92396582b9e9ee503ac15799312
https://github.com/llvm/llvm-project/commit/9791e5414960f92396582b9e9ee503ac15799312
Author: Valery Pykhtin <valery.pykhtin at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/test/CodeGenOpenCL/builtins-amdgcn-wave32.cl
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
M llvm/test/Transforms/InstCombine/AMDGPU/amdgcn-intrinsics.ll
Log Message:
-----------
Revert "[AMDGPU] Add InstCombine rule for ballot.i64 intrinsic in wave32 mode." (#78429)
Reverts llvm/llvm-project#71556
Fixes failures:
https://lab.llvm.org/buildbot/#/builders/188/builds/40541
https://lab.llvm.org/buildbot/#/builders/91/builds/21847
https://lab.llvm.org/buildbot/#/builders/98/builds/31671
https://lab.llvm.org/buildbot/#/builders/139/builds/57289
Commit: 77d21e758ea9665631b211abc0e424d7a7c44989
https://github.com/llvm/llvm-project/commit/77d21e758ea9665631b211abc0e424d7a7c44989
Author: Egor Zhdan <e_zhdan at apple.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Lex/Lexer.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Sema.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/test/Sema/ns_error_enum.m
M clang/utils/TableGen/ClangAttrEmitter.cpp
Log Message:
-----------
[APINotes] Upstream dependencies of Sema logic to apply API Notes to decls
This upstreams more of the Clang API Notes functionality that is
currently implemented in the Apple fork:
https://github.com/apple/llvm-project/tree/next/clang/lib/APINotes
This is the largest chunk of the API Notes functionality in the
upstreaming process. I will soon submit a follow-up patch to actually
enable usage of this functionality by having a Clang driver flag that
enables API Notes, along with tests.
Commit: fc0253264445be7f88d4cf0f9129dcb10c2fb84b
https://github.com/llvm/llvm-project/commit/fc0253264445be7f88d4cf0f9129dcb10c2fb84b
Author: Krystian Stasiowski <sdkrystian at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaDecl.cpp
M clang/test/CXX/temp/temp.res/temp.local/p6.cpp
Log Message:
-----------
[Clang][Sema] Diagnose function/variable templates that shadow their own template parameters (#78274)
Previously, we skipped through template parameter scopes (until we hit a
declaration scope) prior to redeclaration lookup for declarators. For
template declarations, the meant that their template parameters would
not be found and shadowing would not be diagnosed. With these changes
applied, the following declarations are correctly diagnosed:
```cpp
template<typename T> void T(); // error: declaration of 'T' shadows template parameter
template<typename U> int U; // error: declaration of 'U' shadows template parameter
```
The reason for skipping past non-declaration & template parameter scopes
prior to lookup appears to have been because `GetTypeForDeclarator`
needed this adjusted scope... but it doesn't actually use this parameter
anymore.
The scope adjustment now happens prior to calling
`ActOnFunctionDeclarator`/`ActOnVariableDeclarator`/`ActOnTypedefDeclarator`
(just in case they depend on this behavior... I didn't check in depth).
Commit: fca6992be1f272f5e997bd510ca03c9389550c13
https://github.com/llvm/llvm-project/commit/fca6992be1f272f5e997bd510ca03c9389550c13
Author: David Sherwood <57997763+david-arm at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp
M llvm/test/Transforms/LoopIdiom/AArch64/byte-compare-index.ll
Log Message:
-----------
[AArch64] Fix a minor issue with AArch64LoopIdiomTransform (#78136)
I found another case where in the end block we could have a PHI that we
deal with incorrectly. The two incoming values are unique - one of them
is
the induction variable and another one is a value defined outside the
loop, e.g.
%final_val = phi i32 [ %inc, %while.body ], [ %d, %while.cond ]
We won't correctly select between the two values in the new end block
that
we create and so we will get the wrong result.
Commit: a348397a1c694b3b294c995c3ea6ebac7e5dda6d
https://github.com/llvm/llvm-project/commit/a348397a1c694b3b294c995c3ea6ebac7e5dda6d
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
Log Message:
-----------
[RISCV] Don't scale cost by LMUL for TCK_CodeSize in getMemoryOpCost (#78407)
Commit: af4f1766ae5e16152e468d927c0d2faf0e1338db
https://github.com/llvm/llvm-project/commit/af4f1766ae5e16152e468d927c0d2faf0e1338db
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow-codegen.ll
A llvm/test/CodeGen/AMDGPU/call-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
M llvm/test/CodeGen/AMDGPU/gfx-call-non-gfx-func.ll
M llvm/test/CodeGen/AMDGPU/preserve-wwm-copy-dst-reg.ll
Log Message:
-----------
AMDGPU: Allocate special SGPRs before user SGPR arguments (#78234)
Commit: 82811a8f50f7a8a2afab3207f51670a7d9b57d4d
https://github.com/llvm/llvm-project/commit/82811a8f50f7a8a2afab3207f51670a7d9b57d4d
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/utils/gn/build/sync_source_lists_from_cmake.py
Log Message:
-----------
[gn] fix minor mistake from f7cb1afa0633
The script printed two `/` when one suffices.
Commit: 3a82a1c3f6bdc9259cc4641f66fc76d1e171e382
https://github.com/llvm/llvm-project/commit/3a82a1c3f6bdc9259cc4641f66fc76d1e171e382
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/include/clang/Basic/OpenACCKinds.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
A clang/test/ParserOpenACC/parse-clauses.cpp
Log Message:
-----------
[OpenACC] Implement 'collapse' clause parsing.
The 'collapse' clause takes an optional 'force:' followed by an integer
constant expression. For now, parse this as an assignment expression,
and we'll check it for value/ICE later.
Commit: 8fb685fb7ea165f2bc27a3f19b1cffc3f5a4b329
https://github.com/llvm/llvm-project/commit/8fb685fb7ea165f2bc27a3f19b1cffc3f5a4b329
Author: Sergio Afonso <safonsof at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/LLVMIR/LLVMOps.td
M mlir/lib/Target/LLVMIR/ModuleImport.cpp
M mlir/lib/Target/LLVMIR/ModuleTranslation.cpp
M mlir/test/Conversion/FuncToLLVM/convert-funcs.mlir
M mlir/test/Dialect/Bufferization/Transforms/one-shot-module-bufferize-analysis.mlir
A mlir/test/Target/LLVMIR/Import/target-cpu.ll
A mlir/test/Target/LLVMIR/target-cpu.mlir
Log Message:
-----------
[MLIR][LLVM] Add explicit target_cpu attribute to llvm.func (#78287)
This patch adds the target_cpu attribute to llvm.func MLIR operations
and updates the translation to/from LLVM IR to match "target-cpu"
function attributes.
Commit: 656bf13004d62b8f8360d8d496bb1e6e08407c22
https://github.com/llvm/llvm-project/commit/656bf13004d62b8f8360d8d496bb1e6e08407c22
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/Analysis/AliasSetTracker.h
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp
M llvm/test/Analysis/AliasSet/argmemonly.ll
M llvm/test/Analysis/AliasSet/guards.ll
M llvm/test/Analysis/AliasSet/intrinsics.ll
M llvm/test/Analysis/AliasSet/memloc-vscale.ll
M llvm/test/Analysis/AliasSet/memset.ll
M llvm/test/Analysis/AliasSet/memtransfer.ll
M llvm/test/Analysis/AliasSet/saturation.ll
M llvm/test/Transforms/LICM/variant-aainfo.ll
M polly/lib/Analysis/ScopBuilder.cpp
M polly/lib/Analysis/ScopDetection.cpp
M polly/lib/Analysis/ScopDetectionDiagnostic.cpp
Log Message:
-----------
[AST] Don't merge memory locations in AliasSetTracker (#65731)
This changes the AliasSetTracker to track memory locations instead of
pointers in its alias sets. The motivation for this is outlined in an RFC
posted on LLVM discourse:
https://discourse.llvm.org/t/rfc-dont-merge-memory-locations-in-aliassettracker/73336
In the data structures of the AST implementation, I made the choice to
replace the linked list of `PointerRec` entries (that had to go anyway)
with a simple flat vector of `MemoryLocation` objects, but for the
`AliasSet` objects referenced from a lookup table, I retained the
mechanism of a linked list, reference counting, forwarding, etc. The
data structures could be revised in a follow-up change.
Commit: cab041fe63f1eba4cf7a43f713dcb4fb06da7e00
https://github.com/llvm/llvm-project/commit/cab041fe63f1eba4cf7a43f713dcb4fb06da7e00
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
R libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/src/__support/UInt.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/utils/FPUtil/x86_long_double_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
Log Message:
-----------
[reland][libc][NFC] Refactor FPBits and remove LongDoubleBits specialization (#78447)
- [reland] #78192
- Make the implementation work when `__uint128_t` is not available on
the plaftorm.
Commit: 59cdf41f077661cd2178123cf27dc688823b6b0f
https://github.com/llvm/llvm-project/commit/59cdf41f077661cd2178123cf27dc688823b6b0f
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
Log Message:
-----------
[AMDGPU] Do not run GCNNSAReassign pass for GFX12 (#78185)
GFX12 does not have separate NSA and non-NSA encodings.
---------
Co-authored-by: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Commit: 4f57e2076bd21b573411bd40ec770a1b6785eee8
https://github.com/llvm/llvm-project/commit/4f57e2076bd21b573411bd40ec770a1b6785eee8
Author: Stephen Tozer <stephen.tozer at sony.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
[RemoveDIs][DebugInfo] Create overloads of debug intrinsic utilities for DPValues (#78313)
In preparation for the major chunk of the assignment tracking
implementation, this patch adds a new set of overloaded versions of
existing functions that take DbgVariableIntrinsics, with the overloads
taking DPValues. This is used specifically to allow us to use generic code
to handle both DbgVariableIntrinsics and DPValues, reducing code
duplication. This patch doesn't actually add the uses of these functions.
Commit: d8627cb1389c9e6485d41028012c7a36b731d72a
https://github.com/llvm/llvm-project/commit/d8627cb1389c9e6485d41028012c7a36b731d72a
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
A libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/src/__support/UInt.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/utils/FPUtil/x86_long_double_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
R utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
Log Message:
-----------
Revert "[reland][libc][NFC] Refactor FPBits and remove LongDoubleBits specialization" (#78457)
Reverts llvm/llvm-project#78447
This broke the gcc buildbot.
Commit: 69ec35fbecc74b3dd917b659e082ce2353303ca9
https://github.com/llvm/llvm-project/commit/69ec35fbecc74b3dd917b659e082ce2353303ca9
Author: Stephen Tozer <Stephen.Tozer at Sony.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/IntrinsicInst.h
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/Transforms/Utils/Local.cpp
Log Message:
-----------
Revert "Create overloads of debug intrinsic utilities for DPValues (#78313)"
This reverts commit 4f57e207, which added several unused functions, causing
build errors on some buildbots.
Commit: e4c8c5851738b7475efa1b9d500078133159369a
https://github.com/llvm/llvm-project/commit/e4c8c5851738b7475efa1b9d500078133159369a
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/MC/AMDGPU/gfx1150_asm_features.s
M llvm/test/MC/AMDGPU/gfx12_asm_features.s
M llvm/test/MC/Disassembler/AMDGPU/gfx1150_dasm_features.txt
A llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_features.txt
Log Message:
-----------
[AMDGPU] Src1 of VOP3 DPP instructions can be SGPR on GFX12 (#77929)
Commit: d92ce344bf641e6bb025b41b3f1a77dd25e2b3e9
https://github.com/llvm/llvm-project/commit/d92ce344bf641e6bb025b41b3f1a77dd25e2b3e9
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/test/CodeGen/ARM/vector-store.ll
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll
M llvm/test/CodeGen/X86/fold-pcmpeqd-2.ll
M llvm/test/CodeGen/X86/pr78109.ll
M llvm/test/CodeGen/X86/var-permute-256.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-4.ll
M llvm/test/CodeGen/X86/vector-interleaved-load-i8-stride-6.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-128.ll
M llvm/test/CodeGen/X86/vector-shift-ashr-256.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-128.ll
M llvm/test/CodeGen/X86/vector-shift-lshr-256.ll
M llvm/test/CodeGen/X86/vector-shift-shl-128.ll
M llvm/test/CodeGen/X86/vector-shift-shl-256.ll
Log Message:
-----------
Revert faecc736e2ac3cd8c77 #74443 [DAG] isSplatValue - node is a splat if all demanded elts have the same whole constant value (#74443)
Relying on ComputeKnownBits to find a splat is causing miscompilations where a shift of zero is being assumed to give zero, but further simplification leads to a shift of zero by undef, resulting in an unexpected undef value.
Fixes #78109
Commit: 58564ddf5c338edb4dee4d36db83be0136f84935
https://github.com/llvm/llvm-project/commit/58564ddf5c338edb4dee4d36db83be0136f84935
Author: Dmitry Chernenkov <dmitryc at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
Log Message:
-----------
[bazel]Sort loads in llvm/BUILD.bazel
Commit: b7c81c1f91994fb6938875b62337ddc2a49bfd51
https://github.com/llvm/llvm-project/commit/b7c81c1f91994fb6938875b62337ddc2a49bfd51
Author: Alexandre Ganea <37383324+aganea at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/utils/release/build_llvm_release.bat
Log Message:
-----------
On Windows, make the release script work with the local git checkout (#78273)
Add two new flags to the release script:
`--skip-checkout` builds from the local source folder, instead of the downloaded source package
`--local-python` uses whichever local Python version is installed, instead of a specific version (3.10)
If the LLVM source is already in `C:\git\llvm-project` then one can do in a admin prompt:
```
C:\git>llvm-project\llvm\utils\release\build_llvm_release.bat --version 18.0.0 --x64 --skip-checkout
...
```
This allows for iterating more easily on build issues, just before a new LLVM package is made.
Also fix some warnings on the second stage build (`-Wbackend-plugin`).
Commit: 13e977d1738261487d8157918f14497517d75821
https://github.com/llvm/llvm-project/commit/13e977d1738261487d8157918f14497517d75821
Author: ostannard <oliver.stannard at arm.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/test/Driver/aarch64-bf16.c
M clang/test/Driver/aarch64-cortex-a510.c
M clang/test/Driver/aarch64-cortex-a710.c
M clang/test/Driver/aarch64-cortex-x2.c
M clang/test/Driver/aarch64-d128.c
M clang/test/Driver/aarch64-fp16.c
M clang/test/Driver/aarch64-implied-sme-features.c
M clang/test/Driver/aarch64-implied-sve-features.c
M clang/test/Driver/aarch64-ite.c
M clang/test/Driver/aarch64-lrcpc3.c
M clang/test/Driver/aarch64-ls64.c
M clang/test/Driver/aarch64-lse128.c
M clang/test/Driver/aarch64-march.c
M clang/test/Driver/aarch64-mgeneral_regs_only.c
M clang/test/Driver/aarch64-mte.c
M clang/test/Driver/aarch64-perfmon.c
M clang/test/Driver/aarch64-predres.c
M clang/test/Driver/aarch64-rand.c
M clang/test/Driver/aarch64-ras.c
M clang/test/Driver/aarch64-rdm.c
M clang/test/Driver/aarch64-ssbs.c
M clang/test/Driver/aarch64-sve2.c
M clang/test/Driver/aarch64-the.c
M clang/test/Driver/aarch64-v81a.c
M clang/test/Driver/aarch64-v82a.c
M clang/test/Driver/aarch64-v83a.c
M clang/test/Driver/aarch64-v84a.c
M clang/test/Driver/aarch64-v85a.c
M clang/test/Driver/aarch64-v86a.c
M clang/test/Driver/aarch64-v87a.c
M clang/test/Driver/aarch64-v88a.c
M clang/test/Driver/aarch64-v89a.c
M clang/test/Driver/aarch64-v91a.c
M clang/test/Driver/aarch64-v92a.c
M clang/test/Driver/aarch64-v93a.c
M clang/test/Driver/aarch64-v94a.c
M clang/test/Driver/aarch64-v95a.c
M clang/test/Driver/arm-sb.c
M clang/test/Preprocessor/aarch64-target-features.c
M flang/test/Driver/target-cpu-features.f90
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/unittests/TargetParser/TargetParserTest.cpp
Log Message:
-----------
[AArch64][Driver] Better handling of target feature dependencies (#78270)
Currently there are several bits of code in the AArch64 driver which
attempt to enforce dependencies between optional features in the -march=
and -mcpu= options. However, these are based on the list of feature
names being enabled/disabled, so they have a lot of logic to consider
the order in which features were turned on and off, which doesn't scale
well as dependency chains get longer.
This patch moves the code handling these dependencies to TargetParser,
and changes them to use a Bitset of enabled features. This makes it easy
to check which features are enabled, and is converted back to a list of
LLVM feature names once all of the command-line options are parsed.
The motivating example for this was the -mcpu=cortex-r82+nofp option.
Previously, the code handling the dependency between the fp16 and
fp16fml extensions did not consider the nofp modifier, so it added
+fullfp16 to the feature list. This should have been disabled by the
+nofp modifier, and also the backend did follow the dependency between
fullfp16 and fp, resulting in fp being turned back on in the backend.
Most of the dependencies added to AArch64TargetParser.h weren't known
about by clang before, I built that list by checking what the backend
thinks the dependencies between SubtargetFeatures are.
Commit: 3d3c63da6bb68d5306cdc9f9fbf867b428e9b0bf
https://github.com/llvm/llvm-project/commit/3d3c63da6bb68d5306cdc9f9fbf867b428e9b0bf
Author: Kelvin Li <kkwli at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M flang/lib/Evaluate/check-expression.cpp
M flang/lib/Evaluate/fold.cpp
M flang/lib/Lower/ConvertConstant.cpp
A flang/test/Lower/structure-constructors-alloc-comp.f90
M flang/test/Semantics/structconst06.f90
M flang/test/Semantics/structconst07.f90
A flang/test/Semantics/structconst08.f90
Log Message:
-----------
[flang] Add structure constructor with allocatable component (#77845)
Enable the structure constructor with allocatable component support.
Handling of `null()` for the allocatable component is added.
Commit: 509f634f76caa40d522875e17188ca77df9159b5
https://github.com/llvm/llvm-project/commit/509f634f76caa40d522875e17188ca77df9159b5
Author: Bruno De Fraine <brunodf at synopsys.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/test/Analysis/BasicAA/separate_storage-alias-sets.ll
Log Message:
-----------
[BasicAA] Fix new test Analysis/BasicAA/separate_storage-alias-sets.ll
An update of the test was not included in 656bf13004 since it was added
after the branch point of that patch.
Commit: abeb6c9f58f69a7e8395ea4a84a0e6f6889eaf78
https://github.com/llvm/llvm-project/commit/abeb6c9f58f69a7e8395ea4a84a0e6f6889eaf78
Author: agozillon <Andrew.Gozillon at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M flang/include/flang/Optimizer/CodeGen/CGPasses.td
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
M flang/test/Fir/convert-to-llvm.fir
Log Message:
-----------
[Flang][MLIR] Add basic initial support for alloca and program address space handling in FIR->LLVMIR codegen (#77518)
This is a slightly more slimmed down and up-to-date version of the older
PR from here: https://reviews.llvm.org/D144203, written by @jsjodin,
which has already under gone some review.
This PR places allocas in the alloca address space specified by the
provided data layout (default is 0 for all address spaces, unless
explicitly specified by the layout), and then will cast these alloca's
to the program address space if this address space is different from the
allocation address space. For most architectures data layouts, this will
be a no-op, as they have a flat address space. But in the case of AMDGPU
it will result in allocas being placed in the correct address space (5,
private), and then casted into the correct program address space (0,
generic). This results in correct (partially, a follow up PR will be
forthcoming soon) generation of allocations inside of device code.
This PR is in addition to the work by @skatrak in this PR:
https://github.com/llvm/llvm-project/pull/69599 and adds seperate and
neccesary functionality of casting alloca's from their address space to
the program address space, both are independent PRs, although there is
some minor overlap e.g. this PR incorporates some of the useful helper
functions from 69599, so whichever lands first will need a minor rebase.
Co-author: jsjodin
Commit: 5ddd7bc38ce3c417637c1c5c506353f1faad4e2d
https://github.com/llvm/llvm-project/commit/5ddd7bc38ce3c417637c1c5c506353f1faad4e2d
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
R libc/src/__support/FPUtil/x86_64/LongDoubleBits.h
M libc/src/__support/FPUtil/x86_64/NextAfterLongDouble.h
M libc/src/__support/UInt.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/utils/FPUtil/x86_long_double_test.cpp
M utils/bazel/llvm-project-overlay/libc/BUILD.bazel
A utils/bazel/llvm-project-overlay/libc/test/src/__support/FPUtil/BUILD.bazel
Log Message:
-----------
[reland][libc][NFC] Refactor FPBits and remove LongDoubleBits specialization (#78465)
- [reland] #78192
- [reland] #78447
- Turn `as` static function into a `to_storage_type` member function.
Commit: 90bdf76fdbe5f4c38a14494a2e8d254ed70c166a
https://github.com/llvm/llvm-project/commit/90bdf76fdbe5f4c38a14494a2e8d254ed70c166a
Author: Petar Avramovic <Petar.Avramovic at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll
Log Message:
-----------
Revert "AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis" (#78468)
Reverts llvm/llvm-project#76145
Commit: a96b4671b97b167230986bd2811676064c608596
https://github.com/llvm/llvm-project/commit/a96b4671b97b167230986bd2811676064c608596
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M flang/lib/Lower/ConvertVariable.cpp
A flang/test/Lower/HLFIR/bindc-module-var.f90
Log Message:
-----------
[flang] Lower BIND(C) module variables (#78279)
Lower initialized BIND(C) module variable as regular module variable,
except that the fir.global symbol name is the binding label.
For uninitialized variables, add the common linkage so that C code may
define the variables. The standard does not provide a way to indicate
that a variable is defined in C, but there are use cases.
Beware that if the module file compiled object is added to a shared
library, the variable will become a regular global definition and may
override the C variable depending on the linking order.
Commit: 5b65f6f5864ff23e4d87ab1d954a77be343b4c4b
https://github.com/llvm/llvm-project/commit/5b65f6f5864ff23e4d87ab1d954a77be343b4c4b
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn
Log Message:
-----------
[gn] fix mistake from 92289db82fb2
Commit: 74cf9bcf71d94f4df80578bccec6ed6d51dd9682
https://github.com/llvm/llvm-project/commit/74cf9bcf71d94f4df80578bccec6ed6d51dd9682
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/include/mlir/Dialect/GPU/TransformOps/Utils.h
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
Log Message:
-----------
Apply clang-tidy fixes for performance-unnecessary-value-param in Utils.cpp (NFC)
Commit: 9a2a6a728ae0397584fcfb8b2919970d1128e7f5
https://github.com/llvm/llvm-project/commit/9a2a6a728ae0397584fcfb8b2919970d1128e7f5
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/lib/Dialect/GPU/TransformOps/Utils.cpp
Log Message:
-----------
Apply clang-tidy fixes for readability-identifier-naming in Utils.cpp (NFC)
Commit: e730f7600525fd5a9764b5076c6af08dbf477014
https://github.com/llvm/llvm-project/commit/e730f7600525fd5a9764b5076c6af08dbf477014
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/lib/Dialect/GPU/Transforms/DecomposeMemrefs.cpp
Log Message:
-----------
Apply clang-tidy fixes for llvm-qualified-auto in DecomposeMemrefs.cpp (NFC)
Commit: 04e2a5d9837959522eb0ab7b7da499e34a0f07ae
https://github.com/llvm/llvm-project/commit/04e2a5d9837959522eb0ab7b7da499e34a0f07ae
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/lib/Dialect/IRDL/IRDLLoading.cpp
Log Message:
-----------
Apply clang-tidy fixes for readability-identifier-naming in IRDLLoading.cpp (NFC)
Commit: 2cd013a7869a341a6536324c34f0c4e68bf01a38
https://github.com/llvm/llvm-project/commit/2cd013a7869a341a6536324c34f0c4e68bf01a38
Author: Mehdi Amini <joker.eph at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/lib/Dialect/IRDL/IRDLVerifiers.cpp
Log Message:
-----------
Apply clang-tidy fixes for llvm-else-after-return in IRDLVerifiers.cpp (NFC)
Commit: 4ea1994a0307b09532d519292d34dad7555598ca
https://github.com/llvm/llvm-project/commit/4ea1994a0307b09532d519292d34dad7555598ca
Author: John Harrison <harjohn at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/test/API/tools/lldb-dap/completions/TestDAP_completions.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/lldb-dap.cpp
Log Message:
-----------
[lldb-dap] Adjusting how repl-mode auto determines commands vs variable expressions. (#78005)
The previous logic for determining if an expression was a command or
variable expression in the repl would incorrectly identify the context
in many common cases where a local variable name partially overlaps with
the repl input.
For example:
```
int foo() {
int var = 1; // break point, evaluating "p var", previously emitted a warning
}
```
Instead of checking potentially multiple conflicting values against the
expression input, I updated the heuristic to only consider the first
term. This is much more reliable at eliminating false positives when the
input does not actually hide a local variable.
Additionally, I updated the warning on conflicts to occur anytime the
conflict is detected since the specific conflict can change based on the
current input. This also includes additional details on how users can
change the behavior.
Example Debug Console output from
lldb/test/API/tools/lldb-dap/evaluate/main.cpp:11 breakpoint 3.
```
lldb-dap> var + 3
Warning: Expression 'var' is both an LLDB command and variable. It will be evaluated as a variable. To evaluate the expression as an LLDB command, use '`' as a prefix.
45
lldb-dap> var + 1
Warning: Expression 'var' is both an LLDB command and variable. It will be evaluated as a variable. To evaluate the expression as an LLDB command, use '`' as a prefix.
43
```
Commit: d525e2b31b999fb2c989fb0986332066466c61c7
https://github.com/llvm/llvm-project/commit/d525e2b31b999fb2c989fb0986332066466c61c7
Author: Paul T Robinson <paul.robinson at sony.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Headers/ia32intrin.h
M clang/lib/Headers/immintrin.h
Log Message:
-----------
[Headers][X86] Add more descriptions to ia32intrin.h and immintrin.h (#77686)
ia32intrin.h gets descriptions for all remaining non-privileged
intrinsic functions; the macros providing alternate names are not
described. immintrin.h ditto, except for the InterlockedExchange
functions.
Commit: 3b6a8f823bf873aa74cdb738f517e7333e20de7a
https://github.com/llvm/llvm-project/commit/3b6a8f823bf873aa74cdb738f517e7333e20de7a
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
M lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
M lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Platform/MacOSX/CMakeLists.txt
M lldb/source/Plugins/Platform/MacOSX/PlatformAppleSimulator.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
A lldb/source/Plugins/Platform/MacOSX/PlatformRemoteAppleXR.cpp
A lldb/source/Plugins/Platform/MacOSX/PlatformRemoteAppleXR.h
M lldb/source/Plugins/Platform/MacOSX/objcxx/PlatformiOSSimulatorCoreSimulatorSupport.h
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/SystemRuntime/MacOSX/SystemRuntimeMacOSX.cpp
M lldb/source/Utility/XcodeSDK.cpp
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
Log Message:
-----------
[lldb] Upstream xros support in lldb (#78389)
Upstream support for debugging xros applications through LLDB.
Commit: ae1355cdb7b13ec8f5c8b8644d62679ff274b508
https://github.com/llvm/llvm-project/commit/ae1355cdb7b13ec8f5c8b8644d62679ff274b508
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/lldb/source/Plugins/Platform/MacOSX/BUILD.gn
Log Message:
-----------
[gn build] Port 3b6a8f823bf8
Commit: 2d5cc1c9b3c8b8b7cd0ed9dec79489940161d73a
https://github.com/llvm/llvm-project/commit/2d5cc1c9b3c8b8b7cd0ed9dec79489940161d73a
Author: alexfh <alexfh at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
R llvm/test/Transforms/SimplifyCFG/switch-dead-default-lookup-table.ll
M llvm/test/Transforms/SimplifyCFG/switch-dead-default.ll
Log Message:
-----------
Revert "[SimplifyCFG] `switch`: Do Not Transform the Default Case if the Condition is Too Wide" (#78469)
Reverts llvm/llvm-project#77831, which depends on #76669, which
seriously regresses compilation time / memory usage see
https://github.com/llvm/llvm-project/pull/76669#issuecomment-1889271710.
Commit: badf0ee80c2b53bbc227f5d12c74819c01ceaf3c
https://github.com/llvm/llvm-project/commit/badf0ee80c2b53bbc227f5d12c74819c01ceaf3c
Author: Chris Apple <14171107+cjappl at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/cmake/config-ix.cmake
Log Message:
-----------
Remove maximum OSX version for sanitizers (#77543)
Remove a block preventing newer versions of the MacOS SDK from being
selected for compiling the sanitizers.
Commit: c99da46fc182bd28b0661b1b1a6f0a4c1aef2392
https://github.com/llvm/llvm-project/commit/c99da46fc182bd28b0661b1b1a6f0a4c1aef2392
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/atomics.ll
A llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
Log Message:
-----------
[AMDGPU][GFX12] Add Atomic cond_sub_u32 (#76224)
Co-authored-by: Vang Thao <Vang.Thao at amd.com>
Commit: 735adbf1a80db3fe9ea8edaa172582ed2729a220
https://github.com/llvm/llvm-project/commit/735adbf1a80db3fe9ea8edaa172582ed2729a220
Author: Cyndy Ishida <cyndy_ishida at apple.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Analysis/TargetLibraryInfo.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/test/MC/MachO/AArch64/arm-darwin-version-min-load-command.s
M llvm/test/MC/MachO/ARM/build-version-sdk-version.s
M llvm/test/MC/MachO/ARM/build-version.s
M llvm/unittests/TextAPI/TextStubV4Tests.cpp
Log Message:
-----------
[llvm] Teach MachO about XROS (#78373)
Add support for XROS to encode in Mach-O file formats.
Commit: da7462a6ae3730551efe0be5d7d525195dc3678f
https://github.com/llvm/llvm-project/commit/da7462a6ae3730551efe0be5d7d525195dc3678f
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/test/CodeGen/NVPTX/surf-tex.py
Log Message:
-----------
[NVPTX] Add tex.grad.cube{array} intrinsics (#77693)
Extend IR support for PTX `tex` instruction described in [PTX ISA.
9.7.9.3. Texture Instructions:
tex](https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#texture-instructions-tex).
Add support for unified-move versions of `tex.grad.cube{array}` variants
added in PTX ISA 4.3.
Commit: bd5d41a3401f2dc31a82bb04deb0f47fd768a270
https://github.com/llvm/llvm-project/commit/bd5d41a3401f2dc31a82bb04deb0f47fd768a270
Author: Valentin Clement (バレンタイン クレメン) <clementval at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp
Log Message:
-----------
[mlir][openacc][NFC] Use interleaveComma in printers (#78347)
Simplify printer code and use llvm::interleaveComma to print comma
separated list.
Commit: 0c6dc80531ed332e346934019095ad9518f465f3
https://github.com/llvm/llvm-project/commit/0c6dc80531ed332e346934019095ad9518f465f3
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Support/BalancedPartitioning.cpp
M llvm/unittests/ProfileData/BPFunctionNodeTest.cpp
Log Message:
-----------
BalancedPartitioning: minor updates (#77568)
When LargestTraceSize is a power of two, createBPFunctionNodes does not
allocate a group ID for Trace[LargestTraceSize-1] (as N is off by 1).
Fix
this and change floor+log2 to Log2_64.
BalancedPartitioning::bisect can use unstable sort because `Nodes`
contains distinct `InputOrderIndex`s.
BalancedPartitioning::runIterations: use one DenseMap and simplify the
node renumbering code.
Commit: a451c3b9e2124ba2875be678aaafde322057d575
https://github.com/llvm/llvm-project/commit/a451c3b9e2124ba2875be678aaafde322057d575
Author: Alex Langford <alangford at apple.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
Log Message:
-----------
[lldb] Support changes to TLS on macOS (#77988)
The TLS implementation on apple platforms has changed. Instead of
invoking pthread_getspecific with a pthread_key_t, we instead perform a
virtual function call.
Note: Some versions of Apple's new linker do not emit debug symbols for
TLS symbols. This causes the TLS tests to fail because LLDB and dsymutil
expects there to be debug symbols to resolve the relevant TLS block. You
may work around this by switching to the older linker (ld-classic) or by
disabling the TLS tests until you have a newer version of the new
linker.
rdar://120676969
Commit: bc90b91885263eb2128315ff636b7f2d200eab48
https://github.com/llvm/llvm-project/commit/bc90b91885263eb2128315ff636b7f2d200eab48
Author: Alex Bradbury <asb at igalia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfo.h
M llvm/unittests/Target/RISCV/RISCVInstrInfoTest.cpp
Log Message:
-----------
Revert "[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg"
This reverts commit 4b7d997aaed7a2399d5e73fc3adfaaa6a3d35d1f.
A miscompile was reported
<https://github.com/llvm/llvm-project/pull/77610#issuecomment-1896193835>.
Reverting so it can be investigated.
Commit: 103fa3250c46b0c4cf04573c5e075185ca574016
https://github.com/llvm/llvm-project/commit/103fa3250c46b0c4cf04573c5e075185ca574016
Author: Derek Schuff <dschuff at chromium.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lld/wasm/InputFiles.cpp
M lld/wasm/SymbolTable.cpp
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/BinaryFormat/WasmTraits.h
M llvm/include/llvm/MC/MCSymbolWasm.h
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
M llvm/tools/obj2yaml/wasm2yaml.cpp
Log Message:
-----------
[WebAssembly] Use ValType instead of integer types to model wasm tables (#78012)
LLVM models some features found in the binary format with raw integers
and others with nested or enumerated types. This PR switches modeling of
tables and segments to use wasm::ValType rather than uint32_t. This NFC
change is in preparation for modeling more reference types, but IMO is
also cleaner and closer to the spec.
Commit: b1ae461a5358932851de42b66ffde8748da51a83
https://github.com/llvm/llvm-project/commit/b1ae461a5358932851de42b66ffde8748da51a83
Author: Michael Maitland <michaeltmaitland at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/MachineScheduler.cpp
Log Message:
-----------
[CodeGen][MISched][NFC] Rename some instances of Cycle -> ReleaseAtCycle
This is to match the naming of arguments in MachineScheduler.h
Commit: de423cfe3d5de0110b4f55ff1742988b529be6d2
https://github.com/llvm/llvm-project/commit/de423cfe3d5de0110b4f55ff1742988b529be6d2
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-subvector.ll
M llvm/test/CodeGen/RISCV/rvv/load-add-store.ll
Log Message:
-----------
[RISCV] Prefer vsetivli for VLMAX when VLEN is exactly known (#75509)
If VLEN is exactly known, we may be able to use the vsetivli encoding
instead of the vsetvli a0, zero, <vtype> encoding. This slightly reduces
register pressure.
This builds on 632f1c5, but reverses course a bit. It turns out to be
quite complicated to canonicalize from VLMAX to immediate early because
the sentinel value is widely used in tablegen patterns without knowledge
of LMUL. Instead, we canonicalize towards the VLMAX representation, and
then pick the immediate form during insertion since we have the LMUL
information there.
Within InsertVSETVLI, this could reasonable fit in a couple places. If
reviewers want me to e.g. move it to emission, let me know. Doing so may
require a bit of extra code to e.g. handle comparisons of the two forms,
but shouldn't be too complicated.
Commit: 67dc6e907577e8c96adcf574c5787fe5bdf9bb1a
https://github.com/llvm/llvm-project/commit/67dc6e907577e8c96adcf574c5787fe5bdf9bb1a
Author: Thorsten Schütt <schuett at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/icmp.ll
Log Message:
-----------
[GlobalIsel][AArch64] more legal icmps (#78239)
In https://github.com/llvm/llvm-project/pull/78181 the godbolt
(https://llvm.godbolt.org/z/vMsnxMf1v) crashed with GlobalIsel.
LLVM ERROR: unable to legalize instruction: %90:_(<3 x s32>) = G_ICMP
intpred(uge), %15:_(<3 x s32>), %0:_ (in function: vec3_i32)
Commit: c1f433849be5e19127f23c1b4c5f1d0ee0ec63ca
https://github.com/llvm/llvm-project/commit/c1f433849be5e19127f23c1b4c5f1d0ee0ec63ca
Author: Mikhail Gudim <mgudim at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/rotate-rv64.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv32.mir
A llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/shift-rv64.mir
Log Message:
-----------
[GISel][RISCV] Implement selectShiftMask. (#77572)
Implement `selectShiftMask` in `GlobalISel`.
Commit: e473daa7797db6e0f45ef9e12081ccce7d2ed26f
https://github.com/llvm/llvm-project/commit/e473daa7797db6e0f45ef9e12081ccce7d2ed26f
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/test/Analysis/CostModel/AArch64/vec3-ops.ll
Log Message:
-----------
[AArch64] Improve cost computations for odd vector mem ops. (#78181)
Improve cost computaton for odd vector mem ops by breaking them down
into smaller power-of-2 parts and sum up the cost of those parts.
This fixes the current cost estimates, which for most parts
underestimated the cos, due to using getTypeLegalizationCost, which
widens to the next power-of-2 in a single step in most cases. This
doesn't reflect the actual cost.
See https://llvm.godbolt.org/z/vMsnxMf1v for codegen for the tests.
Note that there is a special case for v3i8, for which current codegen is
pretty bad, due to automatic widening to v4i8, which in turn requires
the conversion to go through memory ops in the stack. I am planning on
fixing that as a follow-up, but I am not yet sure where to best fix
this.
At the moment, there are almost no cases in which such vector operations
will be generated automatically. The motivating case is non-power-of-2
SLP vectorization: https://github.com/llvm/llvm-project/pull/77790
PR: https://github.com/llvm/llvm-project/pull/78181
Commit: b26bfcc1ecc3c56d36fe6e525788024d1fdee01c
https://github.com/llvm/llvm-project/commit/b26bfcc1ecc3c56d36fe6e525788024d1fdee01c
Author: Jacek Caban <jacek at codeweavers.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/Object/COFFImportFile.h
M llvm/lib/Object/COFFImportFile.cpp
M llvm/test/tools/llvm-dlltool/coff-exports.def
M llvm/test/tools/llvm-lib/arm64ec-implib.test
M llvm/test/tools/llvm-readobj/COFF/exports-implib.test
M llvm/test/tools/llvm-readobj/COFF/file-headers.test
M llvm/tools/llvm-readobj/COFFImportDumper.cpp
Log Message:
-----------
[llvm-readobj][Object][COFF] Include COFF import file machine type in format string. (#78366)
Commit: 03e43cf1c7ed0770b4afef915f82f2503a9f18fb
https://github.com/llvm/llvm-project/commit/03e43cf1c7ed0770b4afef915f82f2503a9f18fb
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Lex/UnicodeCharSets.h
M clang/test/Lexer/unicode.c
M llvm/lib/Support/Unicode.cpp
M llvm/lib/Support/UnicodeCaseFold.cpp
M llvm/lib/Support/UnicodeNameToCodepoint.cpp
M llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
M llvm/unittests/Support/UnicodeTest.cpp
M llvm/utils/UnicodeData/UnicodeNameMappingGenerator.cpp
Log Message:
-----------
[Clang] Update Unicode version to 15.1 (#77147)
This update all of our Unicode tables to Unicode 15.1. This is a minor
version so only a relatively small numbers of characters are added,
mainly ideographs
https://www.unicode.org/versions/Unicode15.1.0/#Appendices_nb
Commit: 345c1ea881012d84a10b3fe6c2c420dbf8e3ef31
https://github.com/llvm/llvm-project/commit/345c1ea881012d84a10b3fe6c2c420dbf8e3ef31
Author: Peter Klausler <35819229+klausler at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M flang/lib/Semantics/resolve-directives.cpp
Log Message:
-----------
[flang] Avoid new spurious error under -fopenacc (#78504)
Don't create HostAssocDetails symbols for subprograms in OpenACC
regions; it can cause warnings to became errors later in compilation
when calls do not appear to be to external procedures with implicit
interfaces.
Commit: 58b77b8581989a960bcb3bd088ac4a3e00c9fdb5
https://github.com/llvm/llvm-project/commit/58b77b8581989a960bcb3bd088ac4a3e00c9fdb5
Author: erichkeane <ekeane at nvidia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/OpenACCKinds.h
M clang/include/clang/Parse/Parser.h
M clang/lib/Parse/ParseOpenACC.cpp
M clang/test/ParserOpenACC/parse-clauses.c
M clang/test/ParserOpenACC/parse-clauses.cpp
M clang/test/ParserOpenACC/parse-constructs.cpp
Log Message:
-----------
[OpenACC] Implement 'bind' clause parsing.
'bind' takes either a string literal, or an 'identifier' representing
the device-side function that this routine is intended to 'bind' to
(that is, to call). However, it seems that the intent is to permit the
'identifier' to reference any function, thus we're implementing this as
an ID expression.
Additionally, while working on this I discovered that the 'routine' ID
expression parsing for C++ wouldn't allow non-static member functions to
be referenced since it expected us to call it, this was fixed as a part
of this patch as the 'bind' support needed it too. A test was added for
routine.
Commit: 47d59670230fe6940fafd3844c219c4c4636ea76
https://github.com/llvm/llvm-project/commit/47d59670230fe6940fafd3844c219c4c4636ea76
Author: michaelrj-google <71531609+michaelrj-google at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libc/config/linux/aarch64/entrypoints.txt
Log Message:
-----------
[libc][obvious] disable fabsf128 on aarch64 (#78511)
It's not working on the buildbot, so I've disabled it until we fix it.
Commit: 17c390fc789e0f0b33577add7364e89d15a44efa
https://github.com/llvm/llvm-project/commit/17c390fc789e0f0b33577add7364e89d15a44efa
Author: modiking <modiking213 at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lld/ELF/Driver.cpp
M lld/test/ELF/lto/devirt_validate_vtable_typeinfos.ll
Log Message:
-----------
[WPD][LLD] Allow glob matching of --lto-known-safe-vtables (#78505)
Makes it easier to exclude a pattern of safe vtable symbols
Testing:
ninja check-all
Commit: 987123e4f1a6e1713b7c684e696e9b1cd8d595ea
https://github.com/llvm/llvm-project/commit/987123e4f1a6e1713b7c684e696e9b1cd8d595ea
Author: Philip Reames <preames at rivosinc.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lld/ELF/Arch/RISCV.cpp
Log Message:
-----------
[LLD][RISCV] Report error for unsatisfiable RISCV_ALIGN (#74121)
If we have a RISCV_ALIGN relocation which can't be satisfied with the
available space provided, report an error rather than silently
continuing with a corrupt state.
For context, https://github.com/llvm/llvm-project/pull/73977 fixes an
LLD bug which can cause this effect, but that's not the only source of
such cases.
Another is our hard-to-fix set of LTO problems. We can have a single
function which was compiled without C in an otherwise entirely C module.
Until we have all of the mapping symbols and related mechanisms
implemented, this case can continue to arise.
I think it's very important from a user interface perspective to have
non-assertion builds report an error in this case. If we don't report an
error here, we can crash the linker (due to the fatal error at the
bottom of the function), or if we're less lucky silently produce a
malformed binary.
There's a couple of known defects with this patch.
First, there's no test case. I don't know how to write a stable test
case for this that doesn't involve hex editing an object file, or
abusing the LTO bug that we hope to fix.
Second, this will report an error on each relax iteration. I explored
trying to report an error only once after relaxation, but ended up
deciding I didn't have the context to implement it safely.
I would be thrilled if someone more knowledgeable of this code wants to
write a better version of this patch, but in the meantime, I believe we
should land this to address the user experience problem described above.
Commit: 4fffb0401be10dc155e8b51321735f14f88c2589
https://github.com/llvm/llvm-project/commit/4fffb0401be10dc155e8b51321735f14f88c2589
Author: Samuel Thibault <samuel.thibault at ens-lyon.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets.cpp
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hurd.cpp
A clang/test/Driver/Inputs/basic_cross_hurd_tree/usr/lib/gcc/x86_64-gnu/10/crtbegin.o
A clang/test/Driver/Inputs/basic_cross_hurd_tree/usr/x86_64-gnu/bin/as
A clang/test/Driver/Inputs/basic_cross_hurd_tree/usr/x86_64-gnu/bin/ld
A clang/test/Driver/Inputs/basic_cross_hurd_tree/usr/x86_64-gnu/lib/.keep
A clang/test/Driver/Inputs/basic_hurd_tree/lib/x86_64-gnu/.keep
A clang/test/Driver/Inputs/basic_hurd_tree/lib64/.keep
A clang/test/Driver/Inputs/basic_hurd_tree/usr/include/x86_64-gnu/.keep
A clang/test/Driver/Inputs/basic_hurd_tree/usr/include/x86_64-gnu/c++/10/.keep
A clang/test/Driver/Inputs/basic_hurd_tree/usr/lib/gcc/x86_64-gnu/10/crtbegin.o
A clang/test/Driver/Inputs/basic_hurd_tree/usr/lib/gcc/x86_64-gnu/10/crtbeginS.o
A clang/test/Driver/Inputs/basic_hurd_tree/usr/lib/gcc/x86_64-gnu/10/crtbeginT.o
A clang/test/Driver/Inputs/basic_hurd_tree/usr/lib/x86_64-gnu/.keep
A clang/test/Driver/Inputs/basic_hurd_tree/usr/lib64/.keep
M clang/test/Driver/hurd.cpp
M llvm/unittests/TargetParser/TripleTest.cpp
Log Message:
-----------
Hurd: Add x86_64 support (#78065)
This adds Hurd toolchain support to Clang's driver in addition to
handling
translating the triple from GCC toolchain-compatible form (x86_64-gnu)
to
the actual triple registered in LLVM (x86_64-pc-hurd-gnu).
Commit: 5133a8f5590d74d9d15631742a3d84f978394dbd
https://github.com/llvm/llvm-project/commit/5133a8f5590d74d9d15631742a3d84f978394dbd
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/include/clang/Driver/Options.td
M clang/lib/Driver/ToolChains/Gnu.cpp
A clang/test/Driver/Inputs/basic_android_tree/sysroot/usr/lib/crt_pad_segment.o
M clang/test/Driver/linux-ld.c
Log Message:
-----------
[Driver] Add -fandroid-pad-segment/-fno-android-pad-segment (#77244)
-fandroid-pad-segment is an Android-specific opt-in option that
links in crt_pad_segment.o (beside other crt*.o relocatable files).
crt_pad_segment.o contains a note section, which will be included in the
linker-created PT_NOTE segment. This PT_NOTE tell Bionic that: when
create a map for a PT_LOAD segment, extend the end to cover the gap so
that we will have fewer kernel 'struct vm_area_struct' objects when
page_size < MAXPAGESIZE.
See also https://sourceware.org/bugzilla/show_bug.cgi?id=31076
Link: https://r.android.com/2902180
Commit: 0f67c7a0af271888930bb315c85d05d3936e265a
https://github.com/llvm/llvm-project/commit/0f67c7a0af271888930bb315c85d05d3936e265a
Author: Michael Spencer <bigcheesegs at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/test/PCH/gch-probe.c
Log Message:
-----------
[clang] Disable gch-probe.c on AIX as `-gmodules` is not supported there yet. (#78513)
Followup fix for https://github.com/llvm/llvm-project/pull/77711
Commit: 3db5c058ff595e7d2f3a9df8c3bf265e54332a07
https://github.com/llvm/llvm-project/commit/3db5c058ff595e7d2f3a9df8c3bf265e54332a07
Author: Erich Keane <ekeane at nvidia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/include/clang/AST/DeclBase.h
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaTemplate.cpp
Log Message:
-----------
Add Variadic 'dropAttrs' (#78476)
As suggested in https://github.com/llvm/llvm-project/pull/78200
This adds a variadic 'dropAttrs', which drops all attributes of any of
the types specified.
Commit: 04a69a10f63dae3c03cdfa5e199d8ea4458398b5
https://github.com/llvm/llvm-project/commit/04a69a10f63dae3c03cdfa5e199d8ea4458398b5
Author: antangelo <contact at antangelo.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
Log Message:
-----------
[clang] Fix CTAD for aggregates for nested template classes (#78387)
Use the template pattern in determining whether to synthesize the
aggregate deduction guide, and update
DeclareImplicitDeductionGuideFromInitList to substitute outer template
arguments.
Fixes #77599
Commit: af0ee617fc5f69051297b0c23f8c818b20f02c3a
https://github.com/llvm/llvm-project/commit/af0ee617fc5f69051297b0c23f8c818b20f02c3a
Author: Sirraide <74590115+Sirraide at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
A clang/test/CodeGenCXX/ms-property-new.cpp
A clang/test/CodeGenCXX/placement-new-ms-__noop.cpp
A clang/test/CodeGenObjCXX/property-placement-new.mm
M clang/test/SemaCXX/builtin-std-move.cpp
A clang/test/SemaCXX/ms-property-new.cpp
A clang/test/SemaCXX/placement-new-bound-member-function.cpp
A clang/test/SemaCXX/placement-new-builtin.cpp
A clang/test/SemaCXX/placement-new-matrix.cpp
A clang/test/SemaCXX/placement-new-ms-__noop.cpp
A clang/test/SemaObjCXX/property-placement-new.mm
Log Message:
-----------
[Clang] Support MSPropertyRefExpr as placement arg to new-expression (#75883)
It seems we were forgetting to call `checkArgsForPlaceholders` on the
placement arguments of new-expressions in Sema. I don't think that was
intended—at least doing so doesn't seem to break anything—so this pr
adds that.
This also fixes #65053
---------
Co-authored-by: Erich Keane <ekeane at nvidia.com>
Commit: 1b60ddd920e0caadfa85cc7013b559d6453d7e3e
https://github.com/llvm/llvm-project/commit/1b60ddd920e0caadfa85cc7013b559d6453d7e3e
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/lib/Driver/ToolChains/Hurd.cpp
Log Message:
-----------
[Hurd] Fix -Wswitch in Hurd::getDynamicLinker (NFC)
llvm-project/clang/lib/Driver/ToolChains/Hurd.cpp:137:11:
error: 60 enumeration values not handled in switch: 'UnknownArch', 'arm', 'armeb'... [-Werror,-Wswitch]
switch (getArch()) {
^~~~~~~~~
1 error generated.
Commit: 00647a18cee6ced40757d03a8c0d61d7571d22d3
https://github.com/llvm/llvm-project/commit/00647a18cee6ced40757d03a8c0d61d7571d22d3
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/TargetMachine.cpp
M llvm/test/CodeGen/X86/code-model-elf-sections.ll
Log Message:
-----------
[X86] Don't respect large data threshold for globals with an explicit section (#78348)
If multiple globals are placed in an explicit section, there's a chance
that the large data threshold will cause the different globals to be
inconsistent in whether they're large or small. Mixing sections with
mismatched large section flags can cause undesirable issues like
increased relocation pressure because there may be 32-bit references to
the section in some TUs, but the section is considered large since input
section flags are unioned and other TUs added the large section flag.
An explicit code model on the global still overrides the decision. We
can do this for globals without any references to them, like what we did
with asan_globals in #74514. If we have some precompiled small code
model files where asan_globals is not considered large mixed with
medium/large code model files, that's ok because the section is
considered large and placed farther. However, overriding the code model
for globals in some TUs but not others and having references to them
from code will still result in the above undesired behavior.
This mitigates a whole class of mismatched large section flag issues
like what #77986 was trying to fix.
This ends up not adding the SHF_X86_64_LARGE section flag on explicit
sections in the medium/large code model. This is ok for the large code
model since all references from large text must use 64-bit relocations
anyway.
Commit: 1d4c0092a82aa351c5a6e9e501cc5edbc6c0477f
https://github.com/llvm/llvm-project/commit/1d4c0092a82aa351c5a6e9e501cc5edbc6c0477f
Author: Arthur Eubanks <aeubanks at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M lld/ELF/Relocations.cpp
A lld/test/ELF/x86-64-pc32-overflow-large.s
Log Message:
-----------
[lld/ELF] Hint if R_X86_64_PC32 overflows and references a SHF_X86_64_LARGE section (#73045)
Makes it clearer what the issue is when hand-written assembly doesn't
follow medium code model assumptions in a medium code model build.
Alternative to #71248 by only hinting on an overflow.
Commit: b647a34c9f4ef1527c4641eaa51a771ce81a1fe7
https://github.com/llvm/llvm-project/commit/b647a34c9f4ef1527c4641eaa51a771ce81a1fe7
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/TargetParser/AArch64TargetParser.cpp
Log Message:
-----------
[AArch64] Fix -Wreturn-type in AArch64TargetParser.cpp (NFC)
llvm-project/llvm/lib/TargetParser/AArch64TargetParser.cpp:157:1:
error: non-void function does not return a value in all control paths [-Werror,-Wreturn-type]
}
^
1 error generated.
Commit: f2b5a314b29275f2092af3ec26f42272daa4312c
https://github.com/llvm/llvm-project/commit/f2b5a314b29275f2092af3ec26f42272daa4312c
Author: Craig Topper <craig.topper at sifive.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVProcessors.td
Log Message:
-----------
[RISCV] Add LUI/AUIPC+ADDI fusions to sifive-p450. (#78501)
Commit: 430a40d12eaa5a61792c4670955c110146902afb
https://github.com/llvm/llvm-project/commit/430a40d12eaa5a61792c4670955c110146902afb
Author: Alex MacLean <amaclean at nvidia.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/CodeGen/NVPTX/mulhi-intrins.ll
A llvm/test/CodeGen/NVPTX/sad-intrins.ll
Log Message:
-----------
[NVPTX] extend type support for nvvm.{min,max,mulhi,sad} (#78385)
Ensure intrinsics and auto-upgrades support i16, i32, and i64 for for
`nvvm.{min,max,mulhi,sad}`
- `nvvm.min` and `nvvm.max`: These are auto-upgraded to `select`
instructions but it is still nice to support the 16 bit variants just in
case any generators of IR are still trying to use these intrinsics.
- `nvvm.sad` added both the 16 and 64 bit variants, also marked this
instruction as speculateble. These directly correspond to the PTX
`sad.{u16,s16,u64,s64}` instructions.
- `nvvm.mulhi` added the 16 bit variants. These directly correspond to
the PTX `mul.hi.{s,u}16` instructions.
Commit: 67e0f410ff2dbac83602357619a7c931518afc73
https://github.com/llvm/llvm-project/commit/67e0f410ff2dbac83602357619a7c931518afc73
Author: Fangrui Song <i at maskray.me>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M compiler-rt/lib/dfsan/dfsan_custom.cpp
M compiler-rt/test/dfsan/custom.cpp
M compiler-rt/test/dfsan/release_shadow_space.c
Log Message:
-----------
[dfsan] Make sprintf interceptor compatible with glibc 2.37+ and musl (#78363)
snprintf interceptors call `format_buffer` with `size==~0ul`, which
may eventually lead to `snprintf(s, n, "Hello world!")` where `s+n`
wraps around. Since glibc 2.37 (https://sourceware.org/PR30441), the
snprintf call does not write the last char. musl snprintf returns -1
with EOVERFLOW when `n > INT_MAX`.
Change `size` to INT_MAX to work with glibc 2.37+ and musl.
snprintf interceptors are not changed. It's user responsibility to not
cause a compatibility issue with libc implementations.
Fix #60678
Commit: aa02002491333c42060373bc84f1ff5d2c76b4ce
https://github.com/llvm/llvm-project/commit/aa02002491333c42060373bc84f1ff5d2c76b4ce
Author: Tom Stellard <tstellar at redhat.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M .github/workflows/release-binaries.yml
A .github/workflows/release-documentation.yml
A .github/workflows/release-doxygen.yml
A .github/workflows/release-lit.yml
M .github/workflows/release-tasks.yml
M .github/workflows/set-release-binary-outputs.sh
M llvm/utils/release/github-upload-release.py
Log Message:
-----------
workflows: Refactor release-tasks.yml (#69523)
* Split out the lit release job and the documentation build job into
their own workflow files. This makes it possible to manually run these
jobs via workflow_dispatch.
* Improve tag/user validation and ensure it gets run for each release
task.
Commit: f3a4de395c167aeb8207294222c6ff5719ef6f62
https://github.com/llvm/llvm-project/commit/f3a4de395c167aeb8207294222c6ff5719ef6f62
Author: Freddy Ye <freddy.ye at intel.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/test/CodeGen/target-builtin-noerror.c
M clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
M compiler-rt/lib/builtins/cpu_model/x86.c
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/lib/TargetParser/X86TargetParser.cpp
Log Message:
-----------
[X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (#78384)
This resolves issue #65320.
This also supports clarify sapphirerapids and cooperlake for
cpu_specific/dispatch.
Commit: 558ea411599a42d2a15dd6a878700cf62a8b36e7
https://github.com/llvm/llvm-project/commit/558ea411599a42d2a15dd6a878700cf62a8b36e7
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
Log Message:
-----------
[AMDGPU] Reapply 'Sign extend simm16 in setreg intrinsic' (#78492)
We currently force users to use a negative contant in the intrinsic
call. Changing it zext would break existing programs, so just sign
extend an argument.
Commit: f6617091a982c0802e9b980f2ce7e11a1355c38b
https://github.com/llvm/llvm-project/commit/f6617091a982c0802e9b980f2ce7e11a1355c38b
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/test/CodeGen/X86/apx/adc.ll
M llvm/test/CodeGen/X86/apx/add.ll
M llvm/test/CodeGen/X86/apx/and.ll
M llvm/test/CodeGen/X86/apx/or.ll
M llvm/test/CodeGen/X86/apx/sbb.ll
M llvm/test/CodeGen/X86/apx/sub.ll
M llvm/test/CodeGen/X86/apx/xor.ll
Log Message:
-----------
[X86][test] Add --show-mc-encoding for lowering tests of NDD arithmetic instructions (#78406)
#77564 added lowering tests for NDD arithmetic instructions.
It would be great to add `--show-mc-encoding` to check the NDD variant
is selected first.
Commit: 2d92f7de800a1b1b3dca3dab1e11da712cd55f2b
https://github.com/llvm/llvm-project/commit/2d92f7de800a1b1b3dca3dab1e11da712cd55f2b
Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel-x86_64.ll
M llvm/test/CodeGen/X86/bmi-intrinsics-fast-isel.ll
M llvm/test/CodeGen/X86/bmi-x86_64.ll
M llvm/test/CodeGen/X86/bmi.ll
M llvm/test/CodeGen/X86/bmi2-x86_64.ll
M llvm/test/CodeGen/X86/bmi2.ll
M llvm/test/CodeGen/X86/shift-bmi2.ll
Log Message:
-----------
[X86] Support lowering for APX promoted BMI instructions. (#77433)
R16-R31 was added into GPRs in
https://github.com/llvm/llvm-project/pull/70958,
This patch supports the lowering for promoted BMI instructions in EVEX
space, enc/dec has been supported in
https://github.com/llvm/llvm-project/pull/73899.
RFC:
https://discourse.llvm.org/t/rfc-design-for-apx-feature-egpr-and-ndd-support/73031/4
Commit: ba81477e9cdb5384a10c700ee247562f0f6c03e6
https://github.com/llvm/llvm-project/commit/ba81477e9cdb5384a10c700ee247562f0f6c03e6
Author: Chia <sun1011jacobi at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll
M llvm/test/CodeGen/RISCV/rvv/vscale-vw-web-simplification.ll
Log Message:
-----------
Recommit "[RISCV][ISel] Combine scalable vector add/sub/mul with zero/sign extension." (#76785)
This patch was originally introduced in PR #72340, but was reverted due
to a bug on invalid extension combine.
Specifically, we resolve the case in the
https://github.com/llvm/llvm-project/pull/72340#issuecomment-1874810998
```
define <vscale x 1 x i32> @foo(<vscale x 1 x i1> %x, <vscale x 1 x i2> %y) {
%a = zext <vscale x 1 x i1> %x to <vscale x 1 x i32>
%b = zext <vscale x 1 x i1> %y to <vscale x 1 x i32>
%c = add <vscale x 1 x i32> %a, %b
ret <vscale x 1 x i32> %c
}
```
The previous patch didn't check if the semantic of `ISD::ZERO_EXTEND`
and `ISD::ZERO_EXTEND` is equivalent to the `vsext.vf2` or `vzext.vf2`
(not ensuring the SEW condition on widening Vector Arithmetic
Instructions).
Thanks for @topperc pointing out this bug.
## The original description
This PR mainly aims at resolving the below missed-optimization case,
while it could also be considered as an extension of the previous patch
https://reviews.llvm.org/D133739?id=
### Missed-Optimization Case
Compiler Explorer: https://godbolt.org/z/GzWzP7Pfh
### Source Code:
```
define <vscale x 2 x i16> @multiple_users(ptr %x, ptr %y, ptr %z) {
%a = load <vscale x 2 x i8>, ptr %x
%b = load <vscale x 2 x i8>, ptr %y
%b2 = load <vscale x 2 x i8>, ptr %z
%c = sext <vscale x 2 x i8> %a to <vscale x 2 x i16>
%d = sext <vscale x 2 x i8> %b to <vscale x 2 x i16>
%d2 = sext <vscale x 2 x i8> %b2 to <vscale x 2 x i16>
%e = mul <vscale x 2 x i16> %c, %d
%f = add <vscale x 2 x i16> %c, %d2
%g = sub <vscale x 2 x i16> %c, %d2
%h = or <vscale x 2 x i16> %e, %f
%i = or <vscale x 2 x i16> %h, %g
ret <vscale x 2 x i16> %i
}
```
### Before This Patch
```
# %bb.0:
vsetvli a3, zero, e16, mf2, ta, ma
vle8.v v8, (a0)
vle8.v v9, (a1)
vle8.v v10, (a2)
svf2 v11, v8
vsext.vf2 v8, v9
vsext.vf2 v9, v10
vmul.vv v8, v11, v8
vadd.vv v10, v11, v9
vsub.vv v9, v11, v9
vor.vv v8, v8, v10
vor.vv v8, v8, v9
ret
```
### After This Patch
```
# %bb.0:
vsetvli a3, zero, e8, mf4, ta, ma
vle8.v v8, (a0)
vle8.v v9, (a1)
vle8.v v10, (a2)
vwmul.vv v11, v8, v9
vwadd.vv v9, v8, v10
vwsub.vv v12, v8, v10
vsetvli zero, zero, e16, mf2, ta, ma
vor.vv v8, v11, v9
vor.vv v8, v8, v12
ret
```
We can see Add/Sub/Mul are combined with the Sign Extension.
### Relation to the Patch D133739
The patch D133739 introduced an optimization for folding `ADD_VL`/
`SUB_VL` / `MUL_V` with `VSEXT_VL` / `VZEXT_VL`. However, the patch did
not consider the case of non-fixed length vector case, thus this PR
could also be considered as an extension for the D133739.
Commit: 8dfc67d6724eb0af5d278f4d1d5511ca9f9e039f
https://github.com/llvm/llvm-project/commit/8dfc67d6724eb0af5d278f4d1d5511ca9f9e039f
Author: Konstantin Varlamov <varconsteq at gmail.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M libcxx/CMakeLists.txt
M libcxx/docs/BuildingLibcxx.rst
M libcxx/docs/ReleaseNotes/18.rst
M libcxx/docs/UsingLibcxx.rst
M libcxx/include/CMakeLists.txt
M libcxx/include/__assert
M libcxx/test/libcxx/assertions/modes/enabling_assertions_enables_extensive_mode.pass.cpp
M libcxx/test/libcxx/assertions/modes/override_with_debug_mode.pass.cpp
M libcxx/test/libcxx/assertions/modes/override_with_extensive_mode.pass.cpp
M libcxx/test/libcxx/assertions/modes/override_with_fast_mode.pass.cpp
M libcxx/test/libcxx/assertions/modes/override_with_unchecked_mode.pass.cpp
M libcxx/test/libcxx/containers/sequences/deque/asan_caterpillar.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.move/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.transform/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.none_of/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.merge/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.sort/stable.sort/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/numeric.ops/reduce/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/numeric.ops/transform.reduce/pstl.exception_handling.pass.cpp
M libcxx/test/support/check_assertion.h
M libcxx/utils/libcxx/header_information.py
A libcxx/vendor/llvm/default_assertion_handler.in
Log Message:
-----------
[libc++][hardening] Rework how the assertion handler can be overridden. (#77883)
Previously there were two ways to override the verbose abort function
which gets called when a hardening assertion is triggered:
- compile-time: define the `_LIBCPP_VERBOSE_ABORT` macro;
- link-time: provide a definition of `__libcpp_verbose_abort` function.
This patch adds a new configure-time approach: the vendor can provide
a path to a custom header file which will get copied into the build by
CMake and included by the library. The header must provide a definition
of the
`_LIBCPP_ASSERTION_HANDLER` macro which is what will get called should
a hardening assertion fail. As of this patch, overriding
`_LIBCPP_VERBOSE_ABORT` will still work, but the previous mechanisms
will be effectively removed in a follow-up patch, making the
configure-time mechanism the sole way of overriding the default handler.
Note that `_LIBCPP_ASSERTION_HANDLER` only gets invoked when a hardening
assertion fails. It does not affect other cases where
`_LIBCPP_VERBOSE_ABORT` is currently used (e.g. when an exception is
thrown in the `-fno-exceptions` mode).
The library provides a default version of the custom header file that
will get used if it's not overridden by the vendor. That allows us to
always test the override mechanism and reduces the difference in
configuration between the pristine version of the library and
a platform-specific version.
Commit: fdcb76f2480d2a0187641cc844e92f1d6c4b2635
https://github.com/llvm/llvm-project/commit/fdcb76f2480d2a0187641cc844e92f1d6c4b2635
Author: Kai Sasaki <lewuathe at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M mlir/lib/Conversion/ComplexToLibm/ComplexToLibm.cpp
M mlir/test/Conversion/ComplexToLibm/convert-to-libm.mlir
Log Message:
-----------
[mlir][complex] Convert complex.tan to libm ctan call (#78250)
We can convert `complex.tan` op to
[ctan/ctanf](https://sourceware.org/newlib/libm.html#ctan) function in
libm in the complex to libm conversion.
Commit: 11bf02e0192aea0ddef9a81098c2162cde82dc7e
https://github.com/llvm/llvm-project/commit/11bf02e0192aea0ddef9a81098c2162cde82dc7e
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.bf16.ll
M llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll
R llvm/test/CodeGen/AMDGPU/strict_fp_casts.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
A llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
Log Message:
-----------
DAG: Fix ABI lowering with FP promote in strictfp functions (#74405)
This was emitting non-strict casts in ABI contexts for illegal
types.
Commit: 7f2408fba3106319f64880794d555edad26d7add
https://github.com/llvm/llvm-project/commit/7f2408fba3106319f64880794d555edad26d7add
Author: antangelo <contact at antangelo.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp
Log Message:
-----------
Revert "[clang] Fix CTAD for aggregates for nested template classes" (#78541)
Reverts llvm/llvm-project#78387
The added tests are failing on several build bots.
Commit: 7e6482b3d8bbc31ddb005dd30cd50ded780a360a
https://github.com/llvm/llvm-project/commit/7e6482b3d8bbc31ddb005dd30cd50ded780a360a
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Support/Caching.cpp
M llvm/lib/Support/FileCollector.cpp
M llvm/lib/Support/GraphWriter.cpp
M llvm/lib/Support/LockFileManager.cpp
M llvm/lib/Support/Path.cpp
M llvm/lib/Support/Process.cpp
M llvm/lib/Support/Unix/Program.inc
M llvm/lib/Support/VirtualFileSystem.cpp
Log Message:
-----------
[Support] Use SmallString::operator std::string (NFC)
Commit: ac6d2f1ba06080e0eef67931703aa55f98e8c9c6
https://github.com/llvm/llvm-project/commit/ac6d2f1ba06080e0eef67931703aa55f98e8c9c6
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp
M llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
Log Message:
-----------
[DebugInfo] Use StringRef::consume_front (NFC)
Commit: 9a817b82bbef95880db900e20ddc840dc9921ced
https://github.com/llvm/llvm-project/commit/9a817b82bbef95880db900e20ddc840dc9921ced
Author: Kazu Hirata <kazu at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/include/llvm/Support/GenericLoopInfo.h
Log Message:
-----------
[Support] Use llvm::inverse_children (NFC)
Commit: d06fb0b29c7030497e0e6411cf256cabd71940c2
https://github.com/llvm/llvm-project/commit/d06fb0b29c7030497e0e6411cf256cabd71940c2
Author: Tacet <advenam.tacet at trailofbits.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M libcxx/include/string
A libcxx/test/libcxx/containers/strings/basic.string/asan_deque_integration.pass.cpp
A libcxx/test/libcxx/containers/strings/basic.string/asan_short.pass.cpp
A libcxx/test/libcxx/containers/strings/basic.string/asan_vector_integration.pass.cpp
M libcxx/test/support/asan_testing.h
Log Message:
-----------
[ASan][libc++] Turn on ASan annotations for short strings (#75882)
This commit turns on ASan annotations in `std::basic_string` for short
stings (SSO case).
Originally suggested here: https://reviews.llvm.org/D147680
String annotations added here:
https://github.com/llvm/llvm-project/pull/72677
Requires to pass CI without fails:
- https://github.com/llvm/llvm-project/pull/75845
- https://github.com/llvm/llvm-project/pull/75858
Annotating `std::basic_string` with default allocator is implemented in
https://github.com/llvm/llvm-project/pull/72677 but annotations for
short strings (SSO - Short String Optimization) are turned off there.
This commit turns them on. This also removes
`_LIBCPP_SHORT_STRING_ANNOTATIONS_ALLOWED`, because we do not plan to
support turning on and off short string annotations.
Support in ASan API exists since
https://github.com/llvm/llvm-project/commit/dd1b7b797a116eed588fd752fbe61d34deeb24e4.
You can turn off annotations for a specific allocator based on changes
from
https://github.com/llvm/llvm-project/commit/2fa1bec7a20bb23f2e6620085adb257dafaa3be0.
This PR is a part of a series of patches extending AddressSanitizer C++
container overflow detection capabilities by adding annotations, similar
to those existing in `std::vector` and `std::deque` collections. These
enhancements empower ASan to effectively detect instances where the
instrumented program attempts to access memory within a collection's
internal allocation that remains unused. This includes cases where
access occurs before or after the stored elements in `std::deque`, or
between the `std::basic_string`'s size (including the null terminator)
and capacity bounds.
The introduction of these annotations was spurred by a real-world
software bug discovered by Trail of Bits, involving an out-of-bounds
memory access during the comparison of two strings using the
`std::equals` function. This function was taking iterators
(`iter1_begin`, `iter1_end`, `iter2_begin`) to perform the comparison,
using a custom comparison function. When the `iter1` object exceeded the
length of `iter2`, an out-of-bounds read could occur on the `iter2`
object. Container sanitization, upon enabling these annotations, would
effectively identify and flag this potential vulnerability.
If you have any questions, please email:
advenam.tacet at trailofbits.com
disconnect3d at trailofbits.com
Commit: bd9e14574a80d3c022d796d373aa92bdc63f4c26
https://github.com/llvm/llvm-project/commit/bd9e14574a80d3c022d796d373aa92bdc63f4c26
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
A llvm/include/llvm/CodeGen/GlobalMerge.h
M llvm/include/llvm/CodeGen/MachinePassRegistry.def
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/test/Transforms/GlobalMerge/alignment-2.ll
M llvm/test/Transforms/GlobalMerge/alignment.ll
M llvm/test/Transforms/GlobalMerge/basic.ll
M llvm/test/Transforms/GlobalMerge/debug-info.ll
M llvm/test/Transforms/GlobalMerge/eh-filter.ll
M llvm/test/Transforms/GlobalMerge/used.ll
Log Message:
-----------
[CodeGen] Port GlobalMerge to new pass manager (#77474)
Commit: a4fe6a183883812fa8268490c987798a42c0d34b
https://github.com/llvm/llvm-project/commit/a4fe6a183883812fa8268490c987798a42c0d34b
Author: Jonas Devlieghere <jonas at devlieghere.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp
A clang/test/Driver/xros-driver.c
A clang/test/Frontend/xros-version.c
Log Message:
-----------
[clang] Upstream XROS support in Clang (#78392)
Upstream XROS support in the clang frontend and driver.
Commit: f01b6ca8bed49bdb957607456aed29ff8ee97109
https://github.com/llvm/llvm-project/commit/f01b6ca8bed49bdb957607456aed29ff8ee97109
Author: Vitaly Buka <vitalybuka at google.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M .ci/generate-buildkite-pipeline-premerge
Log Message:
-----------
[CI] Add lld as compiler-rt dependecy (#78536)
Fixing
https://buildkite.com/llvm-project/github-pull-requests/builds/30321#018d1a4a-bf72-449e-a70a-444ded875255
Co-authored-by: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
Commit: d83d1cb89cf80cda9d85e61c7b43f69446638865
https://github.com/llvm/llvm-project/commit/d83d1cb89cf80cda9d85e61c7b43f69446638865
Author: David CARLIER <devnexen at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M compiler-rt/lib/sanitizer_common/sanitizer_common_interceptors.inc
Log Message:
-----------
[compiler-rt] making getrandom call blocking. (#78340)
except when `GRND_NONBLOCK` is present in the flags.
Commit: 9917d39dfceb6a436cd0e370392f9001f30758f1
https://github.com/llvm/llvm-project/commit/9917d39dfceb6a436cd0e370392f9001f30758f1
Author: ZhangYin <zhangyin2018 at iscas.ac.cn>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M libcxx/include/experimental/__simd/aligned_tag.h
Log Message:
-----------
[libc++] <experimental/simd> Fix vector_aligned_tag (#76611)
Co-authored-by: Nikolas Klauser <nikolasklauser at berlin.de>
Commit: 8c2b0d4175dcfe669a43d0173fd00ed3c16dbdaa
https://github.com/llvm/llvm-project/commit/8c2b0d4175dcfe669a43d0173fd00ed3c16dbdaa
Author: cor3ntin <corentinjabot at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/docs/ReleaseNotes.rst
M clang/include/clang/AST/Expr.h
M clang/lib/AST/Expr.cpp
M clang/lib/Sema/TreeTransform.h
M clang/test/SemaCXX/source_location.cpp
Log Message:
-----------
[Clang] Fix dependency of SourceLocExpr. (#78436)
SourceLocExpr that may produce a function name are marked dependent so that the non-instantiated
name of a function does not get evaluated.
In GH78128, the name('s size) is used as
template argument to a `DeclRef` that is not otherwise dependent, and therefore cached and not transformed when the function is
instantiated, leading to 2 different values existing at the same time for the same function.
Fixes #78128
Commit: 8ff0ab0a2ae28c4f4d4b299683a2cc69860295a2
https://github.com/llvm/llvm-project/commit/8ff0ab0a2ae28c4f4d4b299683a2cc69860295a2
Author: Nico Weber <thakis at chromium.org>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/libcxx/include/BUILD.gn
Log Message:
-----------
[gn] attempt to port 8dfc67d6724e (__assertion_handler)
Commit: 9d1dada57741d204f8a95aa2b0c89a7242e101f1
https://github.com/llvm/llvm-project/commit/9d1dada57741d204f8a95aa2b0c89a7242e101f1
Author: Nathan Ridge <zeratul976 at hotmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang-tools-extra/clangd/unittests/DumpASTTests.cpp
M clang/lib/Tooling/Syntax/Tokens.cpp
M clang/unittests/Tooling/Syntax/TokensTest.cpp
Log Message:
-----------
[clangd] Handle an expanded token range that ends in the `eof` token in TokenBuffer::spelledForExpanded() (#78092)
Such ranges can legitimately arise in the case of invalid code, such as
a declaration missing an ending brace.
Fixes https://github.com/clangd/clangd/issues/1559
Commit: baaf0c968edd1a11ba0d1e2ae97b8578455ceed2
https://github.com/llvm/llvm-project/commit/baaf0c968edd1a11ba0d1e2ae97b8578455ceed2
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/unittests/CodeGen/CodeGenPassBuilderTest.cpp
Log Message:
-----------
[CodeGen] Support start/stop in CodeGenPassBuilder (#70912)
Add `-start/stop-before/after` support for CodeGenPassBuilder.
Part of #69879.
Commit: 361016f680abf830004ef726f816820a0c8c1950
https://github.com/llvm/llvm-project/commit/361016f680abf830004ef726f816820a0c8c1950
Author: Matheus Izvekov <mizvekov at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Support/Path.cpp
M llvm/unittests/Support/Path.cpp
Log Message:
-----------
[Path] Fix off-by-one in finding filename for win style paths (#78055)
This fixes a crash where `path::parent_path` causes an invalid access on
a string upon receiving a path that consists of a single colon.
On Windows machine, with runtime checks enabled build, upon `clang -I:
test.cc` produces:
```
Assertion failed: Index < Length && "Invalid index!", file llvm\include\llvm/ADT/StringRef.h, line 232
...
#6 0x00007ff7816201eb `anonymous namespace'::parent_path_end llvm\lib\Support\Path.cpp:144:0
#7 0x00007ff781620135 llvm::sys::path::parent_path(class llvm::StringRef, enum llvm::sys::path::Style) llvm\lib\Support\Path.cpp:470:0
```
Ideally, we can look for the last colon starting from the last
character, but we can instead start from second to last, and handle
empty paths by abusing `0 - 1 == npos`.
Commit: d24f23ed0c09f6899874ca692f7df0584d3c736c
https://github.com/llvm/llvm-project/commit/d24f23ed0c09f6899874ca692f7df0584d3c736c
Author: Sander de Smalen <sander.desmalen at arm.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/include/clang/AST/Type.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/Type.cpp
Log Message:
-----------
[Clang] NFC: Move Arm type attributes to separate trailing object. (#78424)
This decouples the Arm type attributes from other bits, which means
the data will only be allocated when a function uses these Arm
attributes.
The first patch adds the bit `HasArmTypeAttributes` to
`FunctionTypeBitfields`, which grows from 62 bits to 63 bits.
In the second patch, I've moved this bit (`HasArmTypeAttributes`) to
`FunctionTypeExtraBitfields`, because it looks like the bits in
`FunctionTypeBitfields` are precious and we really don't want that
struct
to grow beyond 64 bits.
I've split this out into two patches to explain the rationale, but those
can be squashed before merging.
Commit: c8007f904720c196775880bbcb66f4d4c2dafa57
https://github.com/llvm/llvm-project/commit/c8007f904720c196775880bbcb66f4d4c2dafa57
Author: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
A llvm/test/CodeGen/AArch64/strictfp_f16_abi_promote.ll
Log Message:
-----------
DAG: Fix chain mismanagement in SoftenFloatRes_FP_EXTEND (#74558)
Commit: c3cc09bdf8e83b86bd087e14b2dae34888422096
https://github.com/llvm/llvm-project/commit/c3cc09bdf8e83b86bd087e14b2dae34888422096
Author: Mikael Holmen <mikael.holmen at ericsson.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
Log Message:
-----------
[AsmPrinter] Fix gcc -Wparentheses warning [NFC]
Without this gcc warned
../lib/CodeGen/AsmPrinter/DwarfDebug.cpp:3585:70: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
3584 | ((&Current == &AccelDebugNames) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3585 | (Unit.getUnitDie().getTag() != dwarf::DW_TAG_type_unit)) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
3586 | "Kind is CU but TU is being processed.");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../lib/CodeGen/AsmPrinter/DwarfDebug.cpp:3589:70: warning: suggest parentheses around '&&' within '||' [-Wparentheses]
3588 | ((&Current == &AccelTypeUnitsDebugNames) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
3589 | (Unit.getUnitDie().getTag() == dwarf::DW_TAG_type_unit)) &&
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
3590 | "Kind is TU but CU is being processed.");
| ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Commit: 021def6c2278fd932d18b4d891c2e75c1d8e6f1d
https://github.com/llvm/llvm-project/commit/021def6c2278fd932d18b4d891c2e75c1d8e6f1d
Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
Date: 2024-01-17 (Wed, 17 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/test/CodeGen/AMDGPU/lds-dma-waits.ll
Log Message:
-----------
[AMDGPU] Use alias info to relax waitcounts for LDS DMA (#74537)
LDA DMA loads increase VMCNT and a load from the LDS stored must wait on
this counter to only read memory after it is written. Wait count
insertion pass does not track memory dependencies, it tracks register
dependencies. To model the LDS dependency a pseudo register is used in
the scoreboard, acting like if LDS DMA writes it and LDS load reads it.
This patch adds 8 more pseudo registers to use for independent LDS
locations if we can prove they are disjoint using alias analysis.
Fixes: SWDEV-433427
Commit: 264fd9e13e6006378b2d1de2851b39eec8e98225
https://github.com/llvm/llvm-project/commit/264fd9e13e6006378b2d1de2851b39eec8e98225
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/amdgpu-features.cl
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/TargetParser/TargetParser.cpp
Log Message:
-----------
[AMDGPU][NFC] Rename feature FP8Insts to FP8ConversionInsts (#78439)
Commit: 1b1b5251479c42c793b14fb9588545f9619b85d6
https://github.com/llvm/llvm-project/commit/1b1b5251479c42c793b14fb9588545f9619b85d6
Author: martinboehme <mboehme at google.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/SimplifyConstraints.cpp
Log Message:
-----------
[clang][dataflow] Use `Formula::isLiteral()` in a couple more places. (#78404)
Commit: f1226eea52e21b6325cf24cf0d7ccd6a517baee5
https://github.com/llvm/llvm-project/commit/f1226eea52e21b6325cf24cf0d7ccd6a517baee5
Author: martinboehme <mboehme at google.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/unittests/Analysis/FlowSensitive/TransferTest.cpp
Log Message:
-----------
[clang][dataflow] Consider `CXXDefaultInitExpr` to be an "original record ctor". (#78423)
The CFG doesn't contain a CFGElement for the
`CXXDefaultInitExpr::getInit()`, so
it makes sense to consider the `CXXDefaultInitExpr` to be the expression
that
originally constructs the object.
Commit: 9ca1a08144a3caea8fd2f45fd4930ca796cf4166
https://github.com/llvm/llvm-project/commit/9ca1a08144a3caea8fd2f45fd4930ca796cf4166
Author: Balázs Kéri <balazs.keri at ericsson.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/unittests/AST/StructuralEquivalenceTest.cpp
Log Message:
-----------
[clang][ASTImporter] Improve structural equivalence of overloadable operators. (#72242)
Operators that are overloadable may be parsed as `CXXOperatorCallExpr`
or as `UnaryOperator` (or `BinaryOperator`). This depends on the context
and can be different if a similar construct is imported into an existing
AST. The two "forms" of the operator call AST nodes should be detected
as equivalent to allow AST import of these cases.
This fix has probably other consequences because if a structure is
imported that has `CXXOperatorCallExpr` into an AST with an existing
similar structure that has `UnaryOperator` (or binary), the additional
data in the `CXXOperatorCallExpr` node is lost at the import (because
the existing node will be used). I am not sure if this can cause
problems.
Commit: 37c87d5689134392ba801a9eb28785f9f0b3e5f7
https://github.com/llvm/llvm-project/commit/37c87d5689134392ba801a9eb28785f9f0b3e5f7
Author: Paschalis Mpeis <paschalis.mpeis at arm.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
A llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
Log Message:
-----------
[LV][AArch64] LoopVectorizer allows scalable frem instructions (#76247)
LoopVectorizer is aware when a target can replace a scalable frem
instruction with a vector library call for a given VF and it returns the
relevant cost. Otherwise, it returns an invalid cost (as previously).
Add test that check costs on AArch64, when there is no vector library
available and when there is (with and without tail-folding).
NOTE: Invoking CostModel directly (not through LV) would still return
invalid costs.
Commit: 1d286ad59b9080d9503502a35f9bdb35e40f1f33
https://github.com/llvm/llvm-project/commit/1d286ad59b9080d9503502a35f9bdb35e40f1f33
Author: Mirko Brkušanin <Mirko.Brkusanin at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPU.h
A llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/test/CodeGen/AMDGPU/llc-pipeline.ll
M llvm/test/CodeGen/AMDGPU/sgpr-regalloc-flags.ll
A llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
A llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/MIR/AMDGPU/target-memoperands.mir
Log Message:
-----------
[AMDGPU] Add mark last scratch load pass (#75512)
Commit: 4f62a183d9101a90d62e2a278d0513e9d2afba43
https://github.com/llvm/llvm-project/commit/4f62a183d9101a90d62e2a278d0513e9d2afba43
Author: jeanPerier <jperier at nvidia.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M flang/lib/Optimizer/CodeGen/CodeGen.cpp
A flang/test/Fir/already-defined-free.fir
Log Message:
-----------
[flang] Allow user to define free via BIND(C) (#78428)
A user defining and using free/malloc via BIND(C) would previously cause
flang to crash when generating LLVM IR with error "redefinition of
symbol named 'free'". This was caused by flang codegen not expecting to
find a mlir::func::FuncOp definition of these function and emitting a
new mlir::LLVM::FuncOp that later conflicted when translating the
mlir::func::FuncOp.
Commit: 2a869ced61b9c148bb30c8c6b989b3d2da0c5d9a
https://github.com/llvm/llvm-project/commit/2a869ced61b9c148bb30c8c6b989b3d2da0c5d9a
Author: Ivan Kosarev <ivan.kosarev at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
M llvm/test/CodeGen/AMDGPU/fix-sgpr-copies-f16.mir
M llvm/test/CodeGen/AMDGPU/llvm.floor.f16.ll
M llvm/test/MC/AMDGPU/gfx11_asm_vop1-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_dpp8.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err-fake16.s
M llvm/test/MC/AMDGPU/gfx11_asm_vop1_t16_err.s
M llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa-fake16.s
M llvm/test/MC/AMDGPU/gfx11_unsupported_sdwa.s
M llvm/test/MC/Disassembler/AMDGPU/gfx11_dasm_vop1.txt
Log Message:
-----------
[AMDGPU][True16] Support V_FLOOR_F16. (#78446)
Commit: 9096bcc7c89491b5e26d5e275e69a8f76e2e5146
https://github.com/llvm/llvm-project/commit/9096bcc7c89491b5e26d5e275e69a8f76e2e5146
Author: LLVM GN Syncbot <llvmgnsyncbot at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn
Log Message:
-----------
[gn build] Port 1d286ad59b90
Commit: 085eae6b863881fb9fda323e5b672b04a00ed19e
https://github.com/llvm/llvm-project/commit/085eae6b863881fb9fda323e5b672b04a00ed19e
Author: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/lib/AST/ODRHash.cpp
A clang/test/Modules/pr76638.cppm
Log Message:
-----------
[C++20] [Modules] Allow to merge enums with the same underlying interger types
Close https://github.com/llvm/llvm-project/issues/76638. See the issue
for the context of the change.
Commit: 15b0fabb21af8395c1b810e7d992a869b9ef31d8
https://github.com/llvm/llvm-project/commit/15b0fabb21af8395c1b810e7d992a869b9ef31d8
Author: Luke Lau <luke at igalia.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
A llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare-asm.ll
A llvm/test/CodeGen/RISCV/rvv/riscv-codegenprepare.ll
Log Message:
-----------
[RISCV] Vectorize phi for loop carried @llvm.vector.reduce.fadd (#78244)
LLVM vector reduction intrinsics return a scalar result, but on RISC-V
vector reduction instructions write the result in the first element of a
vector register. So when a reduction in a loop uses a scalar phi, we end
up with unnecessary scalar moves:
loop:
vfmv.s.f v10, fa0
vfredosum.vs v8, v8, v10
vfmv.f.s fa0, v8
This mainly affects ordered fadd reductions, which has a scalar accumulator
operand.
This tries to vectorize any scalar phis that feed into a fadd reduction
in RISCVCodeGenPrepare, converting:
loop:
%phi = phi <float> [ ..., %entry ], [ %acc, %loop]
%acc = call float @llvm.vector.reduce.fadd.nxv4f32(float %phi, <vscale x 2 x float> %vec)
```
to
loop:
%phi = phi <vscale x 2 x float> [ ..., %entry ], [ %acc.vec, %loop]
%phi.scalar = extractelement <vscale x 2 x float> %phi, i64 0
%acc = call float @llvm.vector.reduce.fadd.nxv4f32(float %x, <vscale x 2 x float> %vec)
%acc.vec = insertelement <vscale x 2 x float> poison, float %acc.next, i64 0
Which eliminates the scalar -> vector -> scalar crossing during
instruction selection.
Commit: 51e3d2f73d8f3f5c70f0c1b6b73f62ec9c680cb4
https://github.com/llvm/llvm-project/commit/51e3d2f73d8f3f5c70f0c1b6b73f62ec9c680cb4
Author: Matthew Devereau <matthew.devereau at arm.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
A llvm/test/CodeGen/AArch64/sme-streaming-body-streaming-compatible-interface.ll
Log Message:
-----------
[AArch64][SME] Conditionally do smstart/smstop (#77113)
This patch adds conditional enabling/disabling of streaming mode for
functions which have both the aarch64_pstate_sm_compatible and
aarch64_pstate_sm_body attributes.
This combination allows callees to determine if switching streaming mode
is required instead of relying on the caller.
Commit: bc4f3e31a99ad11b385f68634aa9fbe2cbdd7031
https://github.com/llvm/llvm-project/commit/bc4f3e31a99ad11b385f68634aa9fbe2cbdd7031
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M libc/src/string/memory_utils/op_x86.h
M libc/src/string/memory_utils/utils.h
Log Message:
-----------
[libc][NFC] Selectively disable GCC warnings (#78462)
Commit: 49e3e7514309823e39627175d5337c5d5aff92c1
https://github.com/llvm/llvm-project/commit/49e3e7514309823e39627175d5337c5d5aff92c1
Author: Nikita Popov <npopov at redhat.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/IR/ConstantFold.cpp
M llvm/test/Transforms/InstSimplify/ConstProp/fp-undef.ll
Log Message:
-----------
[ConstantFold] Clean up binop identity folding
Resolve the two FIXMEs: Perform the binop identitiy fold with
AllowRHSConstant, and remove redundant folds later in the code.
Commit: e75720b477216535b14ce604be0a50e0b7a0c829
https://github.com/llvm/llvm-project/commit/e75720b477216535b14ce604be0a50e0b7a0c829
Author: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/include/clang/Basic/arm_sve.td
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create2.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create3.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_create4.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get2.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get3.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_get4.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set2.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set3.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4-bfloat.c
M clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_set4.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create2_bool.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_create4_bool.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_get2_bool.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_get4_bool.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_set2_bool.c
M clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_set4_bool.c
Log Message:
-----------
[Clang][SME] Add missing IsStreamingCompatible flag to svget, svcreate & svset (#78430)
Commit: f1fdfe6888f93b9f6dfb4689e1f3206de584ff5b
https://github.com/llvm/llvm-project/commit/f1fdfe6888f93b9f6dfb4689e1f3206de584ff5b
Author: Alexey Lapshin <a.v.lapshin at mail.ru>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/test/tools/dsymutil/ARM/DWARFLinkerParallel/accel-imported-declarations.test
M llvm/test/tools/dsymutil/ARM/call-pc-reloc.test
M llvm/test/tools/dsymutil/ARM/dwarf5-addr-base.test
M llvm/test/tools/dsymutil/ARM/dwarf5-addrx-0x0-last.test
M llvm/test/tools/dsymutil/ARM/dwarf5-dwarf4-combination-macho.test
M llvm/test/tools/dsymutil/ARM/dwarf5-macho.test
M llvm/test/tools/dsymutil/ARM/dwarf5-str-offsets-base-strx.test
M llvm/test/tools/dsymutil/ARM/empty-map.test
M llvm/test/tools/dsymutil/ARM/extern-alias.test
M llvm/test/tools/dsymutil/ARM/fat-arch-name.test
M llvm/test/tools/dsymutil/ARM/fat-arch-not-found.test
M llvm/test/tools/dsymutil/ARM/fat-dylib-update.test
M llvm/test/tools/dsymutil/ARM/inline-source.test
M llvm/test/tools/dsymutil/ARM/inlined-low_pc.c
M llvm/test/tools/dsymutil/ARM/obfuscated.test
M llvm/test/tools/dsymutil/ARM/preload.test
M llvm/test/tools/dsymutil/ARM/scattered.c
M llvm/test/tools/dsymutil/ARM/thumb.c
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/dead-stripped.cpp
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/empty-CU.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/empty_range.s
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/frame-1.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/frame-2.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/inlined-static-variable.cpp
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/keep-func.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-anon-namespace.cpp
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-fwd-declaration.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-fwd-declaration2.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-fwd-declaration3.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-member-functions.cpp
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-namespace-extension.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-nested-types1.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-nested-types2.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-parents.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-predictable-output.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-predictable-output2.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-recursive-dependence.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-string.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-template-parameters.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-two-units-in-single-file.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-types-in-subprogram1.test
M llvm/test/tools/dsymutil/X86/DWARFLinkerParallel/odr-uniquing.cpp
M llvm/test/tools/dsymutil/X86/alias.test
M llvm/test/tools/dsymutil/X86/basic-linking-bundle.test
M llvm/test/tools/dsymutil/X86/basic-linking-x86.test
M llvm/test/tools/dsymutil/X86/basic-lto-dw4-linking-x86.test
M llvm/test/tools/dsymutil/X86/basic-lto-linking-x86.test
M llvm/test/tools/dsymutil/X86/basic-with-libfat-test.test
M llvm/test/tools/dsymutil/X86/call-site-entry-linking.test
M llvm/test/tools/dsymutil/X86/call-site-entry-reloc.test
M llvm/test/tools/dsymutil/X86/common-sym-multi.test
M llvm/test/tools/dsymutil/X86/common-sym.test
M llvm/test/tools/dsymutil/X86/custom-line-table.test
M llvm/test/tools/dsymutil/X86/darwin-bundle.test
M llvm/test/tools/dsymutil/X86/debug-loc-base-addr.test
M llvm/test/tools/dsymutil/X86/dwarf4-linetable.test
M llvm/test/tools/dsymutil/X86/dwarf5-addrx.test
M llvm/test/tools/dsymutil/X86/dwarf5-call-site-entry-reloc.test
M llvm/test/tools/dsymutil/X86/dwarf5-dw-op-addrx.test
M llvm/test/tools/dsymutil/X86/dwarf5-linetable.test
M llvm/test/tools/dsymutil/X86/dwarf5-loclists.test
M llvm/test/tools/dsymutil/X86/dwarf5-rnglists.test
M llvm/test/tools/dsymutil/X86/eh_frame.test
M llvm/test/tools/dsymutil/X86/fat-archive-input-i386.test
M llvm/test/tools/dsymutil/X86/fat-object-input-x86_64.test
M llvm/test/tools/dsymutil/X86/fat-object-input-x86_64h.test
M llvm/test/tools/dsymutil/X86/generate-empty-CU.test
M llvm/test/tools/dsymutil/X86/global_downgraded_to_static.c
M llvm/test/tools/dsymutil/X86/inlined-static-variable.cpp
M llvm/test/tools/dsymutil/X86/label.test
M llvm/test/tools/dsymutil/X86/label2.test
M llvm/test/tools/dsymutil/X86/lc_build_version.test
M llvm/test/tools/dsymutil/X86/linker-llvm-union-fwd-decl.test
M llvm/test/tools/dsymutil/X86/location-expression.test
M llvm/test/tools/dsymutil/X86/mismatch.m
M llvm/test/tools/dsymutil/X86/modules-dwarf-version.m
M llvm/test/tools/dsymutil/X86/modules-empty.m
M llvm/test/tools/dsymutil/X86/multiple-inputs.test
M llvm/test/tools/dsymutil/X86/object-prefix-path.test
M llvm/test/tools/dsymutil/X86/odr-uniquing.cpp
M llvm/test/tools/dsymutil/X86/op-convert-offset.test
M llvm/test/tools/dsymutil/X86/op-convert.test
M llvm/test/tools/dsymutil/X86/reflection-dump.test
M llvm/test/tools/dsymutil/X86/remarks-linking-archive.text
M llvm/test/tools/dsymutil/X86/remarks-linking-bundle-empty.test
M llvm/test/tools/dsymutil/X86/remarks-linking-bundle.test
M llvm/test/tools/dsymutil/X86/remarks-linking-fat-bundle.test
M llvm/test/tools/dsymutil/X86/reproducer.test
M llvm/test/tools/dsymutil/X86/statistics.test
M llvm/test/tools/dsymutil/X86/swift-ast-x86_64.test
M llvm/test/tools/dsymutil/X86/swift-dwarf-loc.test
M llvm/test/tools/dsymutil/X86/tail-call-linking.test
M llvm/test/tools/dsymutil/X86/thinlto.test
M llvm/test/tools/dsymutil/X86/timestamp-mismatch.test
M llvm/test/tools/dsymutil/X86/tls-variable.test
M llvm/test/tools/dsymutil/X86/verify.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/accelerator-dwarf4.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/accelerator-dwarf5.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf4-macro-short.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf4-macro.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-addresses.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-attributes.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-line-str.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-loclists.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-macro-opcodeop.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-macro-short.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-macro.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/dwarf5-rnglists.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/gc-default.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/gc-func-overlapping-address-ranges.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/gc-maxpc.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/gc-no-garbage.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/gc-unit-overlapping-address-ranges.test
M llvm/test/tools/llvm-dwarfutil/ELF/X86/verify.test
M llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
M llvm/tools/dsymutil/LinkUtils.h
M llvm/tools/dsymutil/Options.td
M llvm/tools/dsymutil/dsymutil.cpp
M llvm/tools/llvm-dwarfutil/DebugInfoLinker.cpp
M llvm/tools/llvm-dwarfutil/Options.h
M llvm/tools/llvm-dwarfutil/Options.td
M llvm/tools/llvm-dwarfutil/llvm-dwarfutil.cpp
Log Message:
-----------
[dsymutil][llvm-dwarfutil] Rename command line options to avoid using vendor names. (#78135)
This patch renames values of dsymutil/llvm-dwarfutil options:
--linker apple -> --linker classic
--linker llvm -> --linker parallel
The purpose to rename options is to avoid using vendor names and to
match with library names. It should be safe to rename options at current
stage as they are not seemed widely used(we may not preserve backward
compatibility).
Commit: 172dbdf9312a15b449954e43623afc28240f50dd
https://github.com/llvm/llvm-project/commit/172dbdf9312a15b449954e43623afc28240f50dd
Author: pvanhout <pierre.vanhoutryve at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/include/llvm/BinaryFormat/ELF.h
Log Message:
-----------
[AMDGPU][ELF] Reserve 0x4f and 0x50 EFLAGS
Commit: c111dc72e907d8aeb85b42e2251ea55130199681
https://github.com/llvm/llvm-project/commit/c111dc72e907d8aeb85b42e2251ea55130199681
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
Log Message:
-----------
[AMDGPU] Allow potentially negative flat scratch offsets on GFX12 (#78193)
https://github.com/llvm/llvm-project/pull/70634 has disabled use
of potentially negative scratch offsets, but we can use it on GFX12.
---------
Co-authored-by: Stanislav Mekhanoshin <Stanislav.Mekhanoshin at amd.com>
Commit: 4c65787f1e45199713f71f63817651ff2decd96c
https://github.com/llvm/llvm-project/commit/4c65787f1e45199713f71f63817651ff2decd96c
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-gfx11-param-err.cl
M clang/test/CodeGenOpenCL/builtins-amdgcn-gfx12.cl
Log Message:
-----------
[AMDGPU] Add GFX12 __builtin_amdgcn_s_sleep_var (#77926)
Commit: 9ca36932b5350a9d8d7ddf6c26ff8c1a81467430
https://github.com/llvm/llvm-project/commit/9ca36932b5350a9d8d7ddf6c26ff8c1a81467430
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/docs/AMDGPUUsage.rst
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/remat-sop.mir
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
Log Message:
-----------
[AMDGPU] Work around s_getpc_b64 zero extending on GFX12 (#78186)
Commit: ba52f06f9d92c7ca04b440f618f8d352ea121fcc
https://github.com/llvm/llvm-project/commit/ba52f06f9d92c7ca04b440f618f8d352ea121fcc
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/add.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_global_pointer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_raw_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomic_optimizations_struct_buffer.ll
M llvm/test/CodeGen/AMDGPU/atomicrmw-expand.ll
M llvm/test/CodeGen/AMDGPU/atomics_cond_sub.ll
M llvm/test/CodeGen/AMDGPU/cgp-addressing-modes-smem.ll
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.global.ll
M llvm/test/CodeGen/AMDGPU/fast-unaligned-load-store.private.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-i8-i16.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch-svs.ll
M llvm/test/CodeGen/AMDGPU/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/fmaximum.ll
M llvm/test/CodeGen/AMDGPU/fminimum.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-flat-atomics.ll
M llvm/test/CodeGen/AMDGPU/fp-min-max-num-global-atomics.ll
M llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_loads.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-load.ll
M llvm/test/CodeGen/AMDGPU/global-saddr-store.ll
M llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.cond.sub.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.global.atomic.ordered.add.b64.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.a16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.flt.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.getlod.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.msaa.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.d16.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.dim.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.encode.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.direct.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.lds.param.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.wait.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.buffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.sleep.var.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.buffer.load.format.v3f16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.load.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll
M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.ll
M llvm/test/CodeGen/AMDGPU/llvm.mulo.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-f64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i16.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i32.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i64.ll
M llvm/test/CodeGen/AMDGPU/load-constant-i8.ll
M llvm/test/CodeGen/AMDGPU/loop-prefetch-data.ll
M llvm/test/CodeGen/AMDGPU/mad_64_32.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-nontemporal.ll
M llvm/test/CodeGen/AMDGPU/memory-legalizer-private-volatile.ll
M llvm/test/CodeGen/AMDGPU/mul.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
M llvm/test/CodeGen/AMDGPU/offset-split-global.ll
M llvm/test/CodeGen/AMDGPU/readcyclecounter.ll
M llvm/test/CodeGen/AMDGPU/s-getpc-b64-remat.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
M llvm/test/CodeGen/AMDGPU/waitcnt-global-inv-wb.mir
Log Message:
-----------
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
Update SIMemoryLegalizer and SIInsertWaitcnts to use separate wait
instructions per counter (e.g. S_WAIT_LOADCNT) and split VMCNT into
separate LOADCNT, SAMPLECNT and BVHCNT counters.
Commit: 40d952b8748bf5c4a97fc82296e1fc050388472f
https://github.com/llvm/llvm-project/commit/40d952b8748bf5c4a97fc82296e1fc050388472f
Author: Florian Hahn <flo at fhahn.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
M llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
M llvm/test/CodeGen/AArch64/bfis-in-loop.ll
M llvm/test/CodeGen/X86/inline-spiller-impdef-on-implicit-def-regression.ll
Log Message:
-----------
[CGP] Avoid replacing a free ext with multiple other exts. (#77094)
Replacing a free extension with 2 or more extensions unnecessarily
increases the number of IR instructions without providing any benefits.
It also unnecessarily causes operations to be performed on wider types
than necessary.
In some cases, the extra extensions also pessimize codegen (see
bfis-in-loop.ll).
The changes in arm64-codegen-prepare-extload.ll also show that we avoid
promotions that should only be performed in stress mode.
PR: https://github.com/llvm/llvm-project/pull/77094
Commit: 667e58a72e0d81abe0ab3500b5d5563b6a598e7f
https://github.com/llvm/llvm-project/commit/667e58a72e0d81abe0ab3500b5d5563b6a598e7f
Author: Utkarsh Saxena <usx at google.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/include/clang/Sema/Sema.h
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/test/SemaCXX/coro-lifetimebound.cpp
M clang/test/SemaCXX/coro-return-type-and-wrapper.cpp
Log Message:
-----------
[coroutines][coro_lifetimebound] Detect lifetime issues with lambda captures (#77066)
### Problem
```cpp
co_task<int> coro() {
int a = 1;
auto lamb = [a]() -> co_task<int> {
co_return a; // 'a' in the lambda object dies after the iniital_suspend in the lambda coroutine.
}();
co_return co_await lamb;
}
```
[use-after-free](https://godbolt.org/z/GWPEovWWc)
Lambda captures (even by value) are prone to use-after-free once the
lambda object dies. In the above example, the lambda object appears only
as a temporary in the call expression. It dies after the first
suspension (`initial_suspend`) in the lambda.
On resumption in `co_await lamb`, the lambda accesses `a` which is part
of the already-dead lambda object.
---
### Solution
This problem can be formulated by saying that the `this` parameter of
the lambda call operator is a lifetimebound parameter. The lambda object
argument should therefore live atleast as long as the return object.
That said, this requirement does not hold if the lambda does not have a
capture list. In principle, the coroutine frame still has a reference to
a dead lambda object, but it is easy to see that the object would not be
used in the lambda-coroutine body due to no capture list.
It is safe to use this pattern inside a`co_await` expression due to the
lifetime extension of temporaries. Example:
```cpp
co_task<int> coro() {
int a = 1;
int res = co_await [a]() -> co_task<int> { co_return a; }();
co_return res;
}
```
---
### Background
This came up in the discussion with seastar folks on
[RFC](https://discourse.llvm.org/t/rfc-lifetime-bound-check-for-parameters-of-coroutines/74253/19?u=usx95).
This is a fairly common pattern in continuation-style-passing (CSP)
async programming involving futures and continuations. Document ["Lambda
coroutine
fiasco"](https://github.com/scylladb/seastar/blob/master/doc/lambda-coroutine-fiasco.md)
by Seastar captures the problem.
This pattern makes the migration from CSP-style async programming to
coroutines very bugprone.
Fixes https://github.com/llvm/llvm-project/issues/76995
---------
Co-authored-by: Chuanqi Xu <yedeng.yd at linux.alibaba.com>
Commit: d5b2e41e208a1176212f0a08313d2a3dad5e5bb6
https://github.com/llvm/llvm-project/commit/d5b2e41e208a1176212f0a08313d2a3dad5e5bb6
Author: Paul Osmialowski <pawel.osmialowski at arm.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M openmp/runtime/src/include/omp_lib.h.var
Log Message:
-----------
[OpenMP][omp_lib] Restore compatibility with more restrictive Fortran compilers (#77780)
The most recent changes to `omp_lib.h.var` have re-introduced some
compatibility issues that had to be fixed due to the similar changes in
the past. Namely:
1. D120707 has removed the "use omp_lib_kinds" statement and replaced it
with import
2. D114537 added line continuation to the long lines
This patch introduces the same kind of changes in order to restore
compatibility with some more restrictive Fortran compilers so their
users could still benefit from the LLVM's OpenMP Fortran library.
Commit: 779af9b713d78b60e724e2a14c6490045b13b640
https://github.com/llvm/llvm-project/commit/779af9b713d78b60e724e2a14c6490045b13b640
Author: Jie Fu <jiefu at tencent.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
Log Message:
-----------
[AMDGPU] Fix -Wunused-variable in SIInsertWaitcnts.cpp (NFC)
llvm-project/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp:1539:10:
error: unused variable 'SWaitInst' [-Werror,-Wunused-variable]
auto SWaitInst =
^
1 error generated.
Commit: cf799b3d3badbcb0c028266daa73043c0d0462c1
https://github.com/llvm/llvm-project/commit/cf799b3d3badbcb0c028266daa73043c0d0462c1
Author: Alexey Lapshin <a.v.lapshin at mail.ru>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h
A llvm/include/llvm/DWARFLinker/IndexedValuesMap.h
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h
R llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h
Log Message:
-----------
[DWARFLinker][NFC] Move common code into the base library: IndexedValuesMap. (#77437)
This patch is extracted from #74725.
Both dwarflinkers contain similar classes for indexed values. Move the
code into the DWARFLinkerBase.
Commit: d12dffacaa838cbdd30454e49214f40d2ec1cc50
https://github.com/llvm/llvm-project/commit/d12dffacaa838cbdd30454e49214f40d2ec1cc50
Author: Simon Pilgrim <llvm-dev at redking.me.uk>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86MCInstLower.cpp
Log Message:
-----------
[X86] Add X86::getConstantFromPool helper function to replace duplicate implementations.
We had the same helper function in shuffle decode / vector constant code - move this to X86InstrInfo to avoid duplication.
Commit: a48c1bda74038c81c19e4508fb1d1e84f3ae690a
https://github.com/llvm/llvm-project/commit/a48c1bda74038c81c19e4508fb1d1e84f3ae690a
Author: paperchalice <liujunchang97 at outlook.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
M llvm/include/llvm/CodeGen/TargetPassConfig.h
M llvm/lib/CodeGen/TargetPassConfig.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/unittests/CodeGen/CodeGenPassBuilderTest.cpp
Log Message:
-----------
Revert "[CodeGen] Support start/stop in CodeGenPassBuilder" (#78567)
Reverts llvm/llvm-project#70912. This breaks some bazel tests.
Commit: 64e94438a416b2ac630f247606a992442d6b0e20
https://github.com/llvm/llvm-project/commit/64e94438a416b2ac630f247606a992442d6b0e20
Author: Congcong Cai <congcongcai0907 at 163.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/test/Transforms/InstCombine/mul.ll
Log Message:
-----------
[InstCombine] combine mul(abs(x),abs(y)) to abs(mul(x,y)) (#78395)
Fixes: https://github.com/llvm/llvm-project/issues/78076
Alive2 Proof: https://alive2.llvm.org/ce/z/XEDy0f
Commit: 9acc4042300a92856527169b28c43cebf179d6d5
https://github.com/llvm/llvm-project/commit/9acc4042300a92856527169b28c43cebf179d6d5
Author: Yingwei Zheng <dtcxzyw2333 at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/test/Transforms/InstCombine/funnel.ll
Log Message:
-----------
[InstCombine] Recognize more rotation patterns (#78107)
InstCombine already handles the pattern `(shl ShVal, (X & (Width - 1)))
| (lshr ShVal, ((-X) & (Width - 1)))`. Under certain circumstances, `X &
(Width - 1)` will be simplified to `X`. Therefore, this patch adds
support for the pattern `(shl ShVal, X) | (lshr ShVal, ((-X) & (Width -
1)))`.
Alive2: https://alive2.llvm.org/ce/z/P7JQ2V
Commit: 11ec512f444986c5cf09ad8b5c01a93063b21c4a
https://github.com/llvm/llvm-project/commit/11ec512f444986c5cf09ad8b5c01a93063b21c4a
Author: Guillaume Chatelet <gchatelet at google.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M libc/src/__support/FPUtil/BasicOperations.h
M libc/src/__support/FPUtil/DivisionAndRemainderOperations.h
M libc/src/__support/FPUtil/FPBits.h
M libc/src/__support/FPUtil/ManipulationFunctions.h
M libc/src/__support/FPUtil/NearestIntegerOperations.h
M libc/src/__support/FPUtil/NormalFloat.h
M libc/src/__support/FPUtil/dyadic_float.h
M libc/src/__support/FPUtil/fpbits_str.h
M libc/src/__support/FPUtil/generic/FMA.h
M libc/src/__support/FPUtil/generic/FMod.h
M libc/src/__support/FPUtil/generic/sqrt.h
M libc/src/__support/FPUtil/generic/sqrt_80_bit_long_double.h
M libc/src/__support/float_to_string.h
M libc/src/__support/str_to_float.h
M libc/src/math/generic/acosf.cpp
M libc/src/math/generic/asinf.cpp
M libc/src/math/generic/atanf.cpp
M libc/src/math/generic/atanhf.cpp
M libc/src/math/generic/cosf.cpp
M libc/src/math/generic/coshf.cpp
M libc/src/math/generic/erff.cpp
M libc/src/math/generic/exp10f_impl.h
M libc/src/math/generic/exp2f_impl.h
M libc/src/math/generic/expf.cpp
M libc/src/math/generic/expm1.cpp
M libc/src/math/generic/expm1f.cpp
M libc/src/math/generic/inv_trigf_utils.h
M libc/src/math/generic/log.cpp
M libc/src/math/generic/log10.cpp
M libc/src/math/generic/log10f.cpp
M libc/src/math/generic/log1p.cpp
M libc/src/math/generic/log1pf.cpp
M libc/src/math/generic/log2.cpp
M libc/src/math/generic/log2f.cpp
M libc/src/math/generic/logf.cpp
M libc/src/math/generic/powf.cpp
M libc/src/math/generic/sinf.cpp
M libc/src/math/generic/sinhf.cpp
M libc/src/math/generic/tanhf.cpp
M libc/src/stdio/printf_core/float_dec_converter.h
M libc/src/stdio/printf_core/float_hex_converter.h
M libc/src/stdio/printf_core/float_inf_nan_converter.h
M libc/test/UnitTest/FPMatcher.h
M libc/test/src/__support/FPUtil/fpbits_test.cpp
M libc/test/src/math/FDimTest.h
M libc/test/src/math/FmaTest.h
M libc/test/src/math/HypotTest.h
M libc/test/src/math/ILogbTest.h
M libc/test/src/math/LdExpTest.h
M libc/test/src/math/NextAfterTest.h
M libc/test/src/math/RIntTest.h
M libc/test/src/math/RemQuoTest.h
M libc/test/src/math/RoundToIntegerTest.h
M libc/test/src/math/atanhf_test.cpp
M libc/test/src/math/smoke/FDimTest.h
M libc/test/src/math/smoke/FmaTest.h
M libc/test/src/math/smoke/HypotTest.h
M libc/test/src/math/smoke/ILogbTest.h
M libc/test/src/math/smoke/LdExpTest.h
M libc/test/src/math/smoke/NextAfterTest.h
M libc/test/src/math/smoke/NextTowardTest.h
M libc/test/src/math/smoke/RIntTest.h
M libc/test/src/math/smoke/RemQuoTest.h
M libc/test/src/math/smoke/RoundToIntegerTest.h
M libc/test/src/math/smoke/atanhf_test.cpp
M libc/test/src/stdlib/strtold_test.cpp
M libc/test/src/time/difftime_test.cpp
Log Message:
-----------
[libc][NFC] Introduce a Sign type for FPBits (#78500)
Another patch is needed to cover `DyadicFloat` and `NormalFloat`
constructors.
Commit: 18d0a7e4c0d085de4e652e359bdd6778c43ec9bf
https://github.com/llvm/llvm-project/commit/18d0a7e4c0d085de4e652e359bdd6778c43ec9bf
Author: Timm Baeder <tbaeder at redhat.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/test/AST/Interp/complex.cpp
Log Message:
-----------
[clang][Interp] Implement ComplexToReal casts (#77294)
Add a new emitComplexReal() helper function and use that for the new
casts as well as the old __real implementation.
Commit: 28b7e498b6a1dbfa1ac249acec45f948665ba58e
https://github.com/llvm/llvm-project/commit/28b7e498b6a1dbfa1ac249acec45f948665ba58e
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-err.cl
A clang/test/CodeGenOpenCL/builtins-amdgcn-dl-insts-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.dot4.f32.ll
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp16_err.s
M llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3p_dpp8_err.s
A llvm/test/MC/AMDGPU/gfx12_asm_vop3p_err.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp16.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3p_dpp8.txt
Log Message:
-----------
AMDGPU/GFX12: Add new dot4 fp8/bf8 instructions (#77892)
Endoding is VOP3P. Tagged as deep/machine learning instructions. i32
type (v4fp8 or v4bf8 packed in i32) is used for src0 and src1. src0 and
src1 have no src_modifiers. src2 is f32 and has src_modifiers: f32
fneg(neg_lo[2]) and f32 fabs(neg_hi[2]).
---------
Co-authored-by: Petar Avramovic <Petar.Avramovic at amd.com>
Commit: 3e6589f21c8088d823377b648aaa1a20ec1bc3d5
https://github.com/llvm/llvm-project/commit/3e6589f21c8088d823377b648aaa1a20ec1bc3d5
Author: Mariusz Sikora <mariusz.sikora at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M clang/test/CodeGenOpenCL/amdgpu-features.cl
A clang/test/CodeGenOpenCL/builtins-fp-atomics-gfx12.cl
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/TargetParser/TargetParser.cpp
A llvm/test/CodeGen/AMDGPU/fp-atomics-gfx1200.ll
A llvm/test/CodeGen/AMDGPU/llvm.amdgcn.image.atomic.pk.add.ll
M llvm/test/MC/AMDGPU/gfx11_unsupported.s
M llvm/test/MC/AMDGPU/gfx12_asm_ds.s
M llvm/test/MC/AMDGPU/gfx12_asm_vbuffer_mubuf.s
M llvm/test/MC/AMDGPU/gfx12_asm_vflat.s
M llvm/test/MC/AMDGPU/gfx12_asm_vimage.s
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_ds.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vbuffer_mubuf.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vflat.txt
M llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vimage.txt
Log Message:
-----------
[AMDGPU][GFX12] Add 16 bit atomic fadd instructions (#75917)
- image_atomic_pk_add_f16
- image_atomic_pk_add_bf16
- ds_pk_add_bf16
- ds_pk_add_f16
- ds_pk_add_rtn_bf16
- ds_pk_add_rtn_f16
- flat_atomic_pk_add_f16
- flat_atomic_pk_add_bf16
- global_atomic_pk_add_f16
- global_atomic_pk_add_bf16
- buffer_atomic_pk_add_f16
- buffer_atomic_pk_add_bf16
Commit: f4fbbebb5edcaad459ce154c011f71fc38fe4052
https://github.com/llvm/llvm-project/commit/f4fbbebb5edcaad459ce154c011f71fc38fe4052
Author: Vlad Serebrennikov <serebrennikov.vladislav at gmail.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
A clang/test/CXX/drs/dr1807.cpp
M clang/test/CXX/drs/dr18xx.cpp
M clang/www/cxx_dr_status.html
Log Message:
-----------
[clang] Add test for CWG1807 (#77637)
The test checks that objects in arrays are destructed in reverse order during stack unwinding.
This patch is trying to establish a precedent how codegen tests for C++ defect report test suite should be written. Refer to PR for exact reasoning.
Commit: 0a3a0ea5914cb4633f4f4c14f1ddc46ce067061a
https://github.com/llvm/llvm-project/commit/0a3a0ea5914cb4633f4f4c14f1ddc46ce067061a
Author: Jay Foad <jay.foad at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/test/CodeGen/AMDGPU/clamp.ll
M llvm/test/CodeGen/AMDGPU/fcanonicalize.ll
M llvm/test/CodeGen/AMDGPU/omod.ll
Log Message:
-----------
[AMDGPU] Update uses of new VOP2 pseudos for GFX12 (#78155)
New pseudos were added for instructions that were natively VOP3 on
GFX11: V_ADD_F64_pseudo, V_MUL_F64_pseudo, V_MIN_NUM_F64, V_MAX_NUM_F64,
V_LSHLREV_B64_pseudo
---------
Co-authored-by: Mirko Brkusanin <Mirko.Brkusanin at amd.com>
Commit: e5a34f9226ef56669f670dc32661934ee3e56f37
https://github.com/llvm/llvm-project/commit/e5a34f9226ef56669f670dc32661934ee3e56f37
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M flang/lib/Lower/OpenMP.cpp
Log Message:
-----------
[Flang][OpenMP] Push genEval closer to leaf lowering functions (#77760)
This moves the lowering of the nested evaluations all the way to the
bottom of the call stack. This PR does not attempt to change the leaf
lowering functions beyond placing the call to `genEval` in there.
Whether the nested evaluations should be lowered for any given op
depends on the context in which that op is created, hence a `genNested`
parameter was added.
Contexts in which nested evaluations should not be lowered are during
lowering of composite constructs, such as PARALLEL SECTIONS. This
particular case is considered a block construct tied to the SECTIONS
directive, and the lowering code will first create an empty parallel op,
and then recursively lower the SECTIONS code. Similar situations occur
when lowering most (if not all) compound/composite constructs.
Recursive lowering [4/5]
Commit: 00ad95a9211bb8fb88de779eba7e6c2acbf810c4
https://github.com/llvm/llvm-project/commit/00ad95a9211bb8fb88de779eba7e6c2acbf810c4
Author: Krzysztof Parzyszek <Krzysztof.Parzyszek at amd.com>
Date: 2024-01-18 (Thu, 18 Jan 2024)
Changed paths:
M .ci/generate-buildkite-pipeline-premerge
M .github/CODEOWNERS
A .github/dependabot.yml
M .github/workflows/docs.yml
M .github/workflows/issue-subscriber.yml
M .github/workflows/libclang-python-tests.yml
M .github/workflows/libcxx-build-and-test.yaml
M .github/workflows/llvm-project-tests.yml
M .github/workflows/new-prs.yml
M .github/workflows/pr-subscriber.yml
M .github/workflows/release-binaries.yml
A .github/workflows/release-documentation.yml
A .github/workflows/release-doxygen.yml
A .github/workflows/release-lit.yml
M .github/workflows/release-tasks.yml
M .github/workflows/set-release-binary-outputs.sh
M bolt/tools/bat-dump/bat-dump.cpp
M bolt/tools/driver/llvm-bolt.cpp
M bolt/tools/heatmap/heatmap.cpp
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.cpp
M clang-tools-extra/clang-tidy/misc/UnusedUsingDeclsCheck.h
M clang-tools-extra/clang-tidy/performance/ForRangeCopyCheck.cpp
M clang-tools-extra/clang-tidy/readability/AvoidNestedConditionalOperatorCheck.cpp
M clang-tools-extra/clang-tidy/readability/ImplicitBoolConversionCheck.cpp
M clang-tools-extra/clang-tidy/utils/FixItHintUtils.cpp
M clang-tools-extra/clang-tidy/utils/FixItHintUtils.h
M clang-tools-extra/clangd/unittests/DumpASTTests.cpp
M clang-tools-extra/docs/ReleaseNotes.rst
M clang-tools-extra/modularize/ModularizeUtilities.cpp
M clang-tools-extra/test/clang-tidy/checkers/performance/for-range-copy.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-allow-in-conditions.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion-cxx98.cpp
M clang-tools-extra/test/clang-tidy/checkers/readability/implicit-bool-conversion.cpp
M clang/bindings/python/README.txt
M clang/bindings/python/clang/cindex.py
M clang/cmake/caches/Fuchsia-stage2.cmake
M clang/cmake/caches/Fuchsia.cmake
A clang/docs/BoundsSafety.rst
A clang/docs/BoundsSafetyImplPlans.rst
M clang/docs/CommandGuide/clang.rst
M clang/docs/LibASTMatchersReference.html
M clang/docs/LibASTMatchersTutorial.rst
M clang/docs/ReleaseNotes.rst
M clang/docs/UsersManual.rst
M clang/docs/index.rst
A clang/include/clang/AST/APNumericStorage.h
M clang/include/clang/AST/Decl.h
M clang/include/clang/AST/DeclBase.h
M clang/include/clang/AST/DeclCXX.h
M clang/include/clang/AST/Expr.h
M clang/include/clang/AST/Type.h
M clang/include/clang/ASTMatchers/ASTMatchers.h
M clang/include/clang/ASTMatchers/ASTMatchersInternal.h
M clang/include/clang/Analysis/FlowSensitive/ControlFlowContext.h
M clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h
M clang/include/clang/Analysis/FlowSensitive/Formula.h
M clang/include/clang/Basic/Attr.td
M clang/include/clang/Basic/BuiltinsAMDGPU.def
M clang/include/clang/Basic/DiagnosticParseKinds.td
M clang/include/clang/Basic/DiagnosticSemaKinds.td
M clang/include/clang/Basic/OpenACCKinds.h
M clang/include/clang/Basic/arm_sve.td
M clang/include/clang/Driver/Options.td
M clang/include/clang/Lex/Lexer.h
M clang/include/clang/Parse/Parser.h
M clang/include/clang/Sema/Sema.h
M clang/lib/AST/ASTContext.cpp
M clang/lib/AST/ASTStructuralEquivalence.cpp
M clang/lib/AST/Decl.cpp
M clang/lib/AST/DeclCXX.cpp
M clang/lib/AST/Expr.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.cpp
M clang/lib/AST/Interp/ByteCodeExprGen.h
M clang/lib/AST/ODRHash.cpp
M clang/lib/AST/Type.cpp
M clang/lib/ASTMatchers/ASTMatchersInternal.cpp
M clang/lib/ASTMatchers/Dynamic/Registry.cpp
M clang/lib/Analysis/ExprMutationAnalyzer.cpp
M clang/lib/Analysis/FlowSensitive/ControlFlowContext.cpp
M clang/lib/Analysis/FlowSensitive/DataflowAnalysisContext.cpp
M clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp
M clang/lib/Analysis/FlowSensitive/SimplifyConstraints.cpp
M clang/lib/Analysis/FlowSensitive/Value.cpp
M clang/lib/Basic/Targets.cpp
M clang/lib/Basic/Targets/AArch64.cpp
M clang/lib/Basic/Targets/AMDGPU.h
M clang/lib/Basic/Targets/OSTargets.h
M clang/lib/Basic/Targets/RISCV.cpp
M clang/lib/Basic/Targets/RISCV.h
M clang/lib/Basic/Targets/X86.cpp
M clang/lib/Basic/Warnings.cpp
M clang/lib/CodeGen/CGBuiltin.cpp
M clang/lib/CodeGen/CGObjC.cpp
M clang/lib/CodeGen/CGStmt.cpp
M clang/lib/CodeGen/CodeGenModule.cpp
M clang/lib/CodeGen/TargetInfo.h
M clang/lib/CodeGen/Targets/RISCV.cpp
M clang/lib/CodeGen/Targets/X86.cpp
M clang/lib/Driver/Driver.cpp
M clang/lib/Driver/ToolChains/Arch/AArch64.cpp
M clang/lib/Driver/ToolChains/Arch/ARM.cpp
M clang/lib/Driver/ToolChains/Arch/RISCV.cpp
M clang/lib/Driver/ToolChains/Clang.cpp
M clang/lib/Driver/ToolChains/Darwin.cpp
M clang/lib/Driver/ToolChains/Darwin.h
M clang/lib/Driver/ToolChains/Gnu.cpp
M clang/lib/Driver/ToolChains/Hurd.cpp
M clang/lib/Format/ContinuationIndenter.cpp
M clang/lib/Format/FormatToken.h
M clang/lib/Format/FormatTokenLexer.cpp
M clang/lib/Format/FormatTokenLexer.h
M clang/lib/Headers/arm_acle.h
M clang/lib/Headers/ia32intrin.h
M clang/lib/Headers/immintrin.h
M clang/lib/Headers/llvm_libc_wrappers/string.h
M clang/lib/Lex/UnicodeCharSets.h
M clang/lib/Parse/ParseDecl.cpp
M clang/lib/Parse/ParseDeclCXX.cpp
M clang/lib/Parse/ParseExpr.cpp
M clang/lib/Parse/ParseExprCXX.cpp
M clang/lib/Parse/ParseObjc.cpp
M clang/lib/Parse/ParseOpenACC.cpp
M clang/lib/Parse/Parser.cpp
M clang/lib/Sema/SemaCoroutine.cpp
M clang/lib/Sema/SemaDecl.cpp
M clang/lib/Sema/SemaDeclAttr.cpp
M clang/lib/Sema/SemaDeclCXX.cpp
M clang/lib/Sema/SemaDeclObjC.cpp
M clang/lib/Sema/SemaExpr.cpp
M clang/lib/Sema/SemaExprCXX.cpp
M clang/lib/Sema/SemaInit.cpp
M clang/lib/Sema/SemaLambda.cpp
M clang/lib/Sema/SemaObjCProperty.cpp
M clang/lib/Sema/SemaOpenMP.cpp
M clang/lib/Sema/SemaOverload.cpp
M clang/lib/Sema/SemaStmt.cpp
M clang/lib/Sema/SemaTemplate.cpp
M clang/lib/Sema/SemaTemplateInstantiateDecl.cpp
M clang/lib/Sema/SemaType.cpp
M clang/lib/Sema/TreeTransform.h
M clang/lib/Serialization/ASTReaderDecl.cpp
M clang/lib/StaticAnalyzer/Checkers/CheckSecuritySyntaxOnly.cpp
M clang/lib/StaticAnalyzer/Checkers/StdLibraryFunctionsChecker.cpp
M clang/lib/Tooling/Syntax/Tokens.cpp
M clang/test/AST/Interp/complex.cpp
M clang/test/AST/ast-dump-invalid-initialized.cpp
M clang/test/Analysis/Inputs/system-header-simulator-for-simple-stream.h
M clang/test/Analysis/Inputs/system-header-simulator.h
M clang/test/Analysis/bsd-string.c
M clang/test/Analysis/std-c-library-functions-POSIX.c
M clang/test/Analysis/stream-errno.c
M clang/test/Analysis/string.c
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A libcxx/test/libcxx/selftest/modules/std-and-std.compat-module.sh.cpp
A libcxx/test/libcxx/selftest/modules/std-module.sh.cpp
A libcxx/test/libcxx/selftest/modules/std.compat-module.sh.cpp
M libcxx/test/libcxx/transitive_includes/cxx03.csv
M libcxx/test/libcxx/transitive_includes/cxx11.csv
M libcxx/test/libcxx/transitive_includes/cxx14.csv
M libcxx/test/libcxx/transitive_includes/cxx17.csv
M libcxx/test/libcxx/transitive_includes/cxx20.csv
M libcxx/test/libcxx/transitive_includes/cxx23.csv
M libcxx/test/libcxx/transitive_includes/cxx26.csv
R libcxx/test/lit.local.cfg
M libcxx/test/std/algorithms/alg.modifying.operations/alg.fill/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.move/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.replace/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.rotate/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.modifying.operations/alg.transform/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.all_of/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.any_of/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.equal/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.find/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.foreach/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.nonmodifying/alg.none_of/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.merge/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/alg.sorting/alg.sort/stable.sort/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/numeric.ops/reduce/pstl.exception_handling.pass.cpp
M libcxx/test/std/algorithms/numeric.ops/transform.reduce/pstl.exception_handling.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/locale-specific_form.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/print.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/println.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_nonunicode.pass.cpp
M libcxx/test/std/input.output/iostream.format/output.streams/ostream.formatted/ostream.formatted.print/vprint_unicode.pass.cpp
A libcxx/test/std/input.output/iostream.format/print.fun/includes.compile.pass.cpp
M libcxx/test/std/modules/std.compat.pass.cpp
M libcxx/test/std/modules/std.pass.cpp
M libcxx/test/std/re/re.const/re.matchflag/match_not_eol.pass.cpp
M libcxx/test/support/asan_testing.h
M libcxx/test/support/check_assertion.h
M libcxx/test/tools/clang_tidy_checks/CMakeLists.txt
M libcxx/test/tools/clang_tidy_checks/header_exportable_declarations.cpp
M libcxx/utils/ci/Dockerfile
M libcxx/utils/ci/buildkite-pipeline.yml
M libcxx/utils/ci/run-buildbot
M libcxx/utils/generate_iwyu_mapping.py
M libcxx/utils/libcxx/header_information.py
M libcxx/utils/libcxx/test/config.py
M libcxx/utils/libcxx/test/features.py
M libcxx/utils/libcxx/test/format.py
M libcxx/utils/libcxx/test/modules.py
A libcxx/vendor/llvm/default_assertion_handler.in
M libcxxabi/CMakeLists.txt
M libunwind/src/UnwindCursor.hpp
M libunwind/src/libunwind.cpp
M lld/COFF/Driver.cpp
M lld/ELF/Arch/RISCV.cpp
M lld/ELF/Driver.cpp
M lld/ELF/Relocations.cpp
M lld/test/COFF/print-search-paths.s
M lld/test/ELF/lto/devirt_validate_vtable_typeinfos.ll
A lld/test/ELF/x86-64-pc32-overflow-large.s
M lld/wasm/InputFiles.cpp
M lld/wasm/SymbolTable.cpp
M lldb/include/lldb/Core/DebuggerEvents.h
M lldb/include/lldb/Core/Progress.h
M lldb/include/lldb/Core/ValueObject.h
M lldb/include/lldb/Host/Config.h.cmake
M lldb/include/lldb/Symbol/CompileUnit.h
M lldb/include/lldb/Symbol/LineEntry.h
M lldb/include/lldb/Utility/FileSpecList.h
A lldb/include/lldb/Utility/SupportFile.h
M lldb/include/lldb/Utility/XcodeSDK.h
M lldb/include/lldb/lldb-forward.h
M lldb/source/API/SBTypeFilter.cpp
M lldb/source/API/SBTypeFormat.cpp
M lldb/source/API/SBTypeSummary.cpp
M lldb/source/API/SBTypeSynthetic.cpp
M lldb/source/Breakpoint/BreakpointResolver.cpp
M lldb/source/Commands/CommandObjectFrame.cpp
M lldb/source/Commands/CommandObjectSource.cpp
M lldb/source/Core/Disassembler.cpp
M lldb/source/Core/Module.cpp
M lldb/source/Core/ModuleList.cpp
M lldb/source/Core/Progress.cpp
M lldb/source/Core/ValueObject.cpp
M lldb/source/Host/macosx/objcxx/HostInfoMacOSX.mm
M lldb/source/Plugins/DynamicLoader/Darwin-Kernel/DynamicLoaderDarwinKernel.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderDarwin.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOS.cpp
M lldb/source/Plugins/DynamicLoader/MacOSX-DYLD/DynamicLoaderMacOSXDYLD.cpp
M lldb/source/Plugins/Instruction/ARM/EmulateInstructionARM.cpp
M lldb/source/Plugins/LanguageRuntime/ObjC/AppleObjCRuntime/AppleObjCRuntimeV2.cpp
M lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp
M lldb/source/Plugins/ObjectFile/Mach-O/ObjectFileMachO.cpp
M lldb/source/Plugins/Platform/MacOSX/CMakeLists.txt
M lldb/source/Plugins/Platform/MacOSX/PlatformAppleSimulator.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformDarwin.cpp
M lldb/source/Plugins/Platform/MacOSX/PlatformMacOSX.cpp
A lldb/source/Plugins/Platform/MacOSX/PlatformRemoteAppleXR.cpp
A lldb/source/Plugins/Platform/MacOSX/PlatformRemoteAppleXR.h
M lldb/source/Plugins/Platform/MacOSX/objcxx/PlatformiOSSimulatorCoreSimulatorSupport.h
M lldb/source/Plugins/Process/MacOSX-Kernel/ProcessKDP.cpp
M lldb/source/Plugins/Process/Utility/RegisterContextPOSIX_mips64.cpp
M lldb/source/Plugins/Process/Windows/Common/x64/RegisterContextWindows_x64.cpp
M lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp
M lldb/source/Plugins/SymbolFile/Breakpad/SymbolFileBreakpad.cpp
M lldb/source/Plugins/SymbolFile/DWARF/ManualDWARFIndex.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARF.cpp
M lldb/source/Plugins/SymbolFile/DWARF/SymbolFileDWARFDebugMap.cpp
M lldb/source/Plugins/SymbolFile/NativePDB/SymbolFileNativePDB.cpp
M lldb/source/Plugins/SymbolLocator/Default/SymbolLocatorDefault.cpp
M lldb/source/Plugins/SystemRuntime/MacOSX/SystemRuntimeMacOSX.cpp
M lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp
M lldb/source/Symbol/CompileUnit.cpp
M lldb/source/Symbol/LineEntry.cpp
M lldb/source/Symbol/LineTable.cpp
M lldb/source/Symbol/SymbolContext.cpp
M lldb/source/Target/Process.cpp
M lldb/source/Target/ThreadPlanStepOverRange.cpp
M lldb/source/Target/ThreadPlanStepRange.cpp
M lldb/source/Utility/FileSpecList.cpp
M lldb/source/Utility/XcodeSDK.cpp
A lldb/test/API/functionalities/executable_first/Makefile
A lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
A lldb/test/API/functionalities/executable_first/b.cpp
A lldb/test/API/functionalities/executable_first/main.cpp
M lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py
M lldb/test/API/functionalities/progress_reporting/TestTrimmedProgressReporting.py
M lldb/test/API/macosx/rosetta/Makefile
M lldb/test/API/tools/lldb-dap/completions/TestDAP_completions.py
M lldb/test/API/tools/lldb-dap/evaluate/TestDAP_evaluate.py
M lldb/tools/debugserver/source/MacOSX/MachProcess.mm
M lldb/tools/debugserver/source/RNBRemote.cpp
M lldb/tools/driver/Driver.cpp
M lldb/tools/lldb-dap/DAP.cpp
M lldb/tools/lldb-dap/DAP.h
M lldb/tools/lldb-dap/lldb-dap.cpp
M lldb/tools/lldb-server/lldb-server.cpp
M lldb/unittests/Utility/XcodeSDKTest.cpp
M llvm/CMakeLists.txt
M llvm/cmake/modules/CrossCompile.cmake
M llvm/docs/AMDGPUUsage.rst
M llvm/docs/LangRef.rst
M llvm/docs/RISCVUsage.rst
M llvm/docs/ReleaseNotes.rst
A llvm/docs/requirements-hashed.txt
M llvm/include/llvm/Analysis/AliasAnalysis.h
M llvm/include/llvm/Analysis/AliasSetTracker.h
M llvm/include/llvm/Analysis/VecFuncs.def
M llvm/include/llvm/Analysis/VectorUtils.h
M llvm/include/llvm/BinaryFormat/ELF.h
M llvm/include/llvm/BinaryFormat/MachO.def
M llvm/include/llvm/BinaryFormat/Magic.h
M llvm/include/llvm/BinaryFormat/Wasm.h
M llvm/include/llvm/BinaryFormat/WasmTraits.h
M llvm/include/llvm/CodeGen/CodeGenPassBuilder.h
A llvm/include/llvm/CodeGen/GlobalMerge.h
M llvm/include/llvm/CodeGen/MachineBasicBlock.h
M llvm/include/llvm/CodeGen/MachinePassRegistry.def
M llvm/include/llvm/CodeGen/MachineScheduler.h
M llvm/include/llvm/DWARFLinker/Classic/DWARFLinker.h
A llvm/include/llvm/DWARFLinker/IndexedValuesMap.h
M llvm/include/llvm/ExecutionEngine/JITLink/aarch32.h
A llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h
M llvm/include/llvm/Frontend/Offloading/Utility.h
M llvm/include/llvm/IR/Attributes.h
M llvm/include/llvm/IR/DIBuilder.h
M llvm/include/llvm/IR/DebugInfo.h
M llvm/include/llvm/IR/DebugInfoMetadata.h
M llvm/include/llvm/IR/DebugProgramInstruction.h
M llvm/include/llvm/IR/IntrinsicsAMDGPU.td
M llvm/include/llvm/IR/IntrinsicsNVVM.td
M llvm/include/llvm/IR/Metadata.h
A llvm/include/llvm/IR/VFABIDemangler.h
M llvm/include/llvm/MC/MCSymbol.h
M llvm/include/llvm/MC/MCSymbolWasm.h
M llvm/include/llvm/Object/COFFImportFile.h
M llvm/include/llvm/Support/GenericLoopInfo.h
M llvm/include/llvm/Support/MathExtras.h
M llvm/include/llvm/Support/RISCVAttributes.h
M llvm/include/llvm/TargetParser/AArch64TargetParser.h
M llvm/include/llvm/TargetParser/Triple.h
M llvm/include/llvm/TargetParser/X86TargetParser.def
M llvm/include/llvm/Transforms/Utils/ModuleUtils.h
M llvm/include/llvm/Transforms/Utils/NameAnonGlobals.h
M llvm/lib/Analysis/AliasAnalysis.cpp
M llvm/lib/Analysis/AliasSetTracker.cpp
M llvm/lib/Analysis/BasicAliasAnalysis.cpp
M llvm/lib/Analysis/CMakeLists.txt
M llvm/lib/Analysis/LoopAccessAnalysis.cpp
M llvm/lib/Analysis/TargetLibraryInfo.cpp
R llvm/lib/Analysis/VFABIDemangling.cpp
M llvm/lib/Analysis/VectorUtils.cpp
M llvm/lib/AsmParser/LLParser.cpp
M llvm/lib/BinaryFormat/Magic.cpp
M llvm/lib/Bitcode/Reader/MetadataLoader.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp
M llvm/lib/CodeGen/AsmPrinter/DwarfCompileUnit.h
M llvm/lib/CodeGen/AsmPrinter/DwarfDebug.cpp
M llvm/lib/CodeGen/BasicBlockSections.cpp
M llvm/lib/CodeGen/BasicBlockSectionsProfileReader.cpp
M llvm/lib/CodeGen/CodeGenPrepare.cpp
M llvm/lib/CodeGen/GlobalISel/CallLowering.cpp
M llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
M llvm/lib/CodeGen/GlobalISel/InstructionSelect.cpp
M llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
M llvm/lib/CodeGen/GlobalMerge.cpp
M llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h
M llvm/lib/CodeGen/MachineScheduler.cpp
M llvm/lib/CodeGen/ReplaceWithVeclib.cpp
M llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
M llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
M llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
M llvm/lib/CodeGen/SlotIndexes.cpp
M llvm/lib/DWARFLinker/Classic/DWARFLinker.cpp
M llvm/lib/DWARFLinker/Parallel/DWARFLinkerUnit.h
R llvm/lib/DWARFLinker/Parallel/IndexedValuesMap.h
M llvm/lib/DebugInfo/DWARF/DWARFTypePrinter.cpp
M llvm/lib/DebugInfo/Symbolize/SymbolizableObjectFile.cpp
M llvm/lib/ExecutionEngine/ExecutionEngine.cpp
M llvm/lib/ExecutionEngine/JITLink/ELF_aarch32.cpp
M llvm/lib/ExecutionEngine/JITLink/aarch32.cpp
M llvm/lib/Frontend/Offloading/CMakeLists.txt
A llvm/lib/Frontend/Offloading/OffloadWrapper.cpp
M llvm/lib/Frontend/Offloading/Utility.cpp
M llvm/lib/IR/AsmWriter.cpp
M llvm/lib/IR/AutoUpgrade.cpp
M llvm/lib/IR/CMakeLists.txt
M llvm/lib/IR/ConstantFold.cpp
M llvm/lib/IR/DIBuilder.cpp
M llvm/lib/IR/DebugInfo.cpp
M llvm/lib/IR/DebugProgramInstruction.cpp
M llvm/lib/IR/Instructions.cpp
M llvm/lib/IR/Metadata.cpp
A llvm/lib/IR/VFABIDemangler.cpp
M llvm/lib/IR/Verifier.cpp
M llvm/lib/MC/MCFragment.cpp
M llvm/lib/MC/MCObjectFileInfo.cpp
M llvm/lib/MC/MCParser/DarwinAsmParser.cpp
M llvm/lib/MC/MCStreamer.cpp
M llvm/lib/MC/WasmObjectWriter.cpp
M llvm/lib/Object/Binary.cpp
M llvm/lib/Object/COFFImportFile.cpp
M llvm/lib/Object/ObjectFile.cpp
M llvm/lib/Object/RelocationResolver.cpp
M llvm/lib/Object/WasmObjectFile.cpp
M llvm/lib/Passes/PassBuilder.cpp
M llvm/lib/Passes/PassRegistry.def
M llvm/lib/ProfileData/InstrProf.cpp
M llvm/lib/Support/BalancedPartitioning.cpp
M llvm/lib/Support/Caching.cpp
M llvm/lib/Support/FileCollector.cpp
M llvm/lib/Support/GraphWriter.cpp
M llvm/lib/Support/LockFileManager.cpp
M llvm/lib/Support/Path.cpp
M llvm/lib/Support/Process.cpp
M llvm/lib/Support/RISCVISAInfo.cpp
M llvm/lib/Support/Unicode.cpp
M llvm/lib/Support/UnicodeCaseFold.cpp
M llvm/lib/Support/UnicodeNameToCodepoint.cpp
M llvm/lib/Support/UnicodeNameToCodepointGenerated.cpp
M llvm/lib/Support/Unix/Program.inc
M llvm/lib/Support/VirtualFileSystem.cpp
M llvm/lib/Target/AArch64/AArch64Combine.td
M llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
M llvm/lib/Target/AArch64/AArch64ISelLowering.h
M llvm/lib/Target/AArch64/AArch64InstrGISel.td
M llvm/lib/Target/AArch64/AArch64InstrInfo.td
M llvm/lib/Target/AArch64/AArch64LoopIdiomTransform.cpp
M llvm/lib/Target/AArch64/AArch64MachineFunctionInfo.h
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.cpp
M llvm/lib/Target/AArch64/AArch64TargetObjectFile.h
M llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
M llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
M llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
M llvm/lib/Target/AArch64/GISel/AArch64PreLegalizerCombiner.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.cpp
M llvm/lib/Target/AArch64/Utils/AArch64SMEAttributes.h
M llvm/lib/Target/AMDGPU/AMDGPU.h
M llvm/lib/Target/AMDGPU/AMDGPU.td
M llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
M llvm/lib/Target/AMDGPU/AMDGPUCallLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUGISel.td
M llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
M llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h
M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
M llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
M llvm/lib/Target/AMDGPU/AMDGPULateCodeGenPrepare.cpp
M llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPULowerKernelArguments.cpp
A llvm/lib/Target/AMDGPU/AMDGPUMarkLastScratchLoad.cpp
M llvm/lib/Target/AMDGPU/AMDGPUPostLegalizerCombiner.cpp
M llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
M llvm/lib/Target/AMDGPU/AMDGPUSearchableTables.td
M llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
M llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
M llvm/lib/Target/AMDGPU/BUFInstructions.td
M llvm/lib/Target/AMDGPU/CMakeLists.txt
M llvm/lib/Target/AMDGPU/DSInstructions.td
M llvm/lib/Target/AMDGPU/FLATInstructions.td
M llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp
M llvm/lib/Target/AMDGPU/GCNNSAReassign.cpp
M llvm/lib/Target/AMDGPU/GCNSubtarget.h
M llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
M llvm/lib/Target/AMDGPU/MIMGInstructions.td
M llvm/lib/Target/AMDGPU/SIDefines.h
M llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
M llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.cpp
M llvm/lib/Target/AMDGPU/SIISelLowering.h
M llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
M llvm/lib/Target/AMDGPU/SIInstrInfo.h
M llvm/lib/Target/AMDGPU/SIInstrInfo.td
M llvm/lib/Target/AMDGPU/SIInstructions.td
M llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
M llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
M llvm/lib/Target/AMDGPU/SMInstructions.td
M llvm/lib/Target/AMDGPU/SOPInstructions.td
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
M llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
M llvm/lib/Target/AMDGPU/VOP1Instructions.td
M llvm/lib/Target/AMDGPU/VOP2Instructions.td
M llvm/lib/Target/AMDGPU/VOP3Instructions.td
M llvm/lib/Target/AMDGPU/VOP3PInstructions.td
M llvm/lib/Target/AMDGPU/VOPCInstructions.td
M llvm/lib/Target/AMDGPU/VOPInstructions.td
M llvm/lib/Target/ARM/ARMInstrMVE.td
M llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp
M llvm/lib/Target/ARM/MCTargetDesc/ARMFixupKinds.h
M llvm/lib/Target/ARM/MVEGatherScatterLowering.cpp
M llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
M llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.cpp
M llvm/lib/Target/LoongArch/MCTargetDesc/LoongArchAsmBackend.h
M llvm/lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.cpp
M llvm/lib/Target/NVPTX/NVPTXISelLowering.h
M llvm/lib/Target/NVPTX/NVPTXIntrinsics.td
M llvm/lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp
M llvm/lib/Target/RISCV/GISel/RISCVCallLowering.cpp
M llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp
M llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
M llvm/lib/Target/RISCV/RISCV.td
M llvm/lib/Target/RISCV/RISCVCallingConv.td
M llvm/lib/Target/RISCV/RISCVCodeGenPrepare.cpp
M llvm/lib/Target/RISCV/RISCVFeatures.td
M llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
M llvm/lib/Target/RISCV/RISCVFrameLowering.h
M llvm/lib/Target/RISCV/RISCVISelLowering.cpp
M llvm/lib/Target/RISCV/RISCVISelLowering.h
M llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
M llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
M llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
M llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp
M llvm/lib/Target/RISCV/RISCVProcessors.td
M llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
A llvm/lib/Target/RISCV/RISCVSchedSiFiveP400.td
M llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
M llvm/lib/Target/RISCV/RISCVTargetObjectFile.cpp
M llvm/lib/Target/RISCV/RISCVTargetObjectFile.h
M llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
M llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp
M llvm/lib/Target/Sparc/Sparc.td
M llvm/lib/Target/Sparc/SparcAsmPrinter.cpp
M llvm/lib/Target/SystemZ/SystemZElimCompare.cpp
M llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
M llvm/lib/Target/SystemZ/SystemZInstrFP.td
M llvm/lib/Target/SystemZ/SystemZInstrFormats.td
M llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
M llvm/lib/Target/SystemZ/SystemZPatterns.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ13.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ14.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ15.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ16.td
M llvm/lib/Target/SystemZ/SystemZScheduleZ196.td
M llvm/lib/Target/SystemZ/SystemZScheduleZEC12.td
M llvm/lib/Target/TargetMachine.cpp
M llvm/lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp
M llvm/lib/Target/WebAssembly/WebAssemblyUtilities.cpp
M llvm/lib/Target/X86/X86AsmPrinter.cpp
M llvm/lib/Target/X86/X86FixupVectorConstants.cpp
M llvm/lib/Target/X86/X86ISelDAGToDAG.cpp
M llvm/lib/Target/X86/X86ISelLowering.cpp
M llvm/lib/Target/X86/X86InstrArithmetic.td
M llvm/lib/Target/X86/X86InstrCompiler.td
M llvm/lib/Target/X86/X86InstrInfo.cpp
M llvm/lib/Target/X86/X86InstrInfo.h
M llvm/lib/Target/X86/X86InstrMisc.td
M llvm/lib/Target/X86/X86InstrSSE.td
M llvm/lib/Target/X86/X86InstrShiftRotate.td
M llvm/lib/Target/X86/X86InstrUtils.td
M llvm/lib/Target/X86/X86LoadValueInjectionLoadHardening.cpp
M llvm/lib/Target/X86/X86MCInstLower.cpp
M llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp
M llvm/lib/TargetParser/AArch64TargetParser.cpp
M llvm/lib/TargetParser/ARMTargetParser.cpp
M llvm/lib/TargetParser/Host.cpp
M llvm/lib/TargetParser/TargetParser.cpp
M llvm/lib/TargetParser/Triple.cpp
M llvm/lib/TargetParser/X86TargetParser.cpp
M llvm/lib/TextAPI/Platform.cpp
M llvm/lib/Transforms/Coroutines/CoroEarly.cpp
M llvm/lib/Transforms/Coroutines/CoroFrame.cpp
M llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
M llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
M llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp
M llvm/lib/Transforms/InstCombine/InstCombineInternal.h
M llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp
M llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
M llvm/lib/Transforms/Instrumentation/AddressSanitizer.cpp
M llvm/lib/Transforms/ObjCARC/DependencyAnalysis.cpp
M llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp
M llvm/lib/Transforms/Scalar/LICM.cpp
M llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp
M llvm/lib/Transforms/Scalar/SROA.cpp
M llvm/lib/Transforms/Utils/BasicBlockUtils.cpp
M llvm/lib/Transforms/Utils/CloneFunction.cpp
M llvm/lib/Transforms/Utils/CodeExtractor.cpp
M llvm/lib/Transforms/Utils/InjectTLIMappings.cpp
M llvm/lib/Transforms/Utils/Local.cpp
M llvm/lib/Transforms/Utils/MemoryOpRemark.cpp
M llvm/lib/Transforms/Utils/ModuleUtils.cpp
M llvm/lib/Transforms/Utils/MoveAutoInit.cpp
M llvm/lib/Transforms/Utils/SimplifyCFG.cpp
M llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp
M llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h
M llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
M llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
M llvm/lib/Transforms/Vectorize/VPlanHCFGBuilder.cpp
M llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp
M llvm/runtimes/CMakeLists.txt
M llvm/test/Analysis/AliasSet/argmemonly.ll
M llvm/test/Analysis/AliasSet/guards.ll
M llvm/test/Analysis/AliasSet/intrinsics.ll
M llvm/test/Analysis/AliasSet/memloc-vscale.ll
M llvm/test/Analysis/AliasSet/memset.ll
M llvm/test/Analysis/AliasSet/memtransfer.ll
M llvm/test/Analysis/AliasSet/saturation.ll
M llvm/test/Analysis/BasicAA/gep-alias.ll
M llvm/test/Analysis/BasicAA/inttoptr_constexpr.ll
M llvm/test/Analysis/BasicAA/separate_storage-alias-sets.ll
A llvm/test/Analysis/CostModel/AArch64/arith-fp-frem.ll
M llvm/test/Analysis/CostModel/AArch64/vec3-ops.ll
M llvm/test/Analysis/CostModel/RISCV/rvv-load-store.ll
M llvm/test/Analysis/CostModel/RISCV/shuffle-permute.ll
M llvm/test/Analysis/UniformityAnalysis/AMDGPU/atomics.ll
M llvm/test/Assembler/auto_upgrade_nvvm_intrinsics.ll
A llvm/test/Assembler/implicit-intrinsic-declaration-invalid.ll
A llvm/test/Assembler/implicit-intrinsic-declaration.ll
R llvm/test/Bitcode/clone-local-types.ll
M llvm/test/Bitcode/upgrade-cu-locals.ll
M llvm/test/Bitcode/upgrade-cu-locals.ll.bc
M llvm/test/CodeGen/AArch64/GlobalISel/combine-ext.mir
M llvm/test/CodeGen/AArch64/GlobalISel/combine-select.mir
A llvm/test/CodeGen/AArch64/GlobalISel/counter-fallback.ll
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
M llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
M llvm/test/CodeGen/AArch64/arm64-codegen-prepare-extload.ll
M llvm/test/CodeGen/AArch64/arm64-vabs.ll
M llvm/test/CodeGen/AArch64/avoid-free-ext-promotion.ll
M llvm/test/CodeGen/AArch64/bfis-in-loop.ll
M llvm/test/CodeGen/AArch64/icmp.ll
A llvm/test/CodeGen/AArch64/sme-streaming-body-streaming-compatible-interface.ll
A llvm/test/CodeGen/AArch64/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AArch64/sve2p1-intrinsics-dots.ll
M llvm/test/CodeGen/AArch64/vecreduce-add.ll
M llvm/test/CodeGen/AMDGPU/32-bit-local-address-space.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/addsubu64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-irtranslator.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/amdgpu-prelegalizer-combiner-crash.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/bool-legalization.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-fmed3-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fabs-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-post-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul-pre-legalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-ext-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-foldable-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fsub-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-or-redundant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-redundant-neg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rot.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-illegal-types.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-imm-chain.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic-shlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-shift-of-shifted-logic.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/combine-trunc-shift.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/dereferenceable-declaration.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement-stack-lower.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-atomic-fadd.v2f16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/flat-scratch.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3-min-max-const-combine.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp-atomics-gfx940.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fp64-atomics-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/fpow.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/frem.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f32-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.f64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-no-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/global-atomic-fadd.v2f16-rtn.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inline-asm-mismatched-size.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.class.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cos.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pk.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.i16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pknorm.u16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fcmp.constants.w64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmad.ftz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fmed3.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.fract.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mbcnt.lo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mul.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.i24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.mulhi.u24.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rcp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.reloc.constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.clamp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.rsq.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.barrier.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sffbh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgcn.sin.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-atomic-cmpxchg-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ashr.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomic-cmpxchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-add-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-fadd-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-atomicrmw-xchg-region.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-bitreverse.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-brcond.mir
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M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.invalid.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-stacksave-stackrestore.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-atomic-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-flat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-global.s96.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-local.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-store-private.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-trunc.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.gfx10.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-zext.mir
A llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslate-bf16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgcn-sendmsg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-assert-align.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-atomicrmw.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-constrained-fp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-fast-math-flags.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.v2i65.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-invariant.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-memory-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-metadata.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-sat.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-zext-vec-index.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-misaligned-bug.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/lds-zero-initializer.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-addrspacecast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp-s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-jump-table.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-rotl-rotr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.abs.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ballot.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.scale.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.fmul.legacy.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.global.atomic.csub.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.cd.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.sample.g16.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.intersect_ray.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.make.buffer.rsrc.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mfma.gfx90a.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.mov.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.rsq.clamp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.setreg.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.sleep.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sdot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.set.inactive.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.softwqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.sudot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot2.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot4.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.udot8.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.update.dpp.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_32.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wmma_64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.workitem.id.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.demote.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wqm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.wwm.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.memcpy.inline.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/load-constant.96.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/localizer-wrong-insert-point.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/merge-buffer-stores.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul-known-bits.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/mul.ll
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-reassoc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-abs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.s32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-add.v2s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp-compr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-exp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn-s-buffer-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ballot.i64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.class.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.cvt.pkrtz.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.fmas.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.div.scale.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.append.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.bpermute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.consume.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.init.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.gws.sema.v.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.ordered.swap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.permute.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ds.swizzle.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.else.64.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.fmul.legacy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.groupstaticsize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.mov.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.f16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.interp.p2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kernarg.segment.ptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.kill.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.direct.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.lds.param.load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.live.mask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx90a.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.gfx940.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.mfma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ps.live.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readfirstlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.readlane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getpc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.getreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memrealtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.memtime.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.sendmsghalt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.update.dpp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.demote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wqm.vote.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.writelane.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.wwm.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbh-u32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-ffbl-b32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgpu-wave-address.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-anyext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ashr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-align.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-assert-zext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomic-cmpxchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-and.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-max.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-min.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xchg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-atomicrmw-xor.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitreverse.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-brcond.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bswap.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-build-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-concat-vector.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-constant.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctlz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ctpop.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-dyn-stackalloc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-extract.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fabs.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fadd.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcanonicalize.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fceil.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fcmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fexp2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-flog2.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fma.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fmul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fneg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fpext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptosi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptoui.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fptrunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-frame-index.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsqrt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-fsub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-icmp.s16.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-illegal-copy.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-implicit-def.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert-vector-elt.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-insert.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-intrinsic-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-inttoptr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-load.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-lshr.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mad_64_32.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-merge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-mul.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-or.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi-s1.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-phi.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-pseudo-scalar-transcendental.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptr-add.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrmask.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ptrtoint.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-reg-sequence.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-salu-float.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sbfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-select.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext-inreg.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sext.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sextload.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-shl.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-smulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ssube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-sub.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-trunc.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uadde.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uaddo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-ubfx.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-uitofp.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umax.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umin.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-umulh.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-unmerge-values.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usube.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-usubo.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-widen-scalar-loads.mir
M llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-xor.mir
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M llvm/test/CodeGen/AMDGPU/andorn2.ll
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M llvm/test/CodeGen/AMDGPU/computeKnownBits-scalar-to-vector-crash.ll
M llvm/test/CodeGen/AMDGPU/concat_vectors.ll
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M llvm/test/CodeGen/AMDGPU/dagcombine-fma-fmad.ll
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M llvm/test/CodeGen/AMDGPU/dagcombine-setcc-select.ll
M llvm/test/CodeGen/AMDGPU/dagcombine-v1i8-extractvecelt-crash.ll
M llvm/test/CodeGen/AMDGPU/dagcombiner-bug-illegal-vec4-int-to-fp.ll
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M llvm/test/CodeGen/AMDGPU/disconnected-predset-break-bug.ll
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M llvm/test/CodeGen/AMDGPU/divergence-at-use.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-abs.ll
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M llvm/test/CodeGen/AMDGPU/divergence-driven-negsubinlineconst.ll
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M llvm/test/CodeGen/AMDGPU/divergence-driven-sext-inreg.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-trunc-to-i1.ll
M llvm/test/CodeGen/AMDGPU/divergence-driven-xnor.ll
M llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
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M llvm/test/CodeGen/AMDGPU/dpp_combine.mir
M llvm/test/CodeGen/AMDGPU/dpp_combine_gfx11.mir
M llvm/test/CodeGen/AMDGPU/drop-mem-operand-move-smrd.ll
M llvm/test/CodeGen/AMDGPU/ds-alignment.ll
M llvm/test/CodeGen/AMDGPU/ds-combine-with-dependence.ll
M llvm/test/CodeGen/AMDGPU/ds-negative-offset-addressing-mode-loop.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_offset_order.ll
M llvm/test/CodeGen/AMDGPU/ds_read2_superreg.ll
M llvm/test/CodeGen/AMDGPU/ds_read2st64.ll
M llvm/test/CodeGen/AMDGPU/dual-source-blend-export.ll
M llvm/test/CodeGen/AMDGPU/dynamic_stackalloc.ll
M llvm/test/CodeGen/AMDGPU/early-if-convert-cost.ll
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M llvm/test/CodeGen/AMDGPU/empty-function.ll
M llvm/test/CodeGen/AMDGPU/enable-no-signed-zeros-fp-math.ll
M llvm/test/CodeGen/AMDGPU/endcf-loop-header.ll
M llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
M llvm/test/CodeGen/AMDGPU/exceed-max-sgprs.ll
M llvm/test/CodeGen/AMDGPU/expand-atomicrmw-syncscope.ll
M llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir
M llvm/test/CodeGen/AMDGPU/extend-bit-ops-i16.ll
M llvm/test/CodeGen/AMDGPU/extload-private.ll
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M llvm/test/CodeGen/AMDGPU/extract-vector-elt-build-vector-combine.ll
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M llvm/test/CodeGen/AMDGPU/fetch-limits.r700+.ll
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M llvm/test/CodeGen/AMDGPU/local-memory.amdgcn.ll
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M llvm/test/CodeGen/AMDGPU/local-memory.r600.ll
M llvm/test/CodeGen/AMDGPU/local-stack-slot-offset.ll
M llvm/test/CodeGen/AMDGPU/long-branch-reserve-register.ll
M llvm/test/CodeGen/AMDGPU/loop-address.ll
M llvm/test/CodeGen/AMDGPU/loop-idiom.ll
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M llvm/test/CodeGen/AMDGPU/loop_break.ll
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M llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-atomic-insert-end.mir
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-local.mir
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M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir
M llvm/test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir
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M llvm/test/CodeGen/AMDGPU/memory_clause.ll
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M llvm/test/CodeGen/AMDGPU/merge-image-load-gfx11.mir
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M llvm/test/CodeGen/AMDGPU/merge-load-store-physreg.mir
M llvm/test/CodeGen/AMDGPU/merge-load-store-vreg.mir
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M llvm/test/CodeGen/AMDGPU/merge-m0.mir
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M llvm/test/CodeGen/AMDGPU/mfma-cd-select.ll
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M llvm/test/CodeGen/AMDGPU/mfma-no-register-aliasing.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select-gfx940.ll
M llvm/test/CodeGen/AMDGPU/mfma-vgpr-cd-select.ll
M llvm/test/CodeGen/AMDGPU/min-waves-per-eu-not-respected.ll
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M llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans.ll
M llvm/test/CodeGen/AMDGPU/move-to-valu-vimage-vsample.ll
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M llvm/test/CodeGen/AMDGPU/mubuf-legalize-operands-non-ptr-intrinsics.ll
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M llvm/test/CodeGen/AMDGPU/mubuf-offset-private.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr-non-ptr-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll
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M llvm/test/CodeGen/AMDGPU/mul.i16.ll
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M llvm/test/CodeGen/AMDGPU/mul_int24.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-amdgcn.ll
M llvm/test/CodeGen/AMDGPU/mul_uint24-r600.ll
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M llvm/test/CodeGen/AMDGPU/nested-calls.ll
M llvm/test/CodeGen/AMDGPU/nested-loop-conditions.ll
M llvm/test/CodeGen/AMDGPU/no-dup-inst-prefetch.ll
M llvm/test/CodeGen/AMDGPU/no-shrink-extloads.ll
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M llvm/test/CodeGen/AMDGPU/nsa-vmem-hazard.mir
M llvm/test/CodeGen/AMDGPU/nullptr-long-address-spaces.ll
M llvm/test/CodeGen/AMDGPU/nullptr.ll
M llvm/test/CodeGen/AMDGPU/occupancy-levels.ll
M llvm/test/CodeGen/AMDGPU/offset-split-flat.ll
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M llvm/test/CodeGen/AMDGPU/parallelandifcollapse.ll
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M llvm/test/CodeGen/AMDGPU/rsq.f64.ll
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M llvm/test/CodeGen/AMDGPU/s_movk_i32.ll
M llvm/test/CodeGen/AMDGPU/s_or_saveexec_xor_combine.mir
M llvm/test/CodeGen/AMDGPU/saddo.ll
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M llvm/test/CodeGen/AMDGPU/scalar-branch-missing-and-exec.ll
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M llvm/test/CodeGen/AMDGPU/scalar_to_vector_v2x16.ll
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M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit2.ll
M llvm/test/CodeGen/AMDGPU/schedule-regpressure-limit3.ll
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M llvm/test/CodeGen/AMDGPU/schedule-relaxed-occupancy.ll
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M llvm/test/CodeGen/AMDGPU/sdag-print-divergence.ll
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M llvm/test/CodeGen/AMDGPU/si-opt-vgpr-liverange-bug-deadlanes.mir
M llvm/test/CodeGen/AMDGPU/si-scheduler-exports.ll
M llvm/test/CodeGen/AMDGPU/si-scheduler.ll
M llvm/test/CodeGen/AMDGPU/si-sgpr-spill.ll
M llvm/test/CodeGen/AMDGPU/si-spill-cf.ll
M llvm/test/CodeGen/AMDGPU/si-spill-sgpr-stack.ll
M llvm/test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll
M llvm/test/CodeGen/AMDGPU/si-vector-hang.ll
M llvm/test/CodeGen/AMDGPU/simplifydemandedbits-recursion.ll
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow-postra.mir
M llvm/test/CodeGen/AMDGPU/sink-after-control-flow.mir
M llvm/test/CodeGen/AMDGPU/sint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/sint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/sitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/skip-if-dead.ll
M llvm/test/CodeGen/AMDGPU/smed3.ll
M llvm/test/CodeGen/AMDGPU/smem-no-clause-coalesced.mir
M llvm/test/CodeGen/AMDGPU/smem-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/sminmax.ll
M llvm/test/CodeGen/AMDGPU/sminmax.v2i16.ll
M llvm/test/CodeGen/AMDGPU/smrd-fold-offset.mir
M llvm/test/CodeGen/AMDGPU/smrd-gfx10.ll
M llvm/test/CodeGen/AMDGPU/smrd-vccz-bug.ll
M llvm/test/CodeGen/AMDGPU/smrd.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-agpr.mir
M llvm/test/CodeGen/AMDGPU/spill-alloc-sgpr-init-bug.ll
M llvm/test/CodeGen/AMDGPU/spill-cfg-position.ll
M llvm/test/CodeGen/AMDGPU/spill-m0.ll
M llvm/test/CodeGen/AMDGPU/spill-reg-tuple-super-reg-use.mir
M llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
M llvm/test/CodeGen/AMDGPU/spill-sgpr-stack-no-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr-to-agpr.ll
M llvm/test/CodeGen/AMDGPU/spill-vgpr.ll
M llvm/test/CodeGen/AMDGPU/spill-wide-sgpr.ll
M llvm/test/CodeGen/AMDGPU/spill192.mir
M llvm/test/CodeGen/AMDGPU/spill224.mir
M llvm/test/CodeGen/AMDGPU/spill288.mir
M llvm/test/CodeGen/AMDGPU/spill320.mir
M llvm/test/CodeGen/AMDGPU/spill352.mir
M llvm/test/CodeGen/AMDGPU/spill384.mir
M llvm/test/CodeGen/AMDGPU/split-mbb-lis-subrange.mir
M llvm/test/CodeGen/AMDGPU/split-scalar-i64-add.ll
M llvm/test/CodeGen/AMDGPU/split-smrd.ll
M llvm/test/CodeGen/AMDGPU/split-vector-memoperand-offsets.ll
M llvm/test/CodeGen/AMDGPU/splitkit-copy-bundle.mir
M llvm/test/CodeGen/AMDGPU/splitkit-copy-live-lanes.mir
M llvm/test/CodeGen/AMDGPU/splitkit-getsubrangeformask.ll
M llvm/test/CodeGen/AMDGPU/splitkit-nolivesubranges.mir
M llvm/test/CodeGen/AMDGPU/sra.ll
M llvm/test/CodeGen/AMDGPU/sram-ecc-default.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-any.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-disabled.ll
M llvm/test/CodeGen/AMDGPU/sramecc-subtarget-feature-enabled.ll
M llvm/test/CodeGen/AMDGPU/srem.ll
M llvm/test/CodeGen/AMDGPU/srem64.ll
M llvm/test/CodeGen/AMDGPU/srl.ll
M llvm/test/CodeGen/AMDGPU/ssubo.ll
M llvm/test/CodeGen/AMDGPU/stack-pointer-offset-relative-frameindex.ll
M llvm/test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir
M llvm/test/CodeGen/AMDGPU/stale-livevar-in-twoaddr-pass.mir
M llvm/test/CodeGen/AMDGPU/store-barrier.ll
M llvm/test/CodeGen/AMDGPU/store-global.ll
M llvm/test/CodeGen/AMDGPU/store-hi16.ll
M llvm/test/CodeGen/AMDGPU/store-local.ll
M llvm/test/CodeGen/AMDGPU/store-private.ll
M llvm/test/CodeGen/AMDGPU/store-v3i64.ll
M llvm/test/CodeGen/AMDGPU/store-vector-ptrs.ll
M llvm/test/CodeGen/AMDGPU/store_typed.ll
R llvm/test/CodeGen/AMDGPU/strict_fp_casts.ll
M llvm/test/CodeGen/AMDGPU/strict_fpext.ll
M llvm/test/CodeGen/AMDGPU/strict_fptrunc.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f16.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f32.ll
M llvm/test/CodeGen/AMDGPU/strict_ldexp.f64.ll
A llvm/test/CodeGen/AMDGPU/strictfp_f16_abi_promote.ll
M llvm/test/CodeGen/AMDGPU/structurize.ll
M llvm/test/CodeGen/AMDGPU/structurize1.ll
M llvm/test/CodeGen/AMDGPU/sub.ll
M llvm/test/CodeGen/AMDGPU/sub.v2i16.ll
M llvm/test/CodeGen/AMDGPU/sub_i1.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-crash.ll
M llvm/test/CodeGen/AMDGPU/subreg-coalescer-undef-use.ll
M llvm/test/CodeGen/AMDGPU/subreg-intervals.mir
M llvm/test/CodeGen/AMDGPU/subreg-split-live-in-error.mir
M llvm/test/CodeGen/AMDGPU/subvector-test.mir
M llvm/test/CodeGen/AMDGPU/switch-unreachable.ll
M llvm/test/CodeGen/AMDGPU/swizzle-export.ll
M llvm/test/CodeGen/AMDGPU/tail-dup-bundle.mir
M llvm/test/CodeGen/AMDGPU/target-cpu.ll
M llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
M llvm/test/CodeGen/AMDGPU/texture-input-merge.ll
M llvm/test/CodeGen/AMDGPU/threeaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/token-factor-inline-limit-test.ll
M llvm/test/CodeGen/AMDGPU/trans-forwarding-hazards.mir
M llvm/test/CodeGen/AMDGPU/triv-disjoint-mem-access-neg-offset.mir
M llvm/test/CodeGen/AMDGPU/true16-ra-pre-gfx11-regression-test.mir
M llvm/test/CodeGen/AMDGPU/trunc-bitcast-vector.ll
M llvm/test/CodeGen/AMDGPU/trunc-cmp-constant.ll
M llvm/test/CodeGen/AMDGPU/trunc-combine.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-f64-to-f16.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i1.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-i64.ll
M llvm/test/CodeGen/AMDGPU/trunc-store-vec-i16-to-i8.ll
M llvm/test/CodeGen/AMDGPU/trunc-store.ll
M llvm/test/CodeGen/AMDGPU/trunc-vector-store-assertion-failure.ll
M llvm/test/CodeGen/AMDGPU/trunc.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-constrain.ll
M llvm/test/CodeGen/AMDGPU/twoaddr-fma-f64.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-fma.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-mad.mir
M llvm/test/CodeGen/AMDGPU/twoaddr-wmma.mir
M llvm/test/CodeGen/AMDGPU/uaddo.ll
M llvm/test/CodeGen/AMDGPU/udiv.ll
M llvm/test/CodeGen/AMDGPU/udiv64.ll
M llvm/test/CodeGen/AMDGPU/udivrem.ll
M llvm/test/CodeGen/AMDGPU/udivrem24.ll
M llvm/test/CodeGen/AMDGPU/udivrem64.r600.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.i64.ll
M llvm/test/CodeGen/AMDGPU/uint_to_fp.ll
M llvm/test/CodeGen/AMDGPU/uitofp.f16.ll
M llvm/test/CodeGen/AMDGPU/umed3.ll
M llvm/test/CodeGen/AMDGPU/unaligned-load-store.ll
M llvm/test/CodeGen/AMDGPU/undef-build-vector.ll
M llvm/test/CodeGen/AMDGPU/undef-copy-propagation.mir
M llvm/test/CodeGen/AMDGPU/undefined-subreg-liverange.ll
M llvm/test/CodeGen/AMDGPU/unhandled-loop-condition-assertion.ll
M llvm/test/CodeGen/AMDGPU/uniform-branch-intrinsic-cond.ll
M llvm/test/CodeGen/AMDGPU/uniform-cfg.ll
M llvm/test/CodeGen/AMDGPU/uniform-crash.ll
M llvm/test/CodeGen/AMDGPU/uniform-load-from-tid.ll
M llvm/test/CodeGen/AMDGPU/uniform-loop-inside-nonuniform.ll
M llvm/test/CodeGen/AMDGPU/uniform-phi-with-undef.ll
M llvm/test/CodeGen/AMDGPU/unigine-liveness-crash.ll
M llvm/test/CodeGen/AMDGPU/unknown-processor.ll
M llvm/test/CodeGen/AMDGPU/unpack-half.ll
M llvm/test/CodeGen/AMDGPU/unsupported-atomics.ll
M llvm/test/CodeGen/AMDGPU/unsupported-calls.ll
M llvm/test/CodeGen/AMDGPU/unsupported-cc.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-a16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-g16.ll
M llvm/test/CodeGen/AMDGPU/unsupported-image-sample.ll
M llvm/test/CodeGen/AMDGPU/urem.ll
M llvm/test/CodeGen/AMDGPU/urem64.ll
M llvm/test/CodeGen/AMDGPU/use-sgpr-multiple-times.ll
M llvm/test/CodeGen/AMDGPU/usubo.ll
M llvm/test/CodeGen/AMDGPU/v1024.ll
M llvm/test/CodeGen/AMDGPU/v1i64-kernel-arg.ll
M llvm/test/CodeGen/AMDGPU/v_add_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_cndmask.ll
M llvm/test/CodeGen/AMDGPU/v_cvt_pk_u8_f32.ll
M llvm/test/CodeGen/AMDGPU/v_mac.ll
M llvm/test/CodeGen/AMDGPU/v_mac_f16.ll
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expand_and_shrink.mir
M llvm/test/CodeGen/AMDGPU/v_mov_b64_expansion.mir
M llvm/test/CodeGen/AMDGPU/v_pack.ll
M llvm/test/CodeGen/AMDGPU/v_sat_pk_u8_i16.ll
M llvm/test/CodeGen/AMDGPU/v_sub_u64_pseudo_sdwa.ll
M llvm/test/CodeGen/AMDGPU/v_swap_b32.mir
M llvm/test/CodeGen/AMDGPU/valu-i1.ll
M llvm/test/CodeGen/AMDGPU/valu-mask-write-hazard.mir
M llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-set-kill.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx-wrong-kill-flags.mir
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.ll
M llvm/test/CodeGen/AMDGPU/vcmp-saveexec-to-vcmpx.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-exec-war-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard-sdwa.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane-hazard.mir
M llvm/test/CodeGen/AMDGPU/vcmpx-permlane16var-hazard.mir
M llvm/test/CodeGen/AMDGPU/vector-alloca.ll
M llvm/test/CodeGen/AMDGPU/vector-extract-insert.ll
M llvm/test/CodeGen/AMDGPU/vector-legalizer-divergence.ll
M llvm/test/CodeGen/AMDGPU/vectorize-global-local.ll
M llvm/test/CodeGen/AMDGPU/verify-constant-bus-violations.mir
M llvm/test/CodeGen/AMDGPU/verify-duplicate-literal.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx12-gds.mir
M llvm/test/CodeGen/AMDGPU/verify-gfx90a-aligned-vgprs.mir
M llvm/test/CodeGen/AMDGPU/verify-image.mir
M llvm/test/CodeGen/AMDGPU/verify-scalar-store.mir
M llvm/test/CodeGen/AMDGPU/verify-sop.mir
M llvm/test/CodeGen/AMDGPU/verify-vimage-vsample.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd-gfx12.mir
M llvm/test/CodeGen/AMDGPU/verify-vopd.mir
M llvm/test/CodeGen/AMDGPU/vertex-fetch-encoding.ll
M llvm/test/CodeGen/AMDGPU/vgpr-agpr-limit-gfx90a.ll
M llvm/test/CodeGen/AMDGPU/vgpr-descriptor-waterfall-loop-idom-update.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange-ir.ll
M llvm/test/CodeGen/AMDGPU/vgpr-liverange.ll
A llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.ll
A llvm/test/CodeGen/AMDGPU/vgpr-mark-last-scratch-load.mir
M llvm/test/CodeGen/AMDGPU/vgpr-remat.mir
M llvm/test/CodeGen/AMDGPU/vi-removed-intrinsics.ll
M llvm/test/CodeGen/AMDGPU/vmem-to-salu-hazard.mir
Log Message:
-----------
Merge branch 'main' into users/kparzysz/spr/a05-complete-createBodyOfOp
Compare: https://github.com/llvm/llvm-project/compare/9394b96f9672...00ad95a9211b
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