[all-commits] [llvm/llvm-project] 67e0f4: [dfsan] Make sprintf interceptor compatible with g...

Wed Jan 17 21:08:10 PST 2024

  Branch: refs/heads/users/vitalybuka/spr/ci-add-lld-as-compiler-rt-dependecy
  Home:   https://github.com/llvm/llvm-project
  Commit: 67e0f410ff2dbac83602357619a7c931518afc73
      https://github.com/llvm/llvm-project/commit/67e0f410ff2dbac83602357619a7c931518afc73
  Author: Fangrui Song <i at maskray.me>
  Date:   2024-01-17 (Wed, 17 Jan 2024)

  Changed paths:
    M compiler-rt/lib/dfsan/dfsan_custom.cpp
    M compiler-rt/test/dfsan/custom.cpp
    M compiler-rt/test/dfsan/release_shadow_space.c

  Log Message:
  -----------
  [dfsan] Make sprintf interceptor compatible with glibc 2.37+ and musl (#78363)

snprintf interceptors call `format_buffer` with `size==~0ul`, which
may eventually lead to `snprintf(s, n, "Hello world!")` where `s+n`
wraps around. Since glibc 2.37 (https://sourceware.org/PR30441), the
snprintf call does not write the last char. musl snprintf returns -1
with EOVERFLOW when `n > INT_MAX`.

Change `size` to INT_MAX to work with glibc 2.37+ and musl.
snprintf interceptors are not changed. It's user responsibility to not
cause a compatibility issue with libc implementations.

Fix #60678

  Commit: aa02002491333c42060373bc84f1ff5d2c76b4ce
      https://github.com/llvm/llvm-project/commit/aa02002491333c42060373bc84f1ff5d2c76b4ce
  Author: Tom Stellard <tstellar at redhat.com>
  Date:   2024-01-17 (Wed, 17 Jan 2024)

  Changed paths:
    M .github/workflows/release-binaries.yml
    A .github/workflows/release-documentation.yml
    A .github/workflows/release-doxygen.yml
    A .github/workflows/release-lit.yml
    M .github/workflows/release-tasks.yml
    M .github/workflows/set-release-binary-outputs.sh
    M llvm/utils/release/github-upload-release.py

  Log Message:
  -----------
  workflows: Refactor release-tasks.yml (#69523)

* Split out the lit release job and the documentation build job into
their own workflow files. This makes it possible to manually run these
jobs via workflow_dispatch.

* Improve tag/user validation and ensure it gets run for each release
task.

  Commit: f3a4de395c167aeb8207294222c6ff5719ef6f62
      https://github.com/llvm/llvm-project/commit/f3a4de395c167aeb8207294222c6ff5719ef6f62
  Author: Freddy Ye <freddy.ye at intel.com>
  Date:   2024-01-18 (Thu, 18 Jan 2024)

  Changed paths:
    M clang/test/CodeGen/target-builtin-noerror.c
    M clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/lib/TargetParser/X86TargetParser.cpp

  Log Message:
  -----------
  [X86] Support "f16c" and "avx512fp16" for __builtin_cpu_supports (#78384)

This resolves issue #65320.
This also supports clarify sapphirerapids and cooperlake for
cpu_specific/dispatch.

  Commit: 558ea411599a42d2a15dd6a878700cf62a8b36e7
      https://github.com/llvm/llvm-project/commit/558ea411599a42d2a15dd6a878700cf62a8b36e7
  Author: Stanislav Mekhanoshin <rampitec at users.noreply.github.com>
  Date:   2024-01-17 (Wed, 17 Jan 2024)

  Changed paths:
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll

  Log Message:
  -----------
  [AMDGPU] Reapply 'Sign extend simm16 in setreg intrinsic' (#78492)

We currently force users to use a negative contant in the intrinsic
call. Changing it zext would break existing programs, so just sign
extend an argument.

  Commit: f6617091a982c0802e9b980f2ce7e11a1355c38b
      https://github.com/llvm/llvm-project/commit/f6617091a982c0802e9b980f2ce7e11a1355c38b
  Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
  Date:   2024-01-18 (Thu, 18 Jan 2024)

  Changed paths:
    M llvm/test/CodeGen/X86/apx/adc.ll
    M llvm/test/CodeGen/X86/apx/add.ll
    M llvm/test/CodeGen/X86/apx/and.ll
    M llvm/test/CodeGen/X86/apx/or.ll
    M llvm/test/CodeGen/X86/apx/sbb.ll
    M llvm/test/CodeGen/X86/apx/sub.ll
    M llvm/test/CodeGen/X86/apx/xor.ll

  Log Message:
  -----------
  [X86][test] Add --show-mc-encoding for lowering tests of NDD arithmetic instructions (#78406)

#77564 added lowering tests for NDD arithmetic instructions.
It would be great to add `--show-mc-encoding` to check the NDD variant
is selected first.

  Commit: fff88f584eb757f966a9121e3d8704221de97291
      https://github.com/llvm/llvm-project/commit/fff88f584eb757f966a9121e3d8704221de97291
  Author: XinWang10 <108658776+XinWang10 at users.noreply.github.com>
  Date:   2024-01-17 (Wed, 17 Jan 2024)

  Changed paths:
    M .github/workflows/release-binaries.yml
    A .github/workflows/release-documentation.yml
    A .github/workflows/release-doxygen.yml
    A .github/workflows/release-lit.yml
    M .github/workflows/release-tasks.yml
    M .github/workflows/set-release-binary-outputs.sh
    M clang/test/CodeGen/target-builtin-noerror.c
    M clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M compiler-rt/lib/dfsan/dfsan_custom.cpp
    M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
    M compiler-rt/test/dfsan/custom.cpp
    M compiler-rt/test/dfsan/release_shadow_space.c
    M compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/lib/TargetParser/X86TargetParser.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/X86/apx/adc.ll
    M llvm/test/CodeGen/X86/apx/add.ll
    M llvm/test/CodeGen/X86/apx/and.ll
    M llvm/test/CodeGen/X86/apx/or.ll
    M llvm/test/CodeGen/X86/apx/sbb.ll
    M llvm/test/CodeGen/X86/apx/sub.ll
    M llvm/test/CodeGen/X86/apx/xor.ll
    M llvm/utils/release/github-upload-release.py

  Log Message:
  -----------
  [𝘀𝗽𝗿] changes introduced through rebase

Created using spr 1.3.4

[skip ci]

  Commit: e0b5094800081c1bbafcbb8e75a752d517eb1d71
      https://github.com/llvm/llvm-project/commit/e0b5094800081c1bbafcbb8e75a752d517eb1d71
  Author: Vitaly Buka <vitalybuka at google.com>
  Date:   2024-01-17 (Wed, 17 Jan 2024)

  Changed paths:
    M .github/workflows/release-binaries.yml
    A .github/workflows/release-documentation.yml
    A .github/workflows/release-doxygen.yml
    A .github/workflows/release-lit.yml
    M .github/workflows/release-tasks.yml
    M .github/workflows/set-release-binary-outputs.sh
    M clang/test/CodeGen/target-builtin-noerror.c
    M clang/test/CodeGenCXX/attr-cpuspecific-outoflinedefs.cpp
    M compiler-rt/lib/builtins/cpu_model/x86.c
    M compiler-rt/lib/dfsan/dfsan_custom.cpp
    M compiler-rt/lib/sanitizer_common/sanitizer_symbolizer_report.cpp
    M compiler-rt/test/dfsan/custom.cpp
    M compiler-rt/test/dfsan/release_shadow_space.c
    M compiler-rt/test/sanitizer_common/TestCases/allocator_returns_null.cpp
    M llvm/include/llvm/TargetParser/X86TargetParser.def
    M llvm/lib/Target/AMDGPU/SIInstrInfo.td
    M llvm/lib/Target/AMDGPU/SIModeRegister.cpp
    M llvm/lib/Target/AMDGPU/SOPInstructions.td
    M llvm/lib/TargetParser/X86TargetParser.cpp
    M llvm/test/CodeGen/AMDGPU/llvm.amdgcn.s.setreg.ll
    M llvm/test/CodeGen/X86/apx/adc.ll
    M llvm/test/CodeGen/X86/apx/add.ll
    M llvm/test/CodeGen/X86/apx/and.ll
    M llvm/test/CodeGen/X86/apx/or.ll
    M llvm/test/CodeGen/X86/apx/sbb.ll
    M llvm/test/CodeGen/X86/apx/sub.ll
    M llvm/test/CodeGen/X86/apx/xor.ll
    M llvm/utils/release/github-upload-release.py

  Log Message:
  -----------
  rebase

Created using spr 1.3.4

Compare: https://github.com/llvm/llvm-project/compare/05b1784a802e...e0b509480008