[all-commits] [llvm/llvm-project] 1fbf53: AMDGPU/GlobalISelDivergenceLowering: select diverg...

[Petar Avramovic via All-commits]

  Branch: refs/heads/main
  Home:   https://github.com/llvm/llvm-project
  Commit: 1fbf5332863e9f7319ce4a91931b2c4ab089d6bb
      https://github.com/llvm/llvm-project/commit/1fbf5332863e9f7319ce4a91931b2c4ab089d6bb
  Author: Petar Avramovic <Petar.Avramovic at amd.com>
  Date:   2024-01-17 (Wed, 17 Jan 2024)

  Changed paths:
    M llvm/include/llvm/CodeGen/MachineUniformityAnalysis.h
    M llvm/lib/CodeGen/MachineUniformityAnalysis.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUGlobalISelDivergenceLowering.cpp
    M llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
    M llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp
    M llvm/lib/Target/AMDGPU/SILowerI1Copies.h
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-phis-no-lane-mask-merging.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-divergent-i1-used-outside-loop.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-structurizer.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergence-temporal-divergent-i1.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/divergent-control-flow.ll
    M llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-phi.mir
    M llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.div.fmas.ll

  Log Message:
  -----------
  AMDGPU/GlobalISelDivergenceLowering: select divergent i1 phis (#76145)

Implement PhiLoweringHelper for GlobalISel in DivergenceLoweringHelper.
Use machine uniformity analysis to find divergent i1 phis and select
them as lane mask phis in same way SILowerI1Copies select VReg_1 phis.
Note that divergent i1 phis include phis created by LCSSA and all cases
of uses outside of cycle are actually covered by "lowering LCSSA phis".
GlobalISel lane masks are registers with sgpr register class and S1 LLT.

TODO: General goal is that instructions created in this pass are fully
instruction-selected so that selection of lane mask phis is not split
across multiple passes.

patch 3 from: https://github.com/llvm/llvm-project/pull/73337